CN102394719B - Multichannel HDLC data processing method based on FPGA - Google Patents

Abstract

The invention discloses a multichannel high-level data link control (HDLC) data processing method based on a field-programmable gate array (FPGA); and according to the method, an FPGA is utilized as a control processing core to realize processing on HDLC data. The method comprises the following steps that: data are input and are used as a serial data flow; meanwhile, a frame synchronization signal and a synchronization clock are provided; according to a high level link control mode, a state of six continuous ''1''s in a mode of '' 01111110''is detected and it is considered that a frame tag (FLAG) is detected; and during a subsequent bit stream, zero deletion and cyclic redundancy check (CRC) verification are carried out; after next FLAG data is detected, data integrity and correctness of a CRC check value are detected; a data packet is processed and the processed data packet is stored in a data memory; data of a sending data memory block are obtained at a sending side; and with regard to a state of five continuous ''1''s, one ''0'' is added; and meanwhile, a CRC check value is calculated; after the data are sent, obtained CRC check data are sent out together. According to the method, receiving and sending of multichannel HDLC data are realized and data with different rates are processed; simultaneously, CRC checking is carried out; and a data packet that has been processed is stored to an assigned data memory.

Description

Multichannel HDLC data processing method based on FPGA

Technical field:

The present invention relates to a kind of HDLC data processor, refer in particular to a kind of Multichannel HDLC data processing method based on FPGA of the E1 of being applied to TDM signal of communication.

Background technology:

E1 TDM refers to a kind of by the time division multiplexing of the intersection digit pulse in different channels or time slot, transmits the technology of a plurality of digitalized datas, voice and video signal etc. simultaneously on same communication medium.Support 2.048 Mbps communication links, it is divided into 32 time slots (every 32 time slots are E1 frame), at interval of being 64 kbps.

Senior link is controlled (High-Level Data Link Control or be called for short HDLC), be one at Synchronization Network transmitting data, bit-oriented data link layer protocol.Form as shown in Figure 1.

CRC is cyclic redundancy check (CRC) code (Cyclic Redundancy Check): be a kind of error check code the most frequently used in data communication field, it is characterized in that the length of information field and check field can be selected arbitrarily.

FPGA(Field-Programmable Gate Array), i.e. field programmable gate array.

Each HDLC frame is forward and backward all an identity code 01111110, as frame initial, stop the synchronous of indication and frame.Identity code does not allow to occur in the inside of frame, in order to avoid cause ambiguity.For guaranteeing the uniqueness of identity code but take into account the transparency of intraframe data, can adopt " 0 bit insertion " to solve.This method monitors all fields except identity code at transmitting terminal, when finding that there is continuously 5individual ' 1 ' when occur, just adding and inserting one ' 0 ' thereafter, then continues the bit stream of sending out follow-up.At receiving terminal, monitor equally all fields except beginning flag code.When continuous discovery 5after individual ' 1 ' appearance, if a bit ' 0 ' is deleted it automatically thereafter, to recover original bit stream; If find continuously 6individual ' 1 ', may be insert ' 0 ' occur that mistake becomes ' 1 ', may be also the termination flag code of having received frame.Latter two situation, can further be distinguished by the frame check sequence in frame.

What receive and send employing while carrying out data processing due to current existing HDLC is to carry out by turn processing mode or every 8 bits are processed, and the former processing method is owing to processing by turn, and the handling interrupt time is subject to the restriction of sample rate.The latter's processing method is: every 8 bits are processed, and company ' 1 ' number of statistics in the first eight bit also needs company's ' 1 ' number of searching for previous eight bits to judge the quantity that connects ' 1 ', and pending data carries out the verification of CRC after becoming bag again.The former this mode efficiency is lower, particularly for E1 TDM signal, independently, very inconvenient according to the processing of bit stream during due to the data of each time slot, is not suitable for high speed HDLC and processes; The latter interrupts the former sampling improving to some extent, reduced the frequency of interrupting, but when special ' 1 ' quantity of statistics continued proportion, also need to obtain the quantity of the company relevant with this 8bit ' 1 ', simultaneously when processing CRC, with becoming the data after bag to process calculating, the operand and the real-time that have increased FPGA are poor, have not well given play to the real-time advantage of high speed of FPGA.The HDLC that simultaneously above several processing modes all do not solve the different paths of different rates processes.

Summary of the invention:

The technical problem that the present invention solves has been to provide the method that the reception of the HDLC of a kind of a kind of E1 of being applied to TDM realizing with FPGA sends, and the processing that has solved the data flow of a plurality of passages and different rates, and has improved disposal ability and the stability of HDLC.

For solving the problems of the technologies described above, the present invention realizes by following steps: a kind of Multichannel HDLC data processing method based on FPGA, it is characterized in that, and on FPGA, realize the input and output of multiplex signal E1 tdm data code stream and the processing of HDLC data;

(1) frame synchronizing signal providing according to E1 TDM, sampling clock or the frame synchronizing signal of extracting according to data, FPGA by the data flow of serial be converted into multi-channel parallel data store into the upper appointment of FPGA double reception buffer area in;

The sequence number that the HDLC module of processing for HDLC data transmit-receive that each time slot of code stream is corresponding is set, different time-gap can arrange identical HDLC module; The upper HDLC module serial number register of FPGA of each time slot allocation, for the selection of HDLC module sequence number;

According to the low preceding order of eight hytes of sequence number, according to the sequence number of the HDLC module of appointment in the receiving register on corresponding FPGA, call HDLC module entrance, carry out the processing of data;

HDLC module receives the octet data (referring to Fig. 2) of corresponding time slot, compares by turn, connects ' 1 ' counting and processes;

When bit is ' 0 ', if there are 5 companies ' 1 ', this bit is rejected; Or there are 6 companies ' 1 ', illustrate and flag F LAG detected, judge the check results of CRC check circuit and the integrality of data;

If the normal bit receiving, puts into this significant bit in corresponding CRC check circuit, process a bit at every turn;

Each mode of processing a bit can all be assigned to the time of data processing each constantly, finally data is separately deposited in the reception buffer area on the FPGA of appointment;

(2) when data having been detected, need to send, eight hytes of each extraction, detect 5 companies ' 1 ', data add ' 0 ' below, through adding the data recombination after ' 0 ' processing, take out successively eight hytes wherein, and according to the HDLC module serial number register of corresponding time slot, be input to the HDLC resume module of appointment, the data after processing output to the transmission buffer area on corresponding FPGA;

When detecting 5 companies ' 1 ', each bit judge simultaneously, carry out CRC check circuit check, generation check code, until send last bit, adds CRC check circuit checks value according to data pattern to and sends.

The present invention is based on FPGA field programmable gate array and complete and from serial data to the processing of HDLC packet, delete ' 0 ' and process, carry out the generation of CRC check code simultaneously, and by raw data packets through inserting ' 0 ', to Packet Generation on serial data.Invented the convenient multichannel of realizing, the implementation of many speed, data are carried out to deal with data according to the mode of serial data frame packet simultaneously, solved each clock cycle can only process individual bit, and abandoned the drawback that bit is all processed in 8 hyte modes completely.The present invention can improve processing speed, has greatly brought into play the feature of the efficient real-time of fpga, meets at a high speed multichannel, the processing demands of multi-rate data.The technical scheme providing in the embodiment of the present invention also can be simultaneously for the parallel processing of different serial datas.The embodiment providing of the present invention is not limited to the FPGA of particular vendors.

Accompanying drawing explanation:

Fig. 1 is the HDLC frame data structure figure of reference of the present invention;

Fig. 2 is serial data stream and the clock signal of the definition of reference of the present invention;

Fig. 3 is that the present invention generates shift register action principle with reference to CRC-CCITT;

Fig. 4 is FPGA reception & disposal block diagram in the present invention;

Fig. 5 is FPGA transmission processing block diagram in the present invention.

Embodiment

In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below in conjunction with accompanying drawing, inventive embodiment is described in detail, scheme is below only embodiments of the invention, for those of ordinary skills, do not paying under the prerequisite of creative work, other accompanying drawing can also be provided according to the accompanying drawing providing.

A Multichannel HDLC data processing method based on FPGA, is characterized in that, realizes the input and output of multiplex signal E1 tdm data code stream and the processing of HDLC data on FPGA;

As shown in Figure 4, the string that receiving course arranges in FPGA also/parallel-to-serial converter, two buffer memory selector, 5 connect ' 1 ' comparators, 6 and connect ' 1 ' comparators, 7 and connect ' 1 ' comparators, delete zero processing, CRC check and data storing received and form;

Receiving course step is as follows:

Step T101: the circuit by the unification of E1 TDM serial data after going here and there and changing, the E1 frame data continuous 256bit that the data of totally 32 time slot 256bit are saved in appointment is received in buffer area, interface provides double reception buffer area, according to the order of frame, intersects and deposits;

Step T102: according to the corresponding HDLC module of user configured eight hytes, call HDLC reception & disposal, the receiving register corresponding according to different HDLC modules, can arrive different data distributions to specify HDLC module very easily, realizes the processing of multichannel processing and different rates;

Step T103: the data according to 256 bits of input, obtain bit 0, data are moved to left one and are convenient to obtain next time bit 0, the bit of obtaining is input to 5 and connects ' 1 ' comparator comparison, and result output a-signal is processed to deleting zero; A-signal is ' 0 ', illustrates that 5 companies ' 1 ' being detected equates, directly abandons this bit; Otherwise export this bit; Proceed to step T105;

Step T104: get after bit with step 3, be input to 6 and connect ' 1 ' comparator comparison, result output B signal is in data memory module, and whether indication flag of frame receives;

Be input to 7 simultaneously and connect ' 1 ' comparator comparison, whether result output C signal, in data memory module, indicates these frame data abnormal; Proceed to step T106;

Step T105: through the bit of step 3 output, be input to CRC and produce in displacement receiving register (as shown in Figure 3), obtain a new crc value, output to data memory module according to D signal;

Step T106: detect packet status signal, B signal, C signal and D signal;

When 7 companies ' 1 ' of C signal designation, forgo data bag being detected; After the bit getting, 8 hytes of recombinating, often obtain 8 hytes, judge B signal simultaneously, when indication detects flag of frame, think that HDLC packet finishes, and detect the integrality of data and check that according to D signal whether CRC check code is correct; Otherwise data storage.

As shown in Figure 5, the HDLC module selection, 5 that process of transmitting arranges in FPGA connects ' 1 ' comparator, CRC check circuit, zero-adding processing and parallel-to-serial converter and forms;

Process of transmitting step is as follows:

Step T201: obtain data from sending buffer area, and the HDLC module corresponding according to each time slot, obtain the data of corresponding HDLC module, obtain a bit in 8 hytes at every turn; Synchronously enter step 2 and 3;

Step T202: the data b it processing through step 1, enter into CRC check circuit and produce check code, after data are sent, the check code that CRC check circuit is produced adds to after data and sends together;

Step T203: the data b it processing through step 1, enter 5 and connect ' 1 ' comparator, judge whether data are 5 companies ' 1 ', provide and whether need zero-adding operation, after adding zero, this data bit is temporary in the HDLC module buffer memory of appointment;

Step T204: through the data after step 3, enter the transmission buffer area that displacement transmitter register outputs to 256 bits, use two buffer area cross-references that send;

Step T205: the mode with serial sends parallel-to-serial converter by the clock of the data based appointment after processing and synchronizing signal.

The present invention is based on FPGA field programmable gate array and complete and from serial data to the processing of HDLC packet, delete " 0 " and process, carry out the generation of CRC check code simultaneously, and by raw data packets through inserting " 0 ", to Packet Generation on serial data.Invented the convenient multichannel of realizing, the implementation of many speed, data are carried out to deal with data according to the mode of serial data frame packet simultaneously, solved each clock cycle can only process individual bit, and abandoned the drawback that bit is all processed in 8 hyte modes completely.The present invention can improve processing speed, has greatly brought into play the feature of the efficient real-time of fpga, meets at a high speed multichannel, the processing demands of multi-rate data.The technical scheme providing in the embodiment of the present invention also can be simultaneously for the parallel processing of different serial datas.The embodiment providing of the present invention is not limited to the FPGA of particular vendors.

The above, be only specific embodiment of the invention method, but protection scope of the present invention is not limited to this, with the protection range of claim, is as the criterion.

Claims (1)

1. the Multichannel HDLC data processing method based on FPGA, is characterized in that, realizes the input and output of multiplex signal E1 tdm data code stream and the processing of HDLC data on FPGA;

(1) string that receiving course arranges in FPGA also/parallel-to-serial converter, two buffer memory selector, 5 connect ' 1 ' comparators, 6 and connect ' 1 ' comparators, 7 and connect ' 1 ' comparators, delete zero processing, CRC check and data storing received and form;

Receiving course step is as follows:

Step T101: the circuit by the unification of E1 TDM serial data after going here and there and changing, the E1 frame data continuous 256bit that the data of totally 32 time slot 256bit are saved in appointment is received in buffer area, interface provides double reception buffer area, according to the order of frame, intersects and deposits;

Step T102: according to the corresponding HDLC module of user configured eight hytes, call HDLC reception & disposal, the receiving register corresponding according to different HDLC modules, can arrive different data distributions to specify HDLC module very easily, realizes the processing of multichannel processing and different rates;

Step T103: the data according to 256 bits of input, obtain bit 0, data are moved to left one and are convenient to obtain next time bit 0, the bit of obtaining is input to 5 and connects ' 1 ' comparator comparison, and result output a-signal is processed to deleting zero; A-signal is ' 0 ', illustrates that 5 companies ' 1 ' being detected equates, directly abandons this bit; Otherwise export this bit; Proceed to step T105;

Step T104: get after bit with step T103, be input to 6 and connect ' 1 ' comparator comparison, result output B signal is in data memory module, and whether indication flag of frame receives;

Be input to 7 simultaneously and connect ' 1 ' comparator comparison, whether result output C signal, in data memory module, indicates these frame data abnormal; Proceed to step T106;

Step T105: through the bit of step T103 output, be input to CRC and produce in displacement receiving register, obtain a new crc value, output to data memory module according to D signal;

Step T106: detect packet status signal, B signal, C signal and D signal;

When 7 companies ' 1 ' of C signal designation, forgo data bag being detected; After the bit getting, 8 hytes of recombinating, often obtain 8 hytes, judge B signal simultaneously, when indication detects flag of frame, think that HDLC packet finishes, and detect the integrality of data and check that according to D signal whether CRC check code is correct; Otherwise data storage;

(2) the HDLC module selection, 5 that process of transmitting arranges in FPGA connects ' 1 ' comparator, CRC check circuit, zero-adding processing and parallel-to-serial converter and forms;

Process of transmitting step is as follows:

Step T201: obtain data from sending buffer area, and the HDLC module corresponding according to each time slot, obtain the data of corresponding HDLC module, obtain a bit in 8 hytes at every turn; Synchronously enter step T202 and T203;

Step T202: the data b it processing through step T201, enter into CRC check circuit and produce check code, after data are sent, the check code that CRC check circuit is produced adds to after data and sends together;

Step T203: the data b it processing through step T201, enter 5 and connect ' 1 ' comparator, judge whether data are 5 companies ' 1 ', provide and whether need zero-adding operation, after adding zero, this data bit is temporary in the HDLC module buffer memory of appointment;

Step T204: the data after step T203, enter the transmission buffer area that displacement transmitter register outputs to 256 bits, use two buffer area cross-references that send;

Step T205: the mode with serial sends parallel-to-serial converter by the clock of the data based appointment after processing and synchronizing signal.

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