CN108259368A - A kind of data transmission system and method based on FPGA - Google Patents
A kind of data transmission system and method based on FPGA Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/12—Avoiding congestion; Recovering from congestion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
- H04L47/2458—Modification of priorities while in transit
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/31—Flow control; Congestion control by tagging of packets, e.g. using discard eligibility [DE] bits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/625—Queue scheduling characterised by scheduling criteria for service slots or service orders
- H04L47/6275—Queue scheduling characterised by scheduling criteria for service slots or service orders based on priority
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Abstract
This application discloses a kind of data transmission system and method based on FPGA, which includes input terminal data-interface, virtual channel management module, multiple virtual channels, arbitration modules and output terminal data-interface.The data transmission method includes：Data packet is obtained, according to the packet header of data packet, different data packets is respectively stored into different virtual channels；Finally according to the priority orders of virtual channel, data packet output is carried out.By the system and method in the embodiment of the present application, FPGA high speed data transmission efficiencys can be greatly improved, improve the utilization rate of interface and bus, effectively avoid the data overflow problem in single channel transmission.
Description
Technical Field
The present application relates to the field of chip design technologies, and in particular, to a data transmission system and method based on an FPGA.
Background
Because the FPGA has the advantages of high speed, high efficiency, flexibility, stability, high integration level, and capability of being repeatedly reconfigured, the FPGA is often used as a platform to design high-speed data transmission in the field of chip design. In the same FPGA chip platform, different data transmission systems can be designed by adopting different data transmission methods according to the requirements of users.
The existing data transmission system and method generally include that an uplink interface is generally of an on-chip bus structure, an uplink line of an FPGA chip is connected with a CPU, a downlink line of the FPGA chip is connected with a controller terminal and other devices, data is transmitted in the FPGA chip through a single line, and when the data volume is large, the CPU is used for adjusting the data transmission sequence.
However, when the existing data transmission system and method are adopted, because the data is transmitted by a single line in the chip bus interface transmission process of the FPGA chip, the input clock frequency is low, generally 100Mhz to 200Mhz, but more functional modules are arranged in an uplink; the output clock frequency is higher, generally 4Ghz, and the clock frequency difference between the input and output ends is larger. That is to say, the transmission rate of the uplink data is low, but the number of the uplink functional modules is large, and the transmission rate of the downlink data is high, so that the uplink functional modules frequently enter an idle state, the bus utilization rate is low, and the data transmission efficiency is low.
Disclosure of Invention
The application provides a data transmission system and method based on an FPGA (field programmable gate array), which aim to solve the problems that an uplink function module frequently enters an idle state and the data transmission efficiency is low in the prior art.
In order to solve the technical problem, the embodiment of the application discloses the following technical scheme:
a Field Programmable Gate Array (FPGA) -based data transmission system, the data transmission system comprising: the device comprises an input end data interface, a virtual channel management module, a plurality of virtual channels, an arbitration module and an output end data interface; wherein,
the virtual channel management module is configured to obtain a data packet from the input end data interface, store different data packets in different virtual channels according to packet headers of the data packets, read the data packet in the virtual channel, and output the data packet to the arbitration module;
the arbitration module is used for arbitrating the priority of the virtual channel and transmitting the data packet to an output end data interface according to the priority sequence of the virtual channel.
Optionally, the virtual channel management module is further configured to add a unique ID to different data packets when the different data packets are stored in the same virtual channel;
the arbitration module is also used for arbitrating the priorities of different data packets in the same virtual channel according to the IDs of the data packets and transmitting data according to the priority sequence of the data packets.
Optionally, the arbitration module is further configured to arbitrate priorities of different data packets in the same virtual channel according to the IDs of the data packets, so that the data packet with the ID before is transmitted preferentially.
Optionally, the data transmission system further includes a redundant virtual channel for temporarily storing the data packet in a cyclic manner.
Optionally, the virtual channel management module is further configured to detect a remaining storage space of the multiple virtual channels, and store a next data packet in any one of the multiple virtual channels into the redundant virtual channel when the storage space of any one of the multiple virtual channels is not enough to store the data packet continuously.
Optionally, the virtual channel is a buffer register generated by using a catalog ip tool.
A data transmission method based on FPGA comprises the following steps:
acquiring a data packet;
storing different data packets into different virtual channels respectively according to the packet headers of the data packets;
and outputting the data packets according to the priority order of the virtual channels.
Optionally, the method further includes storing different data packets in different virtual channels according to the packet headers of the data packets, and specifically includes the following steps:
when different data packets are stored in the same virtual channel, unique IDs are added to the different data packets respectively;
and arbitrating the different data packets according to the ID, and determining the priority order of the different data packets in the same virtual channel.
Optionally, after storing different data packets into different virtual channels respectively according to the packet headers of the data packets, the method further includes:
detecting the residual storage space of the virtual channel;
when the residual storage space of the virtual channel is not enough to store data packets continuously, temporarily storing the data packets which cannot be stored into a redundant virtual channel, wherein the redundant virtual channel is used for temporarily storing the data packets in a cyclic use mode;
and releasing the redundant virtual channel after the data packet which cannot be stored is output.
Optionally, the virtual channel is a buffer register generated by using a catalog ip tool.
The technical scheme provided by the embodiment of the application can have the following beneficial effects:
the application provides a data transmission system based on FPGA, and the data transmission system comprises an input end data interface, a virtual channel management module, a plurality of virtual channels, an arbitration module and an output end data interface. After the data packets are acquired through the data interface of the input end, the virtual channel management module respectively stores different data packets into different virtual channels according to packet headers of the data packets, then reads the data packets in the virtual channels and outputs the data packets to the arbitration module, the arbitration module carries out forced arbitration on the priority of the virtual channels, and the data packets are transmitted to the data interface of the output end according to the priority sequence of the virtual channels. The multi-pass multi-channel transmission device is provided with the virtual channels, each virtual channel corresponds to one functional module in the FPGA, the multiple virtual channels can be arranged to realize multi-pass multi-channel transmission in uplink data transmission, the phenomena that in the prior art, single-channel data packets are removed in the data transmission process, and the uplink functional modules frequently enter an idle state are avoided, and therefore data transmission efficiency is greatly improved. The virtual channel management module can store different data packets into different virtual modules according to packet headers of the data packets, so that the virtual channels and the data packets are in one-to-one correspondence, the data in the virtual channels are controlled to be transmitted to the arbitration module, the subsequent arbitration module is favorable for processing the data in the virtual channels, and the data transmission efficiency is improved. The arbitration module can perform priority sequencing on the plurality of virtual channels, so that the data blockage phenomenon caused by the arrangement of the plurality of virtual channels is avoided, and the data transmission efficiency is improved.
The application provides a data transmission method based on FPGA, firstly, a data packet is obtained, and then different data packets are respectively stored in different virtual channels according to the packet head of the data packet; and finally, outputting the data packets according to the priority order of the virtual channels. According to the embodiment of the application, the acquired data packets are respectively stored in different virtual channels, so that multi-stroke and multi-channel data transmission can be realized, and the data transmission efficiency of the input end is greatly improved. The virtual channels are forcibly arbitrated, and data packets are output according to the priority order of the virtual channels, so that the phenomenon of data packet blockage can be effectively avoided, and the data transmission efficiency is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an FPGA-based data transmission system according to an embodiment of the present disclosure;
fig. 2 is a schematic flowchart of a data transmission method based on an FPGA according to an embodiment of the present disclosure;
fig. 3 is a schematic flowchart of another FPGA-based data transmission method according to an embodiment of the present application.
The symbols represent:
1-input end data interface, 2-virtual channel management module, 3-virtual channel, 4-arbitration module, and 5-output end data interface.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The FPGA is a semi-custom circuit in the field of application specific integrated circuits, and has the advantages of high speed, high efficiency, flexibility, stability, high integration level, repeated reconfiguration and the like, so in the field of chip design, the FPGA is usually adopted to realize the design of high-speed data transmission. In addition, the FPGA can also be used as a small-scale trial production before official tape-out, and is still an excellent platform for research and development design due to the existence of a solidified functional module and various types of common IP inside the FPGA. In the embodiment of the present application, an Altera cycle v type FPGA is taken as an example.
A virtual channel is a communication circuit that can transport ATM (asynchronous transfer Mode) cells between two or more endpoints. The virtual path between the endpoints may be a user-to-user connection, a user-to-network connection, or a network-to-network connection.
For a better understanding of the present application, embodiments of the present application are explained in detail below with reference to the accompanying drawings.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of an FPGA-based data transmission system applied in the embodiment of the present application. As can be seen from fig. 1, the data transmission system in the embodiment of the present application mainly includes: the input end data interface 1, the virtual channel management module 2, the plurality of virtual channels 3, the arbitration module 4 and the output end data interface 5. The virtual channel management module 2 is configured to obtain a data packet from the input end data interface 1, where data of different packet headers are stored in the data packet in the embodiment of the present application; after acquiring the data packet, the virtual channel management module 2 stores different data packets into different virtual channels 3 according to the packet header of the data packet, and the virtual channel management module 2 is further configured to read the data packet in the virtual channel 3 and output the data packet to the arbitration module 4. The arbitration module 4 is configured to arbitrate the priority of the virtual channel 3, and transmit the data packet to the output end data interface according to the priority order of the virtual channel 3.
The input end data interface 1 acquires a data packet from an upper stage, transmits the data packet to the virtual channel management module 2 at first, and the virtual channel management module 2 processes the data packet and then transmits the data packet to different virtual channels 3. Specifically, the virtual channel management module 2 classifies the data packets according to the packet headers of the acquired data packets, the packet headers specify the functional modules in the FPGA to which the data packets correspond, different data packets are respectively stored in different virtual channels 3 through the virtual channel management module 2, so that one-to-one correspondence between different functional modules and different virtual channels can be realized, and the data packets of different functional modules are transmitted through the corresponding virtual channels, thereby realizing partition management of different functional modules in the FPGA and facilitating improvement of data transmission efficiency.
The setting of a plurality of virtual channels 3 in the embodiment of the application is logically equivalent to transmitting data through a multi-stroke multi-channel, and the phenomenon that only single-channel data is transmitted in uplink data transmission can be avoided, so that the data transmission efficiency is greatly improved. The virtual channel 3 in the embodiment of the present application is implemented by using a multi-RAM (Random Access Memory) cache manner. The virtual channel 3 in the embodiment of the present application may be configured as a buffer register generated by using a catalog ip tool, that is, a RAM generated by using the catalog ip tool is used to replace a buffer register in the prior art.
As can be seen from fig. 1, the data transmission system according to the embodiment of the present application further includes an arbitration module 4. The virtual channel management module 2 stores different data packets into different virtual channels 3, and then reads the data packets in the virtual channels 3 and outputs the read data packets to the arbitration module 4. After acquiring the data packets in the different virtual channels 3, the arbitration module 4 arbitrates the priorities of the virtual channels 3, that is, forcibly arbitrates the priorities of the multiple virtual channels. For example, in a data transmission system having three virtual channels 3, VC0, VC1, and VC2, the arbitration module 4 can specify the priority order of the three virtual channels as: VC0 is greater than VC1 is greater than VC2, namely, a data packet in a VC0 channel is transmitted to an output end data interface 5, then the data packet in a VC1 channel is transmitted to the output end data interface 5, and finally the data packet in a VC2 channel is transmitted to the output end data interface 5. The arbitration module 4 can avoid the data blockage phenomenon caused by the simultaneous transmission of data packets by the virtual channels 3, and is beneficial to improving the data transmission efficiency.
Further, since each virtual channel 3 may store a plurality of different data packets, the virtual channel management module 2 in this embodiment is further configured to add a unique ID to different data packets when the different data packets are stored in the same virtual channel 3. Correspondingly, the arbitration module 4 is further configured to arbitrate priorities of different data packets in the same virtual channel 3 according to the IDs of the data packets, and perform data transmission according to the priority order of the data packets. According to the embodiment of the application, the virtual channel management module 2 and the arbitration module 4 are arranged, the transmission problem of data packets in a single virtual channel 3 can be effectively solved, the data blockage phenomenon is effectively avoided, and the improvement of the data transmission efficiency is facilitated.
In addition, in order to adapt to the situation of large-amount high-speed data transmission, a redundant virtual channel is further arranged in the embodiment of the application and used for temporarily storing the data packet in a recycling mode. That is to say, the redundant virtual channel in the embodiment of the present application is only used to replace the virtual channel 3 to temporarily store the data packet, and does not fixedly replace a certain virtual channel to store the data.
When the storage space of the virtual channel 3 is insufficient, the data transmission system in the embodiment of the present application starts a redundant virtual channel through the virtual channel management module 2. Therefore, the virtual channel management module 2 in this embodiment is further configured to detect the remaining storage space of the multiple virtual channels 3, and store the next data packet in any one of the multiple virtual channels 3 into the redundant virtual channel when the storage space of the any one virtual channel is not enough to continue to store the data packet. When the data packet temporarily stored in the redundant virtual channel is transmitted, the redundant virtual channel is released and continues to be used as a standby virtual channel of the virtual channel, the other storage space of which is not enough to continue storing the data packet.
In this embodiment of the present application, the virtual channel management module 2 may refer to the length of the data packet and the depth of the virtual channel 3, based on a criterion that detects whether the remaining storage space of the plurality of virtual channels 3 is enough to continue storing the data packet. Namely: when the length of the data packet to be stored is larger than the depth of the virtual channel 3, judging that the residual storage space of the virtual channel 3 is insufficient; when the length of the data packet to be stored is less than or equal to the depth of the virtual channel 3, it is determined that the remaining storage space of the virtual channel 3 is sufficient.
Example two
Referring to fig. 2, fig. 2 is a schematic flowchart of a data transmission method based on an FPGA according to an embodiment of the present application. As can be seen from fig. 2, the data transmission method in the embodiment of the present application mainly includes the following steps:
s1: and acquiring the data packet.
The data packet of the embodiment of the application stores data of different packet headers. The packet headers of the data packets specify the functional modules in the FPGA corresponding to the data packets, that is, by looking at the packet headers of the data packets, it is possible to know which functional module in the FPGA uplink channel the data packet comes from.
S2: and respectively storing different data packets into different virtual channels according to the packet headers of the data packets.
In the embodiment of the application, different virtual channels have different priority orders. In order to improve the data transmission efficiency in the uplink data transmission channel, different data packets are respectively stored in different virtual channels, which is equivalent to adopting a multi-stroke multi-channel to transmit data, and the data transmission efficiency can be greatly improved.
In addition, through step S2, the data packets of different function modules are transmitted through the corresponding virtual channels, so that partition management of different function modules in the FPGA can be realized, and improvement of data transmission efficiency is facilitated.
Since a plurality of data packets are stored in the same virtual channel, step S2 further includes the following steps:
s21: when different data packets are stored in the same virtual channel, unique IDs are added to the different data packets respectively.
S22: and arbitrating different data packets according to the added ID, and determining the priority order of the different data packets in the same virtual channel.
As can be seen from steps S21-S22, different data packets in the embodiment of the present application also have priority orders in the same virtual channel, and this method can avoid data congestion during data packet transmission in a single virtual channel, thereby effectively improving the efficiency of data transmission.
As can be seen from fig. 2, after storing different packets in different virtual channels, the process proceeds to step S6: and outputting the data packets according to the priority order of the virtual channels.
Since the plurality of virtual channels simultaneously perform data transmission in step S2, in order to avoid data congestion when reading the virtual channels subsequently, the embodiment of the present application reads the data according to the priority order of the virtual channels.
The principle of data transmission in the embodiment of the present application has been described in detail in the first embodiment shown in fig. 1, and the two may be referred to each other and will not be described again.
EXAMPLE III
Referring to fig. 3 on the basis of the embodiment shown in fig. 2, fig. 3 is a schematic flowchart of another FPGA-based data transmission method applied in the embodiment of the present application.
As can be seen from fig. 3, in the embodiment of the present application, between step S2 and step S6, the following steps are further included:
s3: the remaining storage space of the virtual channel is detected.
S4: when the residual storage space of the virtual channel is not enough to store the data packets continuously, the data packets which cannot be stored are temporarily stored in the redundant virtual channel. The redundant virtual channel is used for temporarily storing the data packet in a cyclic use mode.
S5: and releasing the redundant virtual channel after the data packet which cannot be stored is output.
As can be seen from the foregoing steps S3-S5, in the embodiment of the present application, redundant storage is performed by detecting the remaining storage space of the virtual channel, so that data congestion caused by insufficient storage space of the virtual channel in high-speed data transmission is avoided, the efficiency of data transmission can be further improved, and the resource utilization rate of the FPGA is favorably improved. In addition, the redundant virtual channels in the embodiment of the application are used in a cyclic manner, that is, the redundant virtual channels do not fixedly replace a certain virtual channel for data storage, but the use of the redundant virtual channels is flexibly adjusted according to the detection condition of the residual storage space of each virtual channel, which is beneficial to flexible scheduling of resources.
The parts of the embodiment not described in detail can refer to the first embodiment and the second embodiment shown in fig. 1 and 2, and they can be referred to each other, and will not be described in detail herein.
The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. An FPGA-based data transmission system, comprising: the device comprises an input end data interface (1), a virtual channel management module (2), a plurality of virtual channels (3), an arbitration module (4) and an output end data interface (5); wherein,
the virtual channel management module (2) is configured to acquire a data packet from the input end data interface (1), store different data packets into different virtual channels (3) according to packet headers of the data packets, and read the data packet in the virtual channel (3) and output the data packet to the arbitration module (4);
the arbitration module (4) is configured to arbitrate the priority of the virtual channel (3), and transmit the data packet to an output end data interface (5) according to the priority order of the virtual channel (3).
2. The FPGA-based data transmission system of claim 1, wherein the virtual channel management module (2) is further configured to add a unique ID to different data packets when the different data packets are stored in the same virtual channel (3);
the arbitration module (4) is further used for arbitrating the priorities of different data packets in the same virtual channel (3) according to the IDs of the data packets, and transmitting data according to the priority sequence of the data packets.
3. The FPGA-based data transmission system of claim 1, further comprising a redundant virtual channel for temporarily storing data packets in a cyclic manner.
4. The FPGA-based data transmission system according to claim 3, wherein the virtual channel management module (2) is further configured to detect a remaining storage space of the plurality of virtual channels (3), and store a next data packet in any one of the plurality of virtual channels (3) into the redundant virtual channel when the storage space of the any one of the plurality of virtual channels is not enough to store the data packet.
5. An FPGA-based data transmission system according to any of claims 1-4, characterized in that the virtual channel (3) is a buffer register generated by using catalog ip tool.
6. A data transmission method based on FPGA is characterized by comprising the following steps:
acquiring a data packet;
storing different data packets into different virtual channels respectively according to the packet headers of the data packets;
and outputting the data packets according to the priority order of the virtual channels.
7. The FPGA-based data transmission method according to claim 6, wherein different data packets are respectively stored in different virtual channels according to the packet headers of the data packets, and the method specifically comprises the following steps:
when different data packets are stored in the same virtual channel, unique IDs are added to the different data packets respectively;
and arbitrating the different data packets according to the ID, and determining the priority order of the different data packets in the same virtual channel.
8. The FPGA-based data transmission method according to claim 6, wherein after storing different data packets into different virtual channels according to the packet headers of the data packets, the method further comprises:
detecting the residual storage space of the virtual channel;
when the residual storage space of the virtual channel is not enough to store data packets continuously, temporarily storing the data packets which cannot be stored into a redundant virtual channel, wherein the redundant virtual channel is used for temporarily storing the data packets in a cyclic use mode;
and releasing the redundant virtual channel after the data packet which cannot be stored is output.
9. The FPGA-based data transmission method according to any one of claims 6 to 8, wherein the virtual channel is a buffer register generated by using a catalog ip tool.
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| CN110659232A (en) * | 2019-09-12 | 2020-01-07 | 苏州浪潮智能科技有限公司 | Event information transmission method, device, equipment and storage medium |
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