CN105049377B - AFDX exchange datas bus structures and method for interchanging data based on Crossbar frameworks - Google Patents
AFDX exchange datas bus structures and method for interchanging data based on Crossbar frameworks Download PDFInfo
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- CN105049377B CN105049377B CN201510504766.8A CN201510504766A CN105049377B CN 105049377 B CN105049377 B CN 105049377B CN 201510504766 A CN201510504766 A CN 201510504766A CN 105049377 B CN105049377 B CN 105049377B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/102—Packet switching elements characterised by the switching fabric construction using shared medium, e.g. bus or ring
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
Abstract
The present invention provides a kind of AFDX interchangers for shared storage mode, improve the speed of interchanger internal data store forwarding, time of the data frame by interchanger is reduced, ensure that the AFDX exchange datas bus structures and method for interchanging data based on Crossbar frameworks of the service quality of AFDX interchangers.The present invention is not in the case where changing its dispatching algorithm, using Crossbar frameworks, coordinate separation to original global storage and with the one-to-one corresponding of bus host module, realize that each bus host module can have access to arbitrary bus slave computer module, i.e., each host module can form data path with each switch ports themselves；Bus slave computer module caches with reception, the transmission of each port to be connected, and it is operated initiates by bus host module, completes to read or write caching；The quantity of memory module is more, and storage forwarding rate can be higher, realizes the parallel transmission of multiple port datas.
Description
Technical field
The present invention relates to the method that AFDX exchange datas bus and interchanger internal data store forward, specially it is based on
The AFDX exchange datas bus structures and method for interchanging data of Crossbar frameworks.
Background technology
AFDX interchangers widely use the shared exchanged form stored to realize the function of exchange of its data frame, data at present
Bus is to connect switch ports themselves and the pith of shared memory.It is currently based in the AFDX interchangers of shared storage all only
There is a shared memory, data/address bus realizes the connection of shared memory and each port, and the data frame of each port is equal
Stored or forwarded in this unique memory.
A kind of AFDX exchange datas bus structures (Wang Bin text aviation full-duplex Ethernets based on Wishbone buses
Some key technology research of interchanger are with realizing [D] Xi'an:Xian Electronics Science and Technology University, 2008.) using the side of one master and multiple slaves
Formula, the corresponding shared memory of host computer control, slave control the input into/output from cache of each port, realize multiple ports together
Enjoy the connecting path of memory.The major defect of this scheme is：Only allow at any one time be up to a pair of main equipments and from
Equipment is communicated by bus, i.e., the data that synchronization can only have a port are stored or forwarded, so as to limit
The speed of interchanger internal data store forwarding.
A kind of AFDX interchangers (Chinese patent CN201410268433) using dual port shared memory, pass through raising
The bit wide of data/address bus, read-write operation is realized using dual-ported memory, improve the speed of data storage forwarding.This scheme
Major defect be：Data/address bus bit wide is too big (512), and data/address bus control signal is too many, easily causes subsequent placement wiring
Difficulty, be both that can also influence system global reliability.
A kind of AFDX network switch (Chinese patent CN201310037668) with space-time stalling characteristic is proposed to handing over
Each output port changed planes matches somebody with somebody one piece of internal memory and a sub- scheduler, by the data frame of each output port by corresponding to this
The sub- scheduler of output port is scheduled, and is then deposited in the internal memory corresponding to the output port, finally from the output end
Mouth is sent.The major defect of this scheme is：Hardware consumption is larger, for N number of port interchanger need N blocks internal memory and
2N DMA；Conventional scheduling algorithms are changed, therefore data bus structure is complex.
In existing technology, design structure based on shared storage is convenient, and hardware cost is low and hardware utilization
Height, so the development of its technology is very ripe.In AFDX interchangers based on shared storage mode, do not changing the feelings of dispatching algorithm
Under condition, the scheme that exchange data stores forwarding rate is improved by improving data bus structure, it is contemplated that cost and engineering
Practicality, still there is certain defect, and exploitativeness is poor.
The content of the invention
For problems of the prior art, the present invention provides a kind of AFDX interchangers for shared storage mode,
The speed of interchanger internal data store forwarding is improved, reduces time of the data frame by interchanger, ensure that AFDX is handed over
The AFDX exchange datas bus structures and method for interchanging data based on Crossbar frameworks for the service quality changed planes.
The present invention is to be achieved through the following technical solutions：
The AFDX exchange data bus structures based on Crossbar frameworks of the invention, including with switch ports themselves quantity phase
Deng bus slave computer module, a bus interconnection module, the equal bus host module of quantity, memory control module and storage
Device module, and a scheduling selecting module；The quantity of bus host module is not more than the quantity of bus slave computer module；
Each bus host module is mutual using Crossbar frameworks and each bus slave computer module by bus interconnection module
Even；Each bus host module respectively by memory control module connect corresponding to memory module；Each bus host mould
Block connects interchanger scheduling result FIFO by dispatching selecting module.
Preferably, dispatch selecting module include being connected in turn address discrimination module on interchanger scheduling result FIFO and
Instruction sending module；
Address discrimination module is used to extract scheduling result from interchanger scheduling result FIFO, obtains the end to be swapped
Mouth and memory module；
Instruction sending module is used for the bus host module 3 that obtained scheduling result is sent to corresponding ports.
Preferably, switch ports themselves number is 16, and the quantity of bus host module is 4；Storage in memory module
Space is divided into several pages, and every page of capacity is 2KBytes.
The method for interchanging data of AFDX exchange data bus structures of the invention based on Crossbar frameworks, using this hair
Bright described data bus structure, comprises the following steps,
Step 1, information of the scheduling selecting module in interchanger scheduling result FIFO, reads AFDX interchangers and produces
Scheduling result, judge port and the memory module to be swapped, and by the scheduling knot comprising memory address signal
Fruit be sent to should memory module bus host module；
Step 2, complete scheduling selecting module after sending and judge next scheduling result；If the end currently to be swapped
Slogan and memory module differ with previous scheduling result, and corresponding host module is idle, then directly will be current
Scheduling result is sent to corresponding bus host module, then repeat step two；Otherwise, wait corresponding bus host module empty
Spare time, then processing is transmitted to scheduling result；
Step 3, the bus host module for receiving scheduling result are completed to memory module by memory control module
Control accesses, and completes the storage or forwarding of data；Scheduling one feedback signal of selecting module, mark can be given after once-through operation is completed
Its state of will is the free time.
Preferably, in addition to first bus host module, spare bus host module is completed by memory control module
When control to memory module accesses, the memory address information received is changed as follows,
The maximum address of the original address-* memory modules of new address=memory module of memory module；
Wherein, m is the numbering that memory module corresponds to bus host module, and the original address of memory module is tied for scheduling
Storage initial address in fruit FIFO.
Preferably, interchanger scheduling result FIFO includes read operation signal, write operation signal, port numbers, caching number, frame
Long and storage starting address signal.
Compared with prior art, the present invention has technique effect beneficial below：
The present invention, using Crossbar frameworks, coordinates to original global storage in the case where not changing its dispatching algorithm
The separation of device and with the one-to-one corresponding of bus host module, realize that each bus host module can have access to arbitrary bus
Slave module, i.e., each host module can form data path with each switch ports themselves；Bus slave computer module with it is each
The reception of port, transmission caching are connected, and it is operated initiates by bus host module, completes to read or write caching；Memory
The quantity of module is more, and storage forwarding rate can be higher, and ideally, maximum speed-up ratio S=M, so as to
Significantly improve the speed of AFDX interchangers internal data store forwarding；The AFDX interchangers based on shared storage can be applied to
Inside, switch ports themselves and a plurality of data path of shared memory are realized, so as to realize the parallel transmission of multiple port datas.
Further, scheduling result is analyzed due to dispatching selecting module in the present invention, by actively selecting machine
System so that when the Crossbar frameworks of use are realized and exchanged, it is no longer necessary to arbitration modules, need to only realize logical between slave
Road, hardware consumption is greatly reduced, save cost.
Further, it is original so as to not influence by realizing the conversion to appropriate address in corresponding bus host module
The algorithm structure of system, and digital independent and unloading speed are improved, it is simple in construction, it is easy to operate.
Brief description of the drawings
Fig. 1 is the structured flowchart of the data bus structure described in present example.
Fig. 2 is the switching fabric logic diagram of Crossbar frameworks of the present invention.
In figure：1 is bus slave computer module, and 2 be bus interconnection module, and 3 be bus host module, and 4 be that memory controls mould
Block, 5 be memory module, and 6 be scheduling selecting module, and 6A is address discrimination module, and 6B is instruction sending module.
Embodiment
With reference to specific embodiment, the present invention is described in further detail, it is described be explanation of the invention and
It is not to limit.
AFDX exchange data bus structures of the invention based on Crossbar frameworks, are not changing the feelings of its dispatching algorithm
Under condition, it is contemplated that hardware cost and design complexities, data bus structure is carried out based on Crossbar and piecemeal memory technology
Improve.As shown in figure 1, including with lower module：M bus host module (Bus Master), N number of bus slave computer module (Bus
Slave, its quantity are equal with switch ports themselves number), a bus interconnection module (Bus Interconnection), M storage
Device control module (Memory Controller), M memory module (Memory) and a scheduling selecting module
(Scheduler)。
Wherein, the quantity of bus slave computer module 1 is N, identical with switch ports themselves number, is sent out with bus interconnection module and port
Send, order caching is connected.The quantity of bus interconnection module 2 is 1, and inside connects each bus slave computer using Crossbar switching fabrics
Module 1 and bus host module 3.The quantity of bus host module 3 is M, and mould, 4, bus interconnection module 2 and tune are controlled with memory
Selecting module 6 is spent to be connected.The quantity of memory control module 4 is M, is connected with host module and memory module.Memory module 5
Quantity is M, controls mould by memory, 4 control it.It is 1 to dispatch the quantity of selecting module 6, with scheduling result FIFO and respectively
Individual bus host module 3 is connected；Its internal address discrimination module 6A output end connects each bus host module 3 respectively, refers to
Make sending module 6B input scheduling result FIFO connections.Dotted line internal structure is data/address bus knot proposed by the invention
Structure, dotted line outside are other modules inside connected interchanger, and wherein Buffer refers to the transmission of switch ports themselves, received
Caching, FIFO refer to scheduling result FIFO caused by scheduler module in interchanger.
In order to it is more accurate, this bus structures and technical concept are more clearly described, with switch ports themselves number N=16, bus
Illustrate exemplified by host module number M=4.The data for having multiple ports to realize the same time can be carried out with shared memory
Exchange, be connected to using 4 bus host modules 3 in same bus interconnection module 2,16 bus slave computer modules 1 also connect
On that module.Each bus host module 3 is interconnected with bus slave computer module 1 by the way of Crossbar.So
Structure in, it is as shown in Fig. 2 each bus host module 3 can have access to arbitrary bus slave computer module 1, i.e., each total
Line host module 3 can form data path with each switch ports themselves.The reception of bus slave computer module 1 and each port,
Send caching to be connected, its operation is initiated by bus host module 3, completes to read or write caching.
Piecemeal is carried out to shared memory using the thought of piecemeal storage.Memory piecemeal refers to less be deposited with some pieces
For reservoir come one piece of larger memory before replacing, the memory after our piecemeals is referred to as quantum memory, i.e., respectively with bus
Memory module 5 corresponding to host module 3.The quantity of memory piecemeal need to be identical with the quantity of bus host module 3.In 16 ports
Interchanger in, provide that the memory that can obtain 16M can meet to require according to the agreements of ARINC 664, therefore using 4 pieces of 4M's
Memory module 5 is connected with 4 bus host modules 3 respectively, is completed by bus host module 3 by memory control module 4
Control to memory module 5.Each storage space is divided into several pages, every page of capacity is 2KBytes, stores one enough
The most long frames (most long frame is 1518Bytes) of individual AFDX, when so accessing memory every time, only it is to be understood that the initial address and frame of page
Length can be carried out read or write operation.
Scheduling result FIFO of the selecting module 6 respectively with 4 bus host modules 3 and interchanger is dispatched to be connected.Scheduling knot
The information generally comprised in fruit FIFO has：Read operation, write operation, port numbers, caching number, frame length and storage initial address etc..
Information in scheduling result FIFO is as the scheduler module in interchanger according to caused by certain dispatching algorithm, and the present invention does not relate to
And this field, only utilize its caused scheduling result.The major function for dispatching selecting module 6 is read from scheduling result FIFO
Scheduling result caused by AFDX interchangers, judge port and the memory module 5 to be swapped, scheduling result is sent to
Corresponding bus host module 3, while judge next scheduling result：If port numbers and memory and previous scheduling result
Differ, and the corresponding free time of bus host module 3, (host module can give scheduling selecting module one after once-through operation is completed
Individual feedback signal), then this scheduling result is directly sent to corresponding bus host module 3, is then followed by judging next
Scheduling result, the like；Otherwise, wait corresponding bus host module 3 idle, then scheduling result is handled.By total
The storage or forwarding of data are completed in the control of line host module 3.
Due to a block storage has been divided into 4 block memory modules 5, the storage address deposited in scheduling result FIFO is
Corresponding to the continuous address of a block storage.Therefore, in addition to the first block memory module 5, to other three block storages mould
Block 5 needs to be handled address when conducting interviews.Address process process is that original address is reduced accordingly.Calculating side
Method is：Assuming that access number is m memory (m=2,3,4 ...), then new address=original address-(m-1) * memories
Module full address.Address translation process is completed by corresponding bus host module 3.Selecting module 6 is dispatched only according to address
Judge any block memory module 5 accessed, to address without any processing.
In order to more intuitively understand, the working method of bus after improving has been illustrated below.16 ports of note are respectively
1-16,4 memory modules 5 are respectively I, II, III, IV.Assuming that continuous 6 scheduling results are (a) 3 in scheduling result FIFO
→ II, (b) 9 ← IV, (c) 9 ← I, (d) 11 → III, (e) 5 → I, (f) 7 → II.Wherein 3 → II represent that scheduling result is by 3 ends
Mouth writes data into the second block memory module, and it is a to remember the operation, and 9 ← IV represent by reading data in the 4th block memory module
To the process of port 9, it is b to remember the operation, and other scheduling results are similarly.In this case, to be visited between a operations and b operations
The memory module 5 asked and port differ, and in the absence of conflict, and bus host module is idle, therefore can hold parallel
OK.But c operation due to b operation the port to be accessed it is identical, conflict be present, thus c operation can only wait b operation completion.
When c operations detect the signal that b operations are completed, c operations are sent in No. 1 bus host module (corresponding memory module
I), while judge that d is operated, do not conflict because d operations operate with c, can perform parallel, d operations are then also sent to No. 3 always
In line host module (corresponding memory module III).Then judge that e is operated again, although e operations also do not conflict with d operations,
Because e operations are identical with the c operations memory module 5 to be accessed, so at this moment if c operations have been completed, No. 1 host module
In idle condition, then e operations can also perform parallel, even if otherwise it does not conflict with d operations, can not perform parallel.
Above is so that 16 ports, memory are divided into 4 pieces of data bus structure as an example, invention has been described.It is aobvious
So, if the memory module 5 being divided into counts more, the possibility of data parallel is bigger, and message transmission rate will improve.But
The memory module 5 being divided into counts more, bus host module more than 3, and the signal wire inside controller is more, and signal wire to be made
More complicated into subsequent placement wiring, system global reliability will also decline.Therefore, according to theory analysis and actual verification, for
The AFDX interchangers of 16 ports, divide the memory into 4 pieces it is the most reasonable.
In the case where 16 ports, memory are divided into 4 pieces, functional simulation is carried out by software, and it is total with traditional data
Line (a shared block storage) compares.In test environment, two kinds of data/address bus are respectively adopted and are adjusted to handle identical
Spend result, obtain two kinds of buses working time T1 and T4, so as to calculate improve after data/address bus speed-up ratio, wherein accelerating
Compare S=T1/T4.By 20 emulation experiments, it is 2.492 to obtain speed-up ratio maximum, minimum value 1.536, and average is
1.972.Simulation result shows that the data exchange bus after improvement can effectively improve the forwarding of AFDX interchangers internal data store
Speed, and Mean Speed is about original 2 times.
In the case of theory, M values are bigger, and storage forwarding rate can be higher, and ideally, maximum speed-up ratio
S=M.But in actual applications, because of situations such as successive frame is sent to same port, theoretical maximum acceleration can not possibly be reached substantially
Than.Therefore in above-mentioned emulation testing and checking, the speed-up ratio that the present invention is reached meets theory expectation.
The probability that two neighboring scheduling result do not conflict can be obtained according to the related knowledge of probability theory, this probability can be with
As the reference of memory block count, calculation formula is P=(N-1) * (M-1)/(N*M), and wherein N is port number, and M is piecemeal
Number.Under 16 port cases, 2,4,8,16 pieces are divided the memory into, the probability that its two neighboring scheduling result does not conflict is respectively
0.469,0.703,0.820,0.938.When memory number is 2, collision probability is not 0.469, and the probability of conflict has exceeded half
Into, it is clear that this is not to select well；When memory number brings up to 16, the probability that two neighboring scheduling result does not conflict is
0.938, provided although the not collision probability 0.703 when memory number is 4 compared to increasing, takes 4 times of hardware
Source, what this did not calculated obviously also.Therefore, in the selection of memory block count, two neighboring tune that the computational methods obtain
Collision probability value does not have very big reference value to degree result.
The present invention can be used in the AFDX interchangers based on Shared memory switch mode.Shared memory switch mode it is basic
Thought is to carry out store frames of data using a large amount of high-speed RAMs inside interchanger, and the data frame received from each port can basis
Then corresponding dispatching algorithm storage is forwarded to corresponding output port again to the specified location in RAM.Inside AFDX interchangers
It can be handled by the way of control information and data flow are separate.It is so-called separate, refer to the dispatch deal of packet
Performed parallel with the data bus transmission of packet, data/address bus is deposited accordingly according to the dispatch deal result of packet to data
Storage and forwarding.
Traditional data bus structure can be by the data storage that each port receives in a RAM, and such structure is same
One time can only have a port carrying out the storage or forwarding of data.The present invention after based on Crossbar and memory partitioning,
It can realize that multiple ports same time carries out the storage or forwarding of data, improve the speed of interchanger internal data store forwarding
Rate, so as to reduce delay of the data inside interchanger.
According to such scheme, be described with logical design of the Verilog language to modules in the present invention, and by its
Integrated with other modules in AFDX interchangers, finally map that in FPGA and realize.Wherein AFDX exchanges generator terminal
Mouthful number is 16, and memory module is using the outer SSRAM of piece and is divided into 4 pieces.By being tested the function of whole interchanger to examine
Survey the function and performance of the present invention.Under identical test environment, turned using storage of the AFDX interchangers of the present invention to data
Sending out speed ratio will not height using the AFDX interchangers of the present invention.Test result show the present invention have well can practicality, and property
It can meet to be expected.
Claims (6)
1. the AFDX exchange data bus structures based on Crossbar frameworks, it is characterised in that including with switch ports themselves number
Measure equal bus slave computer module (1), a bus interconnection module (2), bus host module (3), memory control module (4)
With memory module (5), and a scheduling selecting module (6)；The quantity of bus host module (3) is not more than bus slave computer mould
The quantity of block (1)；Bus host module (3), memory control module (4) and memory module (5) quantity are equal and more than 1；
Each bus host module (3) is by bus interconnection module (2) using Crossbar frameworks and each bus slave computer module
(1) interconnect；Each bus host module (3) passes through memory module (5) corresponding to memory control module (4) connection respectively；
Each bus host module (3) connects interchanger scheduling result FIFO by dispatching selecting module (6).
2. the AFDX exchange data bus structures according to claim 1 based on Crossbar frameworks, it is characterised in that
Described scheduling selecting module (6) includes the address discrimination module (6A) being connected in turn on interchanger scheduling result FIFO and referred to
Make sending module (6B)；
Address discrimination module (6A) is used to extract scheduling result from interchanger scheduling result FIFO, obtains the end to be swapped
Mouth and memory module (5)；
Instruction sending module (6B) is used for the bus host module 3 that obtained scheduling result is sent to corresponding ports.
3. the AFDX exchange data bus structures according to claim 1 based on Crossbar frameworks, it is characterised in that
Described switch ports themselves number is 16, and the quantity of bus host module is 4；Memory space point in memory module (5)
For several pages, every page of capacity is 2KBytes.
4. the method for interchanging data of the AFDX exchange data bus structures based on Crossbar frameworks, it is characterised in that use
Data bus structure as claimed in claim 1, comprises the following steps,
Step 1, information of the scheduling selecting module (6) in interchanger scheduling result FIFO, reads caused by AFDX interchangers
Scheduling result, judges port and the memory module (5) to be swapped, and by the scheduling knot comprising memory address signal
Fruit be sent to should memory module (5) bus host module (3)；
Step 2, complete scheduling selecting module (6) after sending and judge next scheduling result；If the port currently to be swapped
Number and memory module (5) differed with previous scheduling result, and corresponding host module is idle, then directly will be currently
Scheduling result is sent to corresponding bus host module (3), then repeat step two；Otherwise, corresponding bus host mould is waited
Block (3) is idle, then processing is transmitted to scheduling result；
Step 3, the bus host module (3) for receiving scheduling result are completed to memory module by memory control module (4)
(5) control accesses, and completes the storage or forwarding of data；Scheduling selecting module (6) one can be given anti-after once-through operation is completed
Feedback signal, indicate its state for the free time.
5. the data exchange side of the AFDX exchange data bus structures according to claim 4 based on Crossbar frameworks
Method, it is characterised in that in addition to first bus host module (3), spare bus host module (3) passes through memory control module
(4) when completing the control access to memory module (5), the memory address information received is changed as follows,
The maximum address of the original address of new address=memory module of memory module-(m-1) * memory modules；
Wherein, m is the numbering that memory module corresponds to bus host module, and the original address of memory module is scheduling result
Storage initial address in FIFO.
6. the data exchange side of the AFDX exchange data bus structures according to claim 4 based on Crossbar frameworks
Method, it is characterised in that interchanger scheduling result FIFO includes read operation signal, write operation signal, port numbers, caching number, frame
Long and storage starting address signal.
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| CN113162872B (en) * | 2021-03-04 | 2022-10-11 | 中国航空工业集团公司西安航空计算技术研究所 | Self-detection ARINC818 switch capable of dynamically switching and monitoring |
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