CN1507285A - Method of realizing router chip of group exchange network with FPGA device - Google Patents
Method of realizing router chip of group exchange network with FPGA device Download PDFInfo
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Abstract
The method of realizing router chip of group exchange network with FPGA device includes the following steps: setting inside chip symmetrical I/O ports via utilizing the gate array resource in FPGA; setting inside chip symmetrical crossed logic switches; dispatching the data passages from the input ports to the output ports with arbitration logic; and completing the data exchange task among multiple ports. The kernel of the present invention is universal crossed switches, and the group communication system with the digital exchange chip is easy to constitute and easy to expand. The present invention may be used in various network topology. In addition, the present invention can simplify effectively the communication protocol and this makes it possible for the corresponding exchange equipment to realize safe and efficient communication among group nodes. The present invention makes best use of the resource superiority of FPGA and speed superiority of serial-parallel conversion interface device.
Description
Technical field
The present invention relates to a kind of FPGA of employing device and realize the method for group of planes internet router chip.
Background technology
Network of Workstation couples together formation to several high-performance treatments nodes by the high speed switching network from hardware configuration, can realize the computer system that high-speed parallel is handled.The performance of the single node in the Network of Workstation is more and more higher, requires the performance of switching network to be complementary with the node performance, otherwise will become the bottleneck of whole system.Router chip is the core component of structure group of planes switching network, and the performance of router chip has decisive influence to the performance of group of planes switching network.Design structure can be expanded, the router chip of high performance machine flock-mate switching network is significant.A kind of expandable switching network network is seen accompanying drawing 1.
The function of router chip is to receive packet from input port, the routing iinformation that comprises in the recognition data bag, determine output port according to the method for routing that pre-defines, the input exchanges data is arrived corresponding output port, thereby provide high speed, reliable data-transmission channel for being connected between each processing node on the switching network.
Traditional router chip design adopts application-specific integrated circuit (ASIC) (ASIC) device to realize, though the ASIC device can guarantee good performance by well-designed and advanced technology, but owing to reasons such as development cost height, construction cycle length and production test cost expense are big, when chip does not form in batches, do not possess higher performance; In addition, in case ASIC device design typification, its logical construction and performance just can not change again, so new method for routing and logical design thought can not in time obtain to use.
Summary of the invention
Purpose of the present invention proposes a kind of method with FPGA device realization structure group of planes switching network router chip, adopts this method design to realize that has 8 full-duplex ports, and the one-way transmission bandwidth of each port reaches the router chip of 4Gbit/S.
A kind of method with FPGA device realization group of planes switching network router chip, method comprises step:
Utilize the gate array resource of programmable logic device, the input-output port of symmetry is set at chip internal;
The crossed logic switches of symmetry is set at chip internal;
Dispatch the data channel that inputs between output port by arbitrated logic;
Finish the data exchange task between the multiport.
The core of the inventive method is the most general complete intersection switch, thereby uses the group of planes communication system of such digital exchange chip structure to be highly susceptible to setting up and expansion, can be applicable in the various network topologies.Simultaneously, because the present invention has simplified communication protocol effectively, corresponding exchange equipment can realize the communication between group of planes node safely and efficiently.The present invention has made full use of the speed advantage of the resources advantage of programmable device FPGA and string-also/also-string translation interface device.The interface digital signal is operated under the dual rate clock, has brought into play the usefulness of device, and the communication bandwidth ratio of system is single along doubling under the clock service conditions.Use multilink transmission method of the present invention, the performance of future communications system can develop along with the development of programming device.Because each link all is reciprocity fully in this method, so in the progress of following device level, only need make an amendment slightly in logic just can increase exponentially the performance of chip.
Description of drawings
Fig. 1 is the two-way multistage group of planes switching network schematic diagram of prior art;
Fig. 2 is a router chip structure chart of the present invention;
Fig. 3 is the annexation schematic diagram of each intermodule in the router chip of the present invention;
Fig. 4 is the input port schematic diagram;
Fig. 5 is the output port schematic diagram;
Fig. 6 is the moderator schematic diagram;
Fig. 7 is the data selector schematic diagram.
Embodiment
Compare with the ASIC device, the FPGA device has the advantage of field-programmable, constantly perfect along with production technology, the integrated level and the operating rate of FPGA device have all obtained very big improvement now, logical resource that its inside provides such as digital dock manager, block memory, MUX, Double Data Rate trigger etc. can satisfy the requirement of router chip to logical resource and clock frequency fully.Realize that with the FPGA device router chip has the design cycle weak point, is convenient to carry out design improvement, ratio of performance to price advantages of higher.The ripe logic that realizes with FPGA also can convert ASIC to easily.
Describe the present invention in detail below in conjunction with accompanying drawing.
As shown in Figure 2, described method has realized that has 8 duplex port, and the one-way transmission bandwidth of each port reaches the router chip of 4Gbit/S.Can construct extendible group of planes switching network with this router chip.
Method of the present invention is described respectively below.
1. method for routing:
Router chip adopts location, source method for routing, and promptly routing iinformation is by sending the head that node inserts packet, and router chip selects output port to transmit data according to this routing iinformation.The packet that is transmitted adopts variable-length, the variable-length here has two-layer meaning: the routing iinformation of (1) head can have one or more, every grade of router chip uses a routing iinformation, therefore can link up a plurality of router chip levels, constitute multistage network, the expansion of network enabled scale; (2) the valid data variable-length in the packet can be easily be embedded into the packet of various upper-layer protocols in the packet of router chip, can reduce the conversion expense between agreement thus, improves protocol efficiency.
2. exchanging mechanism and flow control:
Router chip adopts buffering worm hole routing mechanism to realize exchange and flow control.After the input port of router chip is received the head routing iinformation of packet, just according to this routing iinformation request output port, if output port can be with just being switched directly to output port to data, and needn't wait for and receive complete packet that this method can reduce the switching delay of router chip.When output port is unavailable, as long as input port has spatial cache, just continue to receive data, when the data in the buffering area reach the buffering area upper bound of regulation, send flow control signal, notify higher level's output port to stop paying out data.This flow control methods can hold whole packet down under congestion situations when the buffering area of input port is big, reduced taking the physical channel; For bigger packet, be stored in the buffering area of router chips at different levels disperseing during obstruction, can not cause packet loss yet.Thereby realized support to the variable-length data package transmission.
3. chip internal data channel scheduling:
Router chip adopts the scheduling of distributed frame realization to internal data path, be each output port and be equipped with a moderator, this moderator receives the access request signal from all input ports, and provides the arbitration response signal according to the priority orders in the priority query.Moderator is dispatched request signal by recent minimum service priority principle, a priority query is set in each moderator, priority query sets an initial priority behind the chip reset, and when receiving a plurality of request simultaneously, the request that priority is the highest obtains response; The request that service is responded after finishing is set to lowest priority, and originally priority is higher than by response request, and its priority is constant; Originally priority is lower than by response request, and its priority improves a grade successively.The distributed frame of moderator can improve processing of request speed, and then reduces arbitration delays, and distributed arbitration program also makes things convenient for the support to multi-casting communication in router chip future; Recent minimum service priority principle can guarantee the fairness to each request, some request can not take place by phenomenon hungry to death.
4. port bandwidth extended method:
Each port of router chip all adopts the binary channels technology to come the growth data width of channel, and it is wide to have realized increasing data carousel, can utilize existing high speed string-also/also-string conversion chip again, to support long line transmission and minimizing holding wire quantity.In the input port of router chip, be provided with two and independently import data channel, with two asynchronous FIFO buffering area buffer memory two paths of data respectively independently, buffering area read control logic according to the sky sign of two buffering areas, the Status Flag of sense data, control is to the read operation of buffering area, the clock skew that the compensation two paths of data produces when transmitting on physical circuit is to realize synchronous between two channel datas.
Wide for the data carousel that further increases port, adopt and transmit Double Data Rate (DDR) technology of data simultaneously, and utilized the interior special-purpose DDR logical resource of FPGA device at rising edge clock signal and trailing edge.For reducing the clock work frequency in the chip, in chip, adopt the method for widening data channel with the coupling of realization with external data speed.Adopt the DDR technology to make the data transfer bandwidth of router chip increase by one times.
5. signal load mode:
The transfer of data of router chip adopts the source clock synchronizing method to realize, the source clock is meant when output port sends data, send clock signal simultaneously with data sync, the input port of subordinate's router chip drives the write control logic of asynchronous FIFO buffering area with this clock signal, and the control logic of reading of asynchronous FIFO buffering area is driven by the local clock signal.So just realized that input data between different port read the back from the asynchronous FIFO buffering area and obtain synchronously, and then can simplify the logical design of cross bar switch, moderator and output port.Another implication of synchronous driving is that output port is undertaken by fixing timeticks when sending data, and needn't and the input port of subordinate's chip between set up request, response relation.When flow control takes place, send the order that stops or continuing transmission by subordinate's chip, this order is sent to output port by the backward channel in the full-duplex channel, the data transmission procedure of control output end mouth.Use the asynchronous FIFO buffering area to make the clock signal of input data and the global clock Signal Spacing in the chip, thereby simplified the clock synchronization logic in the chip; The synchronizing signal transfer approach has been eliminated request, has been replied the propagation delay of generation, has improved the signal transfer rate.
6. router chip structure:
Modular method is adopted in the logical design of router chip, by function router chip is divided into input port, output port, moderator and cross bar switch 4 class basic modules.The annexation of each intermodule is seen accompanying drawing 3, and 8 data selectors among the figure are generically and collectively referred to as cross bar switch.
The major function of input port input port comprises: (1) becomes the single clock of data wire double width along data Double Data Rate (DDR) data transaction; (2) data are carried out 8B/10B decoding and isolate the agreement control character that data transmit and do respective handling, identify the position end to end of packet; (3) packet is write in the asynchronous FIFO buffering area of input port, monitor the data volume in the buffering area simultaneously, when reaching the predetermined buffering area upper bound, send flow control signal; (4) according to the state information of two asynchronous FIFO buffering areas, control read operation, and two paths of data is merged into a circuit-switched data, analyze the routing iinformation of packet and send the output port request signal to moderator to buffering area; (5) receive the answer signal of moderator after, control data is to the transport process of output port.As shown in Figure 4, input port has comprised two data passages, and the control logic of reading behind the asynchronous FIFO buffering area synthesizes a circuit-switched data to two paths of data, delivers to cross bar switch and exchanges.
The major function of output port output port comprises: (1) is written to the data of sending here through cross bar switch in the synchronization fifo buffering area of output port, monitors the full scale will of buffering area simultaneously, so that realize the flow control of chip internal; (2) sign end to end and other control characters of sense data from buffering area, and affix data transfer protocol regulation form the protocol data bag; (3) packet is divided into two-way, controls its transport process respectively; (3) two data passages carry out the 8B/10B coding to data respectively, single conversion along data to Double Data Rate (DDR), and the two-way DDR data after the conversion are sent from the pin of output port, send simultaneously to be used for clock signal synchronous; (4) response is made in the flow control that the input port of subordinate's router chip is sent here, promptly suspends or continue the data transmission; (4) realize other controlled function that channel protocol is stipulated.Accompanying drawing 5 shows inner each main modular of output port and annexation thereof.
The moderator moderator receives the request signal from 8 input ports, according to the priority orders of storing in the priority query in the moderator, select the highest request signal of current priority, and it is made response, selection control signal and the output sent simultaneously cross bar switch allow signal.When a packet transmission was finished, request signal was cancelled, and moderator is resequenced to the priority orders in its priority query, and the request of recent minimum service comes limit priority, and the request that has just obtained service comes lowest priority.The structure of moderator as shown in Figure 6.
The function of cross bar switch cross bar switch is for setting up variable data channel between input port and output port, thereby realizes exchanges data.Adopt 8 independently multidigit 8 select 1 data selector to realize, the output of each data selector connects an output port, 8 inputs are connected respectively to 8 input ports, select control signal and output to allow signal to be connected to corresponding moderator.Data selector as shown in Figure 7.
Each functional module adopts hardware description language to write, and downloads in the FPGA device after emulation, the debugging, can realize router chip.
Claims (10)
1. realize the method for group of planes switching network router chip with the FPGA device for one kind, method comprises step:
Utilize the gate array resource of programmable logic device, the input-output port of symmetry is set at chip internal;
The crossed logic switches of symmetry is set at chip internal;
Dispatch the data channel that inputs between output port by arbitrated logic;
Finish the data exchange task between the multiport.
2. the method for claim 1 is characterized in that described symmetry is that the input port number is identical with the output port number, and numbering identical a pair of input/output port is the antithesis port.
3. the method for claim 1 is characterized in that: the method that the scheduling of described internal chiasma switch adopts priority to rotate.
4. method as claimed in claim 3 is characterized in that: the method that described priority is rotated comprises step:
Give the priority sequence number of each input port;
When a plurality of input ports taking place competing same output channel, will give the input port medium priority sequence number that participates in the competition the highest one by power;
And after this data transfer is finished, the priority sequence number of relevant input port is done corresponding the adjustment.
5. the method for claim 1, it is characterized in that: the flow control signal of the data transmission procedure that carries out between input/output port passes through the antithesis output port with the antithesis input port transmission of character command forms to the packet transmit port, know via passing to the output port that sends packet after this antithesis input port interpreted command, realize the flow control on the data word rank.
6. the method for claim 1 is characterized in that: the inner logical resource FIFO of programming device that uses of input port and output port comes the construction data buffering area, to realize the worm hole routing mechanism of band buffering.
7. the method for claim 1, it is characterized in that: transfer of data is unit with the packet, first data carry routing iinformation of each packet indicates the efferent pathway of packet.
8. the method for claim 1 is characterized in that: The data 8b/10b form coding on the port.
9. the method for claim 1 is characterized in that: to press synchronised clock two along transmission for data on the port, by special use string-also/parallel-serial converter spare transmission data.
10. the method for claim 1, it is characterized in that: each port has at least 2 identical physical links to unite formation, each link uses oneself independently clock, and the recipient merges into one the tunnel with multichannel data, and transmit leg is assigned to multichannel with a circuit-switched data and sends.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA021545197A CN1507285A (en) | 2002-12-06 | 2002-12-06 | Method of realizing router chip of group exchange network with FPGA device |
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| CNA021545197A CN1507285A (en) | 2002-12-06 | 2002-12-06 | Method of realizing router chip of group exchange network with FPGA device |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100550832C (en) * | 2005-11-15 | 2009-10-14 | 华为技术有限公司 | A kind of arbitration implementation method of switching network |
| CN1983917B (en) * | 2005-12-14 | 2010-07-14 | 中兴通讯股份有限公司 | Method and structure for realizing progrmmable logic device data exchange |
| CN101924802A (en) * | 2009-05-25 | 2010-12-22 | 株式会社日立高新技术仪器 | Network I/O system and establishing method thereof |
| CN101697147B (en) * | 2009-09-29 | 2011-05-25 | 江俊逢 | Reconfigurable I/O chip |
| CN101719860B (en) * | 2009-11-26 | 2012-05-30 | 盛科网络（苏州）有限公司 | Physical exchange system based on E1/T1 circuit |
| CN101540764B (en) * | 2009-04-27 | 2013-02-06 | 曙光信息产业(北京)有限公司 | Data transmitting and routing method facing to virtual machine based on FPGA |
| CN105391442A (en) * | 2014-08-27 | 2016-03-09 | 快速逻辑公司 | Routing network for programmable logic device |
| CN105634995A (en) * | 2014-10-31 | 2016-06-01 | 中国飞行试验研究院 | Low-delay airborne gigabit Ethernet switching configuration |
| CN110519174A (en) * | 2019-09-16 | 2019-11-29 | 无锡江南计算技术研究所 | A kind of efficient parallel management method and framework towards high-order router chip |
| CN112737952A (en) * | 2020-12-28 | 2021-04-30 | 天使方舟有限公司 | FPGA service application layer information routing model and monitoring platform thereof |
| CN113242188A (en) * | 2021-04-22 | 2021-08-10 | 中国电子科技集团公司第二十九研究所 | Microwave channel full-switching network construction method, control method and coding and decoding method |
-
2002
- 2002-12-06 CN CNA021545197A patent/CN1507285A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100550832C (en) * | 2005-11-15 | 2009-10-14 | 华为技术有限公司 | A kind of arbitration implementation method of switching network |
| CN1983917B (en) * | 2005-12-14 | 2010-07-14 | 中兴通讯股份有限公司 | Method and structure for realizing progrmmable logic device data exchange |
| CN101540764B (en) * | 2009-04-27 | 2013-02-06 | 曙光信息产业(北京)有限公司 | Data transmitting and routing method facing to virtual machine based on FPGA |
| CN101924802A (en) * | 2009-05-25 | 2010-12-22 | 株式会社日立高新技术仪器 | Network I/O system and establishing method thereof |
| CN101924802B (en) * | 2009-05-25 | 2013-08-07 | 株式会社日立高新技术仪器 | Network I/O system and network configuring method |
| CN101697147B (en) * | 2009-09-29 | 2011-05-25 | 江俊逢 | Reconfigurable I/O chip |
| CN101719860B (en) * | 2009-11-26 | 2012-05-30 | 盛科网络（苏州）有限公司 | Physical exchange system based on E1/T1 circuit |
| CN105391442B (en) * | 2014-08-27 | 2021-01-05 | 快速逻辑公司 | Routing network for programmable logic device |
| CN105391442A (en) * | 2014-08-27 | 2016-03-09 | 快速逻辑公司 | Routing network for programmable logic device |
| CN105634995A (en) * | 2014-10-31 | 2016-06-01 | 中国飞行试验研究院 | Low-delay airborne gigabit Ethernet switching configuration |
| CN110519174A (en) * | 2019-09-16 | 2019-11-29 | 无锡江南计算技术研究所 | A kind of efficient parallel management method and framework towards high-order router chip |
| CN110519174B (en) * | 2019-09-16 | 2021-10-29 | 无锡江南计算技术研究所 | Efficient parallel management method and architecture for high-order router chip |
| CN112737952A (en) * | 2020-12-28 | 2021-04-30 | 天使方舟有限公司 | FPGA service application layer information routing model and monitoring platform thereof |
| CN112737952B (en) * | 2020-12-28 | 2022-08-26 | Gotcex 有限公司 | FPGA service application layer information routing model and monitoring platform thereof |
| CN113242188A (en) * | 2021-04-22 | 2021-08-10 | 中国电子科技集团公司第二十九研究所 | Microwave channel full-switching network construction method, control method and coding and decoding method |
| CN113242188B (en) * | 2021-04-22 | 2022-06-21 | 中国电子科技集团公司第二十九研究所 | Microwave channel full-switching network construction method, control method and coding and decoding method |
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