CN115269487B - Inter-chip data high-speed transmission method and device - Google Patents
Inter-chip data high-speed transmission method and device Download PDFInfo
- Publication number
- CN115269487B CN115269487B CN202211173384.8A CN202211173384A CN115269487B CN 115269487 B CN115269487 B CN 115269487B CN 202211173384 A CN202211173384 A CN 202211173384A CN 115269487 B CN115269487 B CN 115269487B
- Authority
- CN
- China
- Prior art keywords
- chip
- data
- speed
- chips
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Software Systems (AREA)
- Communication Control (AREA)
Abstract
The invention belongs to the field of data transmission, and provides a method and a device for transmitting data among chips at a high speed, aiming at the technical problem of low data transmission rate among a plurality of chips in the prior art, wherein the method comprises the following steps: step 1, setting an adjustable chip connection structure according to the connection requirement and technical index of a system on a chip to be designed; and 2, realizing data transmission between the chips by adopting a mode of combining serial transmission and an optical interface. The adjustable connecting structure is as follows: an optical transceiver module is provided physically separable from the plurality of chips. Under the structure, the connection link of the system on chip is sufficient, the connection mode can be adjusted, and the transmission rate among the chips is greatly improved.
Description
Technical Field
The invention belongs to the field of data transmission, and particularly relates to a method and a device for high-speed transmission of data between chips.
Background
In recent years, in order to improve chip performance, the working frequency of a chip is generally increased and the size of the chip is generally reduced in a design process to achieve higher integration level, however, the chip can reach its power limit in this way, in order to avoid this problem, a multi-core chip is generally adopted to replace a single-core chip, and a method for connecting a plurality of chips is proposed to solve the problems of insufficient memory, slow processing speed, single-chip power limit and the like;
for example, the chinese invention patent (CN 111124997a, application publication date: 2020, 5/8) discloses a data transmission method, which, when a data packet of a first processor core needs to be sent to a second processor core, first transmits the data packet in the first processor core to a first buffer area, and obtains the data packet from the first buffer area for sending, so that even if the clock frequency of a data write clock at a sending end is higher than the clock frequency of a link read clock at the sending end, the first processor core does not need to wait for data reading of the link read clock, and only needs to transmit the data packet to the first buffer area according to the clock frequency of the data write clock at the sending end, and then the next data packet transmission or other operations can be performed, and similarly, the data receiving operation can be performed stably according to the rhythm of the link clock at the receiving end, so that two connection chips with different clock frequencies can cooperate with each other efficiently, thereby greatly expanding the clock adaptation range between connection bodies and effectively improving the data transmission efficiency.
Although the method improves the data transmission efficiency by expanding the clock adaptation range between two connected chips, when the method is applied to a chip structure with a plurality of connections, the processing process will become complicated because the clock range needing to be expanded is more, and therefore, the effect of improving the transmission efficiency is not obvious when a plurality of chips are connected.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a new method and apparatus for transmitting chip data at a high speed, aiming at the deficiencies of the above technical solutions.
The invention discloses a method for transmitting data between chips at a high speed, which is characterized by comprising the following steps of:
step 1: setting an adjustable chip connecting structure according to the connection requirement and main technical indexes of a system on a chip to be designed;
step 2: and realizing data transmission between the chips by adopting a mode of combining serial transmission and an optical interface.
The step 2 specifically comprises: the high-speed differential serial connection communication mode is adopted and is completed through a high-speed transceiver on the chip, the high-speed transceiver is compatible with various high-speed serial protocols and supports higher transmission rate, and multi-bit parallel signals in the chip are finally converted into serial electric signals through time division multiplexing and transmitted between chips in a differential mode; meanwhile, the high-speed transceiver is externally connected with the optical transceiving module and the optical fiber, and the high-speed differential electric signal is converted into an optical signal for transmission.
According to the method for transmitting data among chips at high speed, the adjustable connecting structure is characterized in that: the optical transceiver module is physically separable from the plurality of chips, and if the connection communication mode among the plurality of chips needs to be changed, the connection mode of the optical transceiver module and the optical fiber in the connection network only needs to be changed.
According to the method for transmitting data between chips at a high speed, in the step 1, the connection requirements are specifically as follows: mesh interconnection among a plurality of chips is realized; the main technical indexes are as follows: the overall speed reaches 3000Gbps, the single-channel speed reaches 25Gbps, the connection link is more than or equal to 40, and the processor is more than or equal to 4.
According to the method for transmitting data between chips at high speed, the mesh connection structure is selected as the basic connection structure between chips.
According to the method for transmitting data among the chips at a high speed, the adjustable chip connection structure is characterized in that: the chip comprises 5 chips, wherein a chip _ A, a chip _ B, a chip _ C and a chip _ D are in a cross connection structure; and simultaneously, a chip _ X is arranged, and fixed connecting wires are added for the direct or indirect connection of the chip _ X with the chip _ A, the chip _ B, the chip _ C and the chip _ D.
According to the inter-chip data high-speed transmission method, the chip _ A, the chip _ B, the chip _ C and the chip _ D are arranged according to a square structure, and are connected in a pairwise cross manner to form a mesh connection structure.
The following will be described in detail for a high-speed transceiver architecture:
the high-speed transceiver consists of a transmitting end and a receiving end, wherein the two parts have independent functions and comprise a physical medium adaptation layer (PMA) sublayer and a Physical Coding Sublayer (PCS) sublayer. The PMA sublayer contains circuits for high speed serial-to-parallel conversion, pre-emphasis, post-emphasis, and clock recovery. The PCS sublayer comprises circuits such as a data bit width conversion circuit, a pseudo-random sequence generation circuit, an 8B/10B coding and decoding circuit, a gearbox for transmitting 64B/66B and 64B/67B coded data, a buffer area, a channel binding circuit, a polarity reversing circuit and the like;
the high-speed transceiver sending end processing flow is that firstly, data enters a sending end PCS through an interface, whether 8B/10B coding is carried out or not is selected according to requirements, if 64B/66B coding data or 64B/67B coding data is transmitted, the 8B/10B coding function is not needed, and data transmission is carried out through a sending end gearbox. Whether the data are transmitted to a PMA (permanent magnetic access) sending end after the Buffer and the polarity inversion of the sending end are selected to convert the low-speed parallel data into high-speed serial data or not, and operations such as pre-emphasis can be performed on the data. In addition, the transmitting end can generate pseudo random check data of a PRBS7 mode, a PRBS15 mode, a PRBS23 mode or a PRBS31 mode;
the receiving end processing flow of the high-speed transceiver is that firstly, the received high-speed serial data is converted into low-speed parallel data in a serial-parallel mode through a PMA of the receiving end, then the low-speed parallel data is transmitted to a PCS of the receiving end, polarity inversion selection is firstly carried out, then word alignment is carried out, and then whether 8B/10B decoding is carried out or not is selected. If the 64B/66B code or the 64B/67B code data is transmitted, the 8B/10B decoding module is not used, the transmission is carried out through a transmission box of the receiving end, and finally the transmission reaches an interface of the receiving end.
Furthermore, the serial transmission communication protocol in step 2 is an SRIO protocol, data exchange and forwarding are completed through a physical layer and a transport layer, the switching node realizes its switching function by packet routing, each addressable device has at least one unique DeviceID in the SRIO interconnection system, when the communication node generates a data packet, the destidid and sourceID are placed in a header, a routing table is arranged in the SRIO switching component to map different deviceids to physical ports, the SRIO switching component obtains the destidid and sourceID of the current packet by analyzing the received header and searches for the corresponding physical ports through the person routing table, and after the search is completed, the corresponding ports are switched on to realize the packet routing operation, thereby completing the switching.
Furthermore, in this embodiment, a high-speed transceiver is used to connect an optical transceiver module and an optical fiber to implement a high-speed optical interconnection communication between multiple chips, so before a system optical interface design is developed, type selection of the optical transceiver module is performed first, where the type selection is based on a transmission rate and a channel density mainly supported by the module, for chips _ a to chip _ D, a system requires each chip to implement a twelve-channel 6.25Gbps high-speed transceiver link, and an area occupied by the optical transceiver module is large, so that channel density is more emphasized on the type selection of the optical transceiver module, the optical transmission supporting 4 channels and the optical reception supporting 4 channels have a high port density, and a single-channel transmission rate of the optical transceiver module is as high as 10.5Gbps, which can meet a high-speed transceiver index requirement of 6.25Gbps in a single channel in chips _ a to chip _ D, and therefore, in the design of this embodiment, 10 optical interfaces of this type are provided for chips _ a to chip _ D to implement 40-channel high-speed optical interconnection transceiving;
after the optical transceiver module is selected, the optical interface circuit of the optical transceiver module can be designed, taking the optical interfaces used in the chip _ a to the chip _ D as an example, the interface mode is a double-sided gold finger socket, the total number of electrical interface pins of the optical interface is 38, and the optical interface has high integration level, so that the optical interface circuit is strictly in accordance with the standard during design.
The invention also provides a device for transmitting data between chips at high speed, which is characterized in that: the optical path transceiver module is used for executing any inter-chip data high-speed transmission method.
The invention also provides a system on chip, which is characterized by comprising the device for transmitting the data between the chips at a high speed.
Finally, the high-speed chip data transmission method provided by the embodiment can support 42-channel optical link, wherein the maximum transmission rate of 2 channels of single channel reaches 25Gbps, and is completed by chip _ X; and the transmission rate of 40 paths of single channels is 6.25Gbps which is finished from the chip _ A to the chip _ D, so that the transmission rate between the chips is greatly improved.
Based on the technical scheme, the high-speed chip data transmission method and device provided by the application have the following technical effects:
the embodiment provides a method and a device for high-speed transmission of data among chips, and provides a structure for data transmission among chips aiming at the technical problem that the data transmission rate among a plurality of chips in the prior art is not high.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a flowchart of a method for transmitting data between chips at a high speed according to an embodiment of the present disclosure;
fig. 2 is a diagram of the adjustable chip connection structure provided in the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The concept to which the present application relates will be first explained below with reference to the drawings. It should be noted that the following descriptions of the concepts are only for the purpose of facilitating understanding of the contents of the present application, and do not represent limitations on the scope of the present application.
As shown in fig. 1, a method for transmitting data between chips at high speed is characterized in that: step 1: setting an adjustable chip connecting structure according to the connection requirement and the main technical index of the designed system on chip;
specifically, the connection requirement in this embodiment is specifically: the method is oriented to the real-time processing requirement of big data, multi-chip mesh interconnection is realized, and the bottleneck problem of the transmission rate among a plurality of chips is solved; the main technical indexes are as follows: the overall speed reaches 3000Gbps, the single-channel speed is 25Gbps, the connection link is more than or equal to 40, and the processor is more than or equal to 4;
the connection structure in the prior art can be divided into a linear connection structure, a mesh connection structure, a cross connection structure and a mixed connection structure, and as the internal logic gate circuit of the chip is continuously increased and the data interaction between multiple chips is more frequent, the selection of the connection structure is an important link of system design and directly determines the communication speed of the multi-chip system; by comparing the connection structures, the linear connection structure has a single form, has larger time delay, and cannot support parallel and complex communication among multiple chips, so that the linear connection structure cannot be selected; the cross-connection structure has a simple structure, can realize flexible communication of any plurality of chips, needs to additionally introduce an FPID device, occupies the area of a circuit board, increases the system cost, and has low cost performance for a system with a small number of chips, so that the cross-connection structure cannot be selected; for the network connection structure, on one hand, the structure has regular layout, has small time delay difference and can simplify the connection communication between multiple chips, on the other hand, the structure is suitable for multiple chip systems with any number, and when the requirement is insufficient, the expansion of the system can be conveniently realized by increasing the number of the chips. Therefore, in the present embodiment, the mesh connection structure is selected as the basic connection structure between chips; the chip is an FPGA chip;
specifically, as shown in fig. 2, the adjustable chip connection structure specifically includes: the chip comprises 5 chips, wherein a chip _ A, a chip _ B, a chip _ C and a chip _ D are in a cross connection structure; meanwhile, in order to improve the transmission rate of the whole plurality of chips, a chip _ X is simultaneously arranged on the mesh connection structure, and fixed connection lines are added for directly or indirectly connecting the chip _ X with the chip _ a, the chip _ B, the chip _ C and the chip _ D.
Furthermore, the 4 chips _ a, chip _ B, chip _ C and chip _ D are arranged according to a square structure, and are connected in a pairwise cross manner to form an eight-path mesh connection structure;
furthermore, because the traditional connection structure is in a fixed connection form, once the connection mode is determined, the topological structure of the system cannot be changed, which is not favorable for flexible and free communication among a plurality of chips and cannot meet the requirements of a complex and changeable system-on-chip, in this embodiment, according to the system index requirements, the mesh connection structure and the communication mode are combined, and the characteristic that optical fibers can be freely connected is utilized, this embodiment proposes an adjustable connection structure design, an optical transceiver module is set to be physically separable from the plurality of chips, if the connection communication mode among the plurality of chips needs to be changed, only the connection mode of the optical transceiver module and the optical fibers in a connection network needs to be changed, which can be carried out in the actual work of the system, thereby realizing flexible and free communication among the plurality of chips; the optical transceiver module can be detachably or extendably connected with the chip, and when the high-speed and flexible communication requirements exist, the optical transceiver modules can be separated from the respective chips and arranged in an array, so that optical path exchange is facilitated, and the position movement and exchange of optical fibers can be realized by using mechanisms such as MEMS (micro-electromechanical systems) and the like, so that flexible and variable optical path connection can be realized.
Illustratively, taking chip _ C as an example, there are 12 high-speed transmission links in chip _ C accessing to the connection network, and these 12 links can all be used to complete the connection with chip _ D; the structure can realize the function of flexibly adjusting the connection mode among the multiple chips according to the connection and bandwidth requirements of the current chip, greatly facilitate the data communication among the multiple chips and greatly improve the transmission rate among the chips.
Step 2: the data transmission between the chips is realized by adopting a mode of combining serial transmission and an optical interface;
for a system on a chip, abundant connection links can greatly improve the communication efficiency of the system, and the connection links are limited by IO pin ports of chips, in order to realize high-bandwidth and high-reliability data transmission between the chips, a mode of combining serial transmission and an optical interface is adopted in the embodiment, at this time, the communication mode between the chips is not a multi-parallel line connection communication, but a high-speed differential serial connection communication, the connection communication mode can be completed through a high-speed transceiver on the chip, the high-speed transceiver is compatible with various high-speed serial protocols and supports a higher transmission rate, multi-bit parallel signals inside the chip are finally converted into serial signals through time division multiplexing and are transmitted between the chips in a differential mode, and the required IO pin ports of the chips are greatly reduced; meanwhile, the high-speed transceiver is externally connected with the optical transceiver module and the optical fiber, and the high-speed differential electric signal is converted into an optical signal for transmission, so that the transmission rate is ensured.
The following will be described in detail for a high-speed transceiver architecture:
the high-speed transceiver consists of a transmitting end and a receiving end, wherein the functions of the two parts are independent and both comprise a physical medium adaptation layer (PMA) sublayer and a Physical Coding Sublayer (PCS) sublayer. The PMA sublayer contains circuits for high speed serial-to-parallel conversion, pre-emphasis, post-emphasis, and clock recovery. The PCS sublayer comprises circuits such as a data bit width conversion circuit, a pseudo-random sequence generation circuit, an 8B/10B coding and decoding circuit, a gearbox for transmitting 64B/66B and 64B/67B coded data, a buffer area, a channel binding circuit, a polarity reversing circuit and the like;
the high-speed transceiver sending end processing flow is that firstly, data enters a sending end PCS through an interface, whether 8B 10B coding is carried out or not is selected according to requirements, if 64B/66B coding data or 64B/67B coding data is transmitted, the 8B/10B coding function is not needed, and data transmission is carried out through a sending end gearbox. Whether the data are transmitted to a PMA (permanent magnetic access) sending end after the Buffer and the polarity inversion of the sending end are selected to convert the low-speed parallel data into high-speed serial data or not, and operations such as pre-emphasis can be performed on the data. In addition, the transmitting end can generate pseudo random check data of a PRBS7 mode, a PRBS15 mode, a PRBS23 mode or a PRBS31 mode;
the receiving end processing flow of the high-speed transceiver is that firstly, the received high-speed serial data is converted into low-speed parallel data in a serial-parallel mode through a PMA of the receiving end, then the low-speed parallel data is transmitted to a PCS of the receiving end, polarity inversion selection is firstly carried out, then word alignment is carried out, and then whether 8B/10B decoding is carried out or not is selected. If the 64B/66B code or the 64B/67B code data is transmitted, the 8B/10B decoding module is not used, the transmission is carried out through a transmission box of the receiving end, and finally the transmission reaches an interface of the receiving end.
Furthermore, in this embodiment, the communication protocol using serial transmission is an SRIO protocol; the SRIO protocol is a standard communication protocol, and uses high-speed Serdes (high-speed serial-parallel conversion transceiver) as a physical layer interface, so that flow control, exchange and photoelectric transmission can be realized, and the SRIO protocol has the potential of constructing a networked spatial information system. The SRIO protocol has the advantages of simple transmission protocol, support of various network topologies and small software dependence, and is suitable for realizing high-speed interconnection of the embedded system in a severe space environment. The SRIO protocol supports 5 basic network topology structures, namely a double-star interconnection topology, a single-star expansion topology, a full interconnection topology and a partial interconnection topology.
The SRIO protocol can complete the exchange and forwarding of data through a physical layer and a transport layer, and the switching node realizes its switching function by the routing of packets. In the SRIO interconnection system, each addressable device at least has one unique DeviceID, when a communication node generates a data packet, the destiD and sourceID are placed in a header, a routing table is arranged in an SRIO switching part to map different DeviceIDs to physical ports, the SRIO switching part obtains the destiD and sourceID of the current packet by analyzing the received header and transmits the routing table to search the corresponding physical port, and the corresponding port is switched on after the search is finished to realize the routing operation of the packet, thereby finishing the switching.
Furthermore, in this embodiment, a high-speed transceiver is used to connect an optical transceiver module and an optical fiber to implement high-speed optical interconnection communication between multiple chips, so before a system optical interface design is developed, type selection of the optical transceiver module is performed first, where the type selection is based on a transmission rate and channel density mainly supported by the module, for chips _ a to _ D, a system requires each chip to implement a twelve-channel 6.25Gbps high-speed transceiver link, and the area occupied by the optical transceiver module is large, so channel density is emphasized more on the type selection of the optical transceiver module, the optical transceiver module supports 4-channel optical transmission and 4-channel optical reception, has high port density, and a single-channel transmission rate of 10.5Gbps, and can meet a single-channel 6.25Gbps high-speed transceiver index requirement in a to chip _ D, and therefore, in the design of this embodiment, 10 optical interfaces of this type are provided for chips _ a to _ D to implement 40-channel high-speed optical interconnection transceiving;
after the optical transceiver module is selected, the optical interface circuit of the optical transceiver module can be designed, taking the optical interfaces used in the chip _ a to the chip _ D as an example, the interface mode is a double-sided gold finger socket, the total number of electrical interface pins of the optical interface is 38, and the optical interface has high integration level, so that the optical interface circuit is strictly in accordance with the standard during design.
It should be noted that, considering the area and the transmission distance of the system on chip, the connection between chip _ X and chip _ a and chip _ B is implemented by internal PCB high-speed routing connection.
Finally, the high-speed chip data transmission method provided by the embodiment can support 42-channel optical links, wherein the maximum transmission rate of 2 channels of single channel reaches 25Gbps, and is completed by a chip _ X; and the transmission rate of 40 paths of single channels is 6.25Gbps which is finished from the chip _ A to the chip _ D, so that the transmission rate between the chips is greatly improved.
In summary, the present embodiment provides a method and an apparatus for high-speed transmission of data between chips, which provides an inter-chip data transmission structure for solving the technical problem in the prior art that the data transmission rate between multiple chips is not high, and realizes the data transmission between chips by setting an adjustable chip connection structure and adopting a mode of combining serial transmission and an optical interface, where the connection link of a system on chip is sufficient and the connection mode is adjustable, thereby greatly improving the transmission rate between chips.
According to another embodiment of the present invention, an inter-chip high-speed transmission apparatus is characterized in that: the optical path transceiver module is used for executing the inter-chip high-speed transmission method.
According to another embodiment of the invention, a system on a chip, characterized by: the device comprises the inter-chip data high-speed transmission device.
The above-described embodiments and/or implementations are only for illustrating the preferred embodiments and/or implementations of the present technology, and are not intended to limit the implementations of the present technology in any way, and those skilled in the art can make many modifications or changes without departing from the scope of the technology disclosed in the present disclosure, but should be construed as technology or implementations that are substantially the same as the present technology.
Claims (10)
1. A method for transmitting data between chips at high speed is characterized by comprising the following steps:
step 1: setting an adjustable chip connecting structure according to the connecting requirement and technical index of the system on chip to be designed;
step 2: the data transmission among a plurality of chips is realized by adopting a mode of combining serial transmission and an optical interface;
the step 2 specifically comprises: the method comprises the following steps that a high-speed differential serial connection communication mode is adopted, the high-speed differential serial connection communication mode is completed through a high-speed transceiver on a chip, the high-speed transceiver is compatible with multiple high-speed serial protocols, and multi-bit parallel signals in the chip are finally converted into serial electric signals through time division multiplexing and transmitted between the chips in a differential mode; meanwhile, the high-speed transceiver is externally connected with an optical transceiver module and an optical fiber, and the high-speed differential electric signal is converted into an optical signal for transmission;
the adjustable connecting structure comprises: the optical transceiver module is physically separable from the plurality of chips, and if the connection communication mode among the plurality of chips needs to be changed, the connection mode of the optical transceiver module and the optical fiber in the connection network only needs to be changed.
2. The method according to claim 1, wherein in step 1, the connection requirement is specifically: mesh interconnection among a plurality of chips is realized; the technical indexes comprise: the overall speed reaches 3000Gbps, the single-channel speed is 25Gbps, the connection link is more than or equal to 40, and the processor is more than or equal to 4.
3. The method of claim 1, wherein a mesh connection structure is selected as a basic connection structure between chips.
4. The method according to claim 3, wherein the adjustable chip connection structure is specifically: the chip comprises 5 chips, wherein a chip _ A, a chip _ B, a chip _ C and a chip _ D are in a cross connection structure; and simultaneously, a chip _ X is arranged, and fixed connecting wires are added for the direct or indirect connection of the chip _ X with the chip _ A, the chip _ B, the chip _ C and the chip _ D.
5. The method according to claim 4, wherein the chip _ A, the chip _ B, the chip _ C and the chip _ D are arranged in a square structure, and are connected in a cross manner two by two to form a mesh connection structure.
6. The method of claim 1, wherein the high-speed transceiver comprises a transmitting end and a receiving end, the two parts are independent and each comprise two sublayers, namely a physical medium adaptation layer (PMA) and a Physical Coding Sublayer (PCS), and the PMA sublayer comprises high-speed serial-to-parallel conversion, pre-emphasis, post-emphasis and clock recovery circuits; the PCS sublayer comprises a data bit width conversion circuit, a pseudo-random sequence generation circuit, an 8B/10B coding and decoding circuit, a gearbox for transmitting 64B/66B and 64B/67B coded data, a buffer area, a channel binding circuit and a polarity reversing circuit.
7. The method according to claim 6, wherein the sending end of the high-speed transceiver processes:
firstly, data enters a PCS sublayer of a sending end through an interface, whether 8B/10B coding is carried out or not is selected according to requirements, if 64B/66B coding data or 64B/67B coding data are transmitted, the 8B/10B coding function is not needed, and data transmission is carried out through a transmission case of the sending end;
and then selecting whether to convert low-speed parallel data into high-speed serial data by a PMA sublayer which transmits the data to the transmitting end after the Buffer and the polarity inversion of the transmitting end and also selecting whether to perform pre-emphasis operation on the data, wherein the transmitting end can generate pseudo-random check data in a PRBS7 mode, a PRBS15 mode, a PRBS23 mode or a PRBS31 mode.
8. The method according to claim 6, wherein the processing procedure at the receiving end of the high-speed transceiver is as follows:
firstly, carrying out serial-parallel conversion on received high-speed serial data through a PMA sublayer of the receiving end to obtain low-speed parallel data, transmitting the low-speed parallel data to a PCS sublayer of the receiving end, firstly carrying out polarity inversion selection, and then carrying out word alignment;
and then selecting whether to perform 8B/10B decoding, if transmitting 64B/66B coding or 64B/67B coding data, transmitting through a receiving end gearbox without using an 8B/10B decoding module, and finally reaching a receiving end interface.
9. The method according to claim 1, wherein the communication protocol of serial transmission in step 2 is SRIO protocol, data exchange and forwarding are performed through physical layer and transport layer, the switching node realizes its switching function by packet routing, in the SRIO interconnect system, each addressable device has at least one unique DeviceID, when the communication node generates a data packet, the destceid and sourceID are placed in the header, a routing table is arranged inside the SRIO switching component to map different deviceids to physical ports, the SRIO switching component obtains the destceid and sourceID of the current packet by parsing the received header and outputs the routing table to find the corresponding physical ports, and after the finding, the corresponding ports are turned on to realize packet routing operation, thereby completing switching.
10. A kind of data high-speed transmission device between chips, characterized by that: the optical path transceiver module is used for executing the inter-chip data high-speed transmission method in any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211173384.8A CN115269487B (en) | 2022-09-26 | 2022-09-26 | Inter-chip data high-speed transmission method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211173384.8A CN115269487B (en) | 2022-09-26 | 2022-09-26 | Inter-chip data high-speed transmission method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115269487A CN115269487A (en) | 2022-11-01 |
| CN115269487B true CN115269487B (en) | 2023-01-10 |
Family
ID=83757311
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211173384.8A Active CN115269487B (en) | 2022-09-26 | 2022-09-26 | Inter-chip data high-speed transmission method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115269487B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1695130A (en) * | 2002-08-30 | 2005-11-09 | 英特尔公司 | Multi-port high-speed serial fabric interconnect chip in a meshed configuration |
| CN205320075U (en) * | 2015-12-31 | 2016-06-15 | 上海航天科工电器研究院有限公司 | Multi -service digit optical transmitter and receiver based on optic fibre ethernet |
| CN106788732A (en) * | 2015-11-24 | 2017-05-31 | 上海航天科工电器研究院有限公司 | A kind of Low speed photo modular converter |
| WO2022037511A1 (en) * | 2020-08-20 | 2022-02-24 | 华为技术有限公司 | Light source module and optical communication device |
-
2022
- 2022-09-26 CN CN202211173384.8A patent/CN115269487B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1695130A (en) * | 2002-08-30 | 2005-11-09 | 英特尔公司 | Multi-port high-speed serial fabric interconnect chip in a meshed configuration |
| CN106788732A (en) * | 2015-11-24 | 2017-05-31 | 上海航天科工电器研究院有限公司 | A kind of Low speed photo modular converter |
| CN205320075U (en) * | 2015-12-31 | 2016-06-15 | 上海航天科工电器研究院有限公司 | Multi -service digit optical transmitter and receiver based on optic fibre ethernet |
| WO2022037511A1 (en) * | 2020-08-20 | 2022-02-24 | 华为技术有限公司 | Light source module and optical communication device |
Non-Patent Citations (1)
| Title |
|---|
| 智能变电站的工业以太网交换机组网测试技术;张小飞 等;《电力系统通信》;20200610;1-4+9 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115269487A (en) | 2022-11-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6721313B1 (en) | Switch fabric architecture using integrated serdes transceivers | |
| CN109947681B (en) | Serializer/deserializer and high-speed interface protocol exchange chip | |
| CN101753388B (en) | Routing and interface device suitable for on-chip and inter-chip extension of multi-core processor | |
| US8443124B2 (en) | Physical layer device having an analog SERDES pass through mode | |
| EP1558987B1 (en) | A multi-rate, multi-port, gigabit serdes transceiver | |
| US7890680B2 (en) | Physical layer device having a serdes pass through mode | |
| US20100254703A1 (en) | Optical Network for Cluster Computing | |
| US20100254652A1 (en) | Optical Network for Cluster Computing | |
| CN112905520B (en) | Data transfer events for interconnected dies | |
| CN114185840B (en) | Three-dimensional multi-die interconnection network structure | |
| CN107104737B (en) | A kind of node device port expansion system and method based on optical fiber interconnections | |
| CN108683536B (en) | Configurable dual-mode converged communication method of asynchronous network on chip and interface thereof | |
| CN110515879B (en) | Asynchronous transmission device and transmission method thereof | |
| WO2022088542A1 (en) | Fpga-based usb3.0/3.1 control system | |
| CN116383114A (en) | Chip, chip interconnection system, data transmission method, electronic device and medium | |
| CN116578528A (en) | Multi-FPGA prototype verification platform hardware architecture of multi-mode hybrid interconnection architecture | |
| CN114691558A (en) | Low-delay retimer and delay control method | |
| CN115269487B (en) | Inter-chip data high-speed transmission method and device | |
| CN101009542A (en) | Extension device of data network node device port | |
| CN109561032A (en) | A kind of switch module and the interchanger including it | |
| CN1507285A (en) | Method of realizing router chip of group exchange network with FPGA device | |
| CN108429938A (en) | In reconfigurable arrays processor optical interconnection network is communicated between cluster | |
| US20010021187A1 (en) | Multidimensional crossbar network and parallel computer system | |
| CN115809210A (en) | LVDS high-speed data switch based on FPGA | |
| WO2018196833A1 (en) | Message sending method and message receiving method and apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |