CN1983917B - Method and structure for realizing progrmmable logic device data exchange - Google Patents
Method and structure for realizing progrmmable logic device data exchange Download PDFInfo
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- CN1983917B CN1983917B CN2005101305243A CN200510130524A CN1983917B CN 1983917 B CN1983917 B CN 1983917B CN 2005101305243 A CN2005101305243 A CN 2005101305243A CN 200510130524 A CN200510130524 A CN 200510130524A CN 1983917 B CN1983917 B CN 1983917B
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Abstract
The invention is concerned with the method that the programmable logical device achieves data exchange, includes the following steps: confirms the data multiplying multiple N, uses the RAM integrating on the programmable logical device to creates the base data exchange module from N path data input to N path data output, constructs the data exchange module based on the base data exchange module from M path data input to L path data output; based on the working clock frequency, multiplying the M path inputting data as group K, and sends it to the corresponding K number inputting end of the data exchange module respectively, multiplying the L path outputting data identification as the group j, and sends it to the corresponding J read address port of the data exchange module respectively; processes the releasing multiplying to the data of the data exchange module in order to get the L path output data. The invention is also concerned with the data exchange module fitting for the above method. The invention can achieve the data exchange between the different inputting data path number and the outputting path number, and save logical resource.
Description
Technical field
The present invention relates to the method for interchanging data in the communication system, especially relate to a kind of method of utilizing programmable logic device to realize exchanges data, and realize the required a kind of data exchange module of this method.
Background technology
Exist various exchanges data circuit in communication system, these exchanges data circuit are all realized with special integrated chip usually.This method of utilizing special integrated chip to realize exchanges data has the following shortcoming: cost is higher; Applicability is not strong, has certain wasting of resources; In addition, owing to the special integrated chip function singleness, be unfavorable for improving the integrated level of system.Therefore, some strong communications equipment manufacturer use the special integrated chip of own company design to realize exchanges data, though under the big situation of product lot quantity, make cost-saved in this way, but at the special integrated chip initial stage of development, the R﹠D costs height, the development﹠ testing cycle is long, and this is that general product designer institute is unaffordable.
At present, high speed development along with the chip integrated technology, the integrated level of programmable logic device is more and more higher, scale is increasing, and cost is also more and more lower, it is low to adopt programmable logic device to realize that the large-scale data exchange has become a kind of cost, and applicability is good, the good selection that level of integrated system is high.Increasing product designer uses scale programmable logic device to realize the function that they need, and wherein also comprises the exchanges data circuit.Normally, the employed scale programmable logic device of product designer is field programmable gate array (Field Programmable Gates Array abbreviates FPGA as).
In the prior art, the exchanges data implementation method mainly contains following two exchange characteristics, first exchange characteristics are to utilize the logical resource of FPGA, be that trigger resources and combination logic resource realize exchanges data, attainable like this exchanges data scale is by the logical resource scale decision of selected FPGA; The input and output that another exchange characteristics are requirement exchanges data are symmetrical, and promptly Jiao Huan dateout way equals to import the data way.In FPGA, logical resource is one of the most valuable resource, realize that any function all needs to rely on this resource, if consume too much logical resource in order to realize data exchanging function, when realizing other functions, will be subjected to certain restriction so: or reduce the function that FPGA realizes, reduce level of integrated system; Improve the FPGA scale, increase product cost.Therefore, all realize exchanges data, have certain disadvantage with the logical resource of FPGA.In addition; present communication products function becomes increasingly abundant changeable, and regular meeting runs into various data exchanging function demand, as: it is few that the input way is exported way more; perhaps exporting way, to import way few more, and adopt the exchanges data circuit of input and output symmetry can not satisfy the demand this moment.
Summary of the invention
The technical issues that need to address of the present invention provide method and the structure thereof that a kind of programmable logic device is realized exchanges data, adopt the present invention, the exchanges data between various input data way and the dateout way can be realized easily, logical resource can be saved greatly simultaneously.
In order to solve the problems of the technologies described above, the invention provides the method that a kind of programmable logic device is realized exchanges data, be integrated with some random access memory on the programmable logic device, this method comprises the steps:
(a1) select the also multiplexing multiple N of specified data, utilize described random access memory to generate the master data Switching Module that is input to the output of N circuit-switched data from the N circuit-switched data, be input to the data exchange module of L circuit-switched data output then based on described master data Switching Module structure from the M circuit-switched data;
(a2) determine working clock frequency according to data multiplex multiple N, this working clock frequency is N a times of input data rate;
(a3) based on described working clock frequency, with M road input data multiplex is that K organizes multiplexing input data and is sent to the corresponding K data input of described data exchange module respectively, and identical K is organized K the write address port that multiplexing serial number is sent to described data exchange module; Wherein, multiplexing serial number is from 0 to N-1; If M is the integral multiple of N, then K value is the gained result of M divided by N, otherwise the K value is M to be rounded divided by the gained result of N add 1;
(a4) based on described working clock frequency, dateout sign in L road is multiplexed with the individual address port of reading of corresponding J that J organizes multiplexing dateout sign and is sent to described data exchange module respectively, wherein, if L is the integral multiple of N, then the J value is the gained result of L divided by N, otherwise the J value adds 1 for L is rounded divided by the gained result of N;
(a5) multiplex data to the output of data Switching Module carries out demultiplexing, has been exchanged the L road dateout of finishing.
Further, this method also has following characteristics: when M was not the integral multiple of N, the part that K organizes input data deficiencies in the multiplexing input data was set to 0.
Further, this method also has following characteristics: when L was not the integral multiple of N, the part that J organizes dateout sign deficiency in the multiplexing dateout sign was set to invalid dateout sign.
Further, this method also has following characteristics: described master data Switching Module adopts the table tennis read-write mode to realize exchanges data.
In order to solve the problems of the technologies described above, the present invention also provide a kind of be applicable to said method be input to the data exchange module of L circuit-switched data output from the M circuit-switched data, this data exchange module is made up of J identical being input to the intermediate data exchange module of N circuit-switched data output and connecing from the M circuit-switched data, the input data of the data input pin of each intermediate data exchange module are K and organize multiplexing input data, the input signal of write address port is K and organizes multiplexing serial number, and the input signal of reading address port then is respectively J and organizes in the multiplexing dateout sign and the corresponding one group of multiplexing dateout sign of this middle rank data exchange module; Described intermediate data exchange module is by identical being input to the master data Switching Module of N circuit-switched data output and one from the N circuit-switched data and selecting module to constitute of K, the input data of the data input pin of each master data Switching Module are respectively K and organize in the multiplexing input data and the corresponding one group of multiplexing input data of this master data Switching Module, the input signal of write address port is one group of multiplexing serial number, the input signal of reading address port is corresponding one group of multiplexing dateout sign, this selection module is connected with the data output end of K master data Switching Module, and its selecting side is by the control of corresponding one group of multiplexing dateout sign.
Further, the present invention also has following characteristics: described master data Switching Module is made of random access memory, and this random access memory is that storage depth equals 2N, the storage bit wide equals the dual port random access memory that it imports data bit width.
Further, the present invention also has following characteristics: data input pin is a write port in the described dual port random access memory, and data output end is a read port.
Further, the present invention also has following characteristics: described dual port random access memory adopts the table tennis read-write mode to realize exchanges data.
Compared with prior art, the present invention has the following advantages:
A, the present invention adopt random access memory resource integrated on the programmable logic device to realize necessary a large amount of switches selections of exchanges data and metadata cache function, thereby reduce the use of logical resource;
B, more much more than logical resource because of random access memory resource in common programmable logic device is so adopt the present invention can realize more massive exchanges data;
C, the present invention utilize the master data Switching Module, Jiao Huan input and output way is combined into complete exchanges data circuit according to actual needs, so not only can realize identical or different input data way and the exchanges data between the dateout way, and implementation method is convenient flexibly; In addition, also can expand existing input and output way according to actual needs, compared with prior art, the present invention has better adaptability.
Description of drawings
Fig. 1 is that the present invention adopts programmable logic device to realize the enforcement block diagram of exchanges data;
Fig. 2 is data multiplex and the multiplexing schematic diagram of dateout sign imported before exchanges data of the present invention;
Fig. 3 is that the present invention adopts programmable logic device to realize the schematic flow sheet of exchanges data;
Fig. 4 is the dual port random access memory that the master data Switching Module described in the present invention adopts, and the schematic diagram of inputoutput data and read/write address;
Fig. 5 of the present inventionly expands to the schematic diagram of intermediate data exchange module, wherein M＞N with the master data Switching Module;
Fig. 6 of the present inventionly expands to the schematic diagram of data exchange module, wherein L＞N with intermediate data exchange module;
Fig. 7 is to the schematic diagram of dateout demultiplexing after the exchanges data of the present invention.
Embodiment
In order to understand the present invention in depth, the present invention is described in detail below in conjunction with drawings and the specific embodiments.
In this embodiment, the input data are 60 the tunnel, are designated as M=60, and dateout is 50 the tunnel, is designated as L=50, and the speed of input data is designated as f
0According to the speed of these input data, to select the multiplexing multiple N of suitable data, thereby determine working clock frequency f, this data multiplex multiple value is 8 in this embodiment, is designated as N=8, i.e. f=N * f
0, N is the integer greater than 1, according to the multiplexing multiple of existing higher data, can not strengthen the principle of logic synthesis realization difficulty again and choose data multiplex multiple N; In addition, the value of N is preferably 2 positive integer time power.
Every road dateout in 50 tunnel exchange back dateouts is all disposed a corresponding sign respectively, be referred to as the dateout sign, be designated as ID, each road dateout of the content representation of this sign pairing input data sequence number before exchanges data.
The invention process process as shown in Figure 1, based on working clock frequency, Multiplexing module 101 is multiplexed into 8 groups of multiplexing input data with 60 tunnel input data by 8 the tunnel one groups, is about to 60 road parallel input datas process and string conversion, becomes 8 road serial input datas.Similarly, Multiplexing module 102 also is multiplexed into 7 groups of multiplexing dateout signs by 8 the tunnel one groups with 50 tunnel dateouts sign; Then, each is organized multiplexing input data and multiplexing dateout sign ID deliver to data exchange module 103, be designated as the data exchange module 103 of 60-＞50 from 60 tunnel input data to 50 tunnel dateouts.Through after the exchanges data, the multiplexing dateout of 8 circuit-switched data that 7 groups of data exchange module 103 outputs of 60-＞50 are multiplexing, pass through demultiplexing module 104 at last after, obtain the dateout after 50 tunnel exchanges.
The data exchange module 103 of 60-shown in Figure 1＞50 can be divided into two steps to be realized: the first step is that unit extensions becomes the intermediate data exchange module (being designated as the intermediate data exchange module of 60-＞8) from 60 tunnel input data to 8 tunnel dateouts with the master data Switching Module (being designated as the master data Switching Module of 8-＞8) that is input to the output of 8 circuit-switched data from 8 circuit-switched data earlier; Second step was the data exchange module that unit extensions becomes 60-＞50 with the intermediate data exchange module of 60-＞8.
As shown in Figure 3, the flow process of this embodiment comprises the steps:
Step 301 is selected and the multiplexing multiple N=8 of specified data, thereby determines working clock frequency f, i.e. working clock frequency f=8f
0
Step 302 based on working clock frequency, is imported the time division multiplexing that data are 8:1 with the M=60 road, is multiplexed into 8 groups of multiplexing input data, meanwhile, L=50 road dateout is identified the time division multiplexing of being 8:1, is multiplexed into 7 groups of multiplexing dateouts signs;
Step 303 utilizes dual port random access memory (DPRAM) integrated on the programmable logic device to generate the master data Switching Module of 8-＞8, as shown in Figure 4;
Step 304 is a unit module with the master data Switching Module of 8-＞8, selects for use the master data Switching Module of 8 described 8-＞8 to be extended to the intermediate data exchange module of 60-＞8, as shown in Figure 5;
Step 305, intermediate data exchange module with 60-＞8 is a unit module, select for use the intermediate data exchange module of 7 described 60-＞8 to be extended to the data exchange module of 60-＞50, as shown in Figure 6, and 8 groups of multiplexing input data are sent to corresponding 8 data inputs of the data exchange module of 60-＞50 respectively, identical 8 groups of multiplexing serial numbers (from 0 to 7) are sent to 8 write address ports of the data exchange module of 60-＞50, corresponding 7 of data exchange module that 7 groups of multiplexing dateouts signs are sent to 60-＞50 respectively read address port, realize exchanges data;
Step 306 is carried out demultiplexing to 7 groups of multiplexing dateouts after the data exchange module exchange of 60-＞50, obtains 50 tunnel dateouts, as shown in Figure 7.
Be illustrated in figure 4 as the master data Switching Module 403 of 8-＞8, it is a write port that this DPRAM is provided with its data input pin, and data output end is a read port, with the data input of one group of multiplexing input data 401 as DPRAM write port; The input signal of write address port is one group of multiplexing serial number 402; The input signal of reading address port is corresponding one group of multiplexing dateout sign 405; So just utilize the decoding of DPRAM to read/write address, finished a large amount of switches of realizing with logical resource in the existing method and selected circuit, the order of DPRAM dateout 404 is exactly the order after the desired exchange at this moment.
And the DPRAM among the present invention can adopt the table tennis read-write mode to finish decoding to read/write address (promptly finishing the exchange of input data and dateout).The storage depth of this DPRAM equals 16, so its read/write address can be stored bit wide and equal its input data bit width with 4 bit bit representations.Low 8 addresses among the DPRAM were distinguished as " ping ", the conduct of high 8 addresses " pang " district.Because the way of multiplex data is 8, a circuit-switched data is stored in each address, just in time take 8 addresses, adopt low 3bit effectively to represent, therefore the highest order of address can be used for selecting " ping " district still " pang " district, make read operation carry out at different memory spaces respectively, thereby avoid the read/write conflict of DPRAM with write operation.
As shown in Figure 5, master data Switching Module with 8-＞8 is the intermediate data exchange module that unit extensions becomes 60-＞8, module 501,502 to 508 is the master data Switching Module of 8-＞8, except last master data Switching Module has only been done 4 tunnel exchanges, other master data Switching Modules have all been done 8 tunnel exchanges, have used 8 master data Switching Modules altogether.The data-out port of 8 master data Switching Modules links to each other with selecting module 504, and 8 road multiplex datas of output need be determined the dateout of the intermediate data exchange module of this 60-＞8 through the screening of selecting module 504.The screening process of module 504 is as follows: each master data Switching Module to read the address identical, be one group of multiplexing dateout sign, the numerical value of each sign is between 0～59, available 6bit represents; But storing every road multiplex data, DPRAM only needs 8 memory cell, therefore the low 3bit that identifies numerical value has only been used in the real address of reading, and its high 3bit can be used as selecting the control of module 504 selecting side SEL, the dateout of which master data Switching Module is selected in i.e. control, as the dateout of the intermediate data exchange module of 60-＞8.
As shown in Figure 6, intermediate swap data module with 60-＞8 is the data exchange module that unit extensions becomes 60-＞50, module 601,602 to 607 all is the intermediate data exchange module of 60-＞8, except last data exchange module has only been done 2 tunnel exchanges, other data exchange modules have all been done 8 tunnel exchanges, have used the intermediate data exchange module of 7 60-＞8 altogether.The input data of the intermediate data exchange module of each 60-＞8 and input write address are identical, and input is read the address and is respectively 7 groups of multiplex data output identifications, dateout after the exchange is 7 road multiplex datas like this, and except that last road multiplex data, every road multiplex data has comprised 8 tunnel dateouts.
As shown in Figure 7,7 tunnel multiplexing dateouts 701,702 to 707 after the exchange are carried out demultiplexing through demultiplexing module 801,802 to 807, so just obtain 50 channel parallel datas, arrive this, data exchanging completed from 60 tunnel input data to 50 tunnel dateouts.
Therefore, the present invention can realize the exchanges data between various input data way and the dateout way according to actual needs flexibly and easily, and can also save logical resource greatly, thereby realizes more massive exchanges data.
Claims (8)
1. the method for a programmable logic device realization exchanges data is integrated with some random access memory on the programmable logic device, and this method comprises the steps:
(a1) select the also multiplexing multiple N of specified data, utilize described random access memory to generate the master data Switching Module that is input to the output of N circuit-switched data from the N circuit-switched data, be input to the data exchange module of L circuit-switched data output then based on described master data Switching Module structure from the M circuit-switched data;
(a2) determine working clock frequency according to data multiplex multiple N, this working clock frequency is N a times of input data rate;
(a3) based on described working clock frequency, with M road input data multiplex is that K organizes multiplexing input data and is sent to the corresponding K data input of described data exchange module respectively, and identical K is organized K the write address port that multiplexing serial number is sent to described data exchange module; Wherein, multiplexing serial number is from 0 to N-1; If M is the integral multiple of N, then K value is the gained result of M divided by N, otherwise the K value is M to be rounded divided by the gained result of N add 1;
(a4) based on described working clock frequency, dateout sign in L road is multiplexed with the individual address port of reading of corresponding J that J organizes multiplexing dateout sign and is sent to described data exchange module respectively, wherein, if L is the integral multiple of N, then the J value is the gained result of L divided by N, otherwise the J value adds 1 for L is rounded divided by the gained result of N;
(a5) multiplex data to the output of data Switching Module carries out demultiplexing, has been exchanged the L road dateout of finishing.
2. a kind of programmable logic device according to claim 1 is realized the method for exchanges data, it is characterized in that: when M was not the integral multiple of N, the part that K organizes input data deficiencies in the multiplexing input data was set to 0.
3. a kind of programmable logic device according to claim 2 is realized the method for exchanges data, it is characterized in that: when L was not the integral multiple of N, the part that J organizes dateout sign deficiency in the multiplexing dateout sign was set to invalid dateout sign.
4. a kind of programmable logic device according to claim 3 is realized the method for exchanges data, it is characterized in that: described master data Switching Module adopts the table tennis read-write mode to realize exchanges data.
One kind be applicable to the described method of claim 1 be input to the data exchange module of L circuit-switched data output from the M circuit-switched data, it is characterized in that: this data exchange module is made up of J identical being input to the intermediate data exchange module of N circuit-switched data output and connecing from the M circuit-switched data, the input data of the data input pin of each intermediate data exchange module are K and organize multiplexing input data, the input signal of write address port is K and organizes multiplexing serial number, and the input signal of reading address port then is respectively J and organizes in the multiplexing dateout sign and the corresponding one group of multiplexing dateout sign of this middle rank data exchange module; Described intermediate data exchange module is by identical being input to the master data Switching Module of N circuit-switched data output and one from the N circuit-switched data and selecting module to constitute of K, the input data of the data input pin of each master data Switching Module are respectively K and organize in the multiplexing input data and the corresponding one group of multiplexing input data of this master data Switching Module, the input signal of write address port is one group of multiplexing serial number, the input signal of reading address port is corresponding one group of multiplexing dateout sign, this selection module is connected with the data output end of K master data Switching Module, and its selecting side is by the control of corresponding one group of multiplexing dateout sign.
6. data exchange module according to claim 5, it is characterized in that: described master data Switching Module is made of random access memory, and this random access memory is that storage depth equals 2N, the storage bit wide equals the dual port random access memory that it imports data bit width.
7. data exchange module according to claim 6 is characterized in that: data input pin is a write port in the described dual port random access memory, and data output end is a read port.
8. data exchange module according to claim 7 is characterized in that: described dual port random access memory adopts the table tennis read-write mode to realize exchanges data.
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| CN107145457B (en) * | 2017-04-25 | 2019-10-29 | 电子科技大学 | The device and method of multichannel valid data transmission is promoted based on piece RAM |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1507285A (en) * | 2002-12-06 | 2004-06-23 | 中国科学院计算技术研究所 | Method of realizing router chip of group exchange network with FPGA device |
| CN1571346A (en) * | 2003-07-15 | 2005-01-26 | 中兴通讯股份有限公司 | Method of multi-port received and transmitted packet number statistic in network information exchange |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1507285A (en) * | 2002-12-06 | 2004-06-23 | 中国科学院计算技术研究所 | Method of realizing router chip of group exchange network with FPGA device |
| CN1571346A (en) * | 2003-07-15 | 2005-01-26 | 中兴通讯股份有限公司 | Method of multi-port received and transmitted packet number statistic in network information exchange |
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