CN105373348A - Hardware implementation system and method for hybrid memory - Google Patents
Hardware implementation system and method for hybrid memory Download PDFInfo
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- CN105373348A CN105373348A CN201510698601.9A CN201510698601A CN105373348A CN 105373348 A CN105373348 A CN 105373348A CN 201510698601 A CN201510698601 A CN 201510698601A CN 105373348 A CN105373348 A CN 105373348A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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Abstract
The invention relates to the field of a memorizer, and in particular to a hardware implementation system and method for a hybrid memory. The hybrid memory at least comprises N DRAM memorizers, at least an NCM memorizer, an address lookup conversion module, a control module and a multiplexer, wherein the N DRAM memorizers are divided into a main distributing region and a tail end distributing region according to DRAM storage unit retention time; N is an integer; the at least one NCM memorizer can substitute the DRAM memorizers to store the storage data in the tail end distributing region of the DRAM memorizers; the address information of the storage data in the tail end distributing region in the DRAM memorizers and the corresponding address information in the NCM memorizer for substituting the DRAM memorizers to store the storage data in the tail end distributing region in the DRAM memorizers are pre-stored in the address lookup conversion module; the control module is used for obtaining address information and address mapping relation, and judging the output access source of the system data according to the address information and address mapping relation, and the control module generates and outputs a control signal according to the source of the output access; and the multiplexer is connected with the control module, the DRAM memorizers and the NCM memorizer separately for receiving the control signal and selecting data for outputting according to the control signal.
Description
Technical field
The present invention relates to memory area, particularly relate to a kind of system for implementing hardware and the method that mix internal memory.
Background technology
Decades in the past, dynamic RAM (DynamicRandomAccessMemory, DRAM) cost constantly reduces along with Moore's Law.But along with characteristic dimension is more and more less, the requirement of chip to power consumption is more and more higher, because therefore the electric leakage of DRAM memory capacitance just must refresh once at set intervals, refresh power consumption is increasing, Fig. 1 is proportion and the trend schematic diagram of DRAM refresh power consumption in prior art, as shown in Figure 1, DRAM refresh power consumption increases further along with the increase of DRAM capacity.The refresh cycle of DRAM is determined by the retention time of electric charge in its storage unit.
Fig. 2 a-2b is DRAM retention time distribution schematic diagram in prior art; Wherein Fig. 2 a is overall distribution preview graph, Fig. 2 b is rear distribution plan, retention time distribution mainly comprises two parts, a part is main distributive province (maindistribution), another part is tail end distributive province (taildistribution), and schematic diagram as illustrated in figures 2 a-2b.Can find out in figure, retention time of most of storage unit can reach the 1s even longer time, and only has storage unit distribution less than 1% at tail end, their retention time lower than 1s, even less than 100ms.But determine the storage unit (tailbit) that the rear-end maintenance data capability that distributes exactly of DRAM refresh time is the poorest.At present, the refresh cycle of DRAM storage chip is 64ms, 128ms, 256ms etc.Refresh operation not only can produce refresh power consumption, also can reduce DRAM performance simultaneously, because system can not conduct interviews to DRAM when performing refresh operation.
Fig. 3 is a kind of mixing DRAM structural representation in prior art, has a kind of method improving the refresh cycle to be exactly the mode adopting mixing internal memory at present, adds non-volatile novel memory devices, as shown in Figure 3.Under the non-busy state of DRAM by the data batchmove that is stored in the storage unit of DRAM tail end distributive province in novel memory devices, then improve the DRAM refresh cycle, thus greatly can reduce the refresh power consumption of DRAM, improve the performance of DRAM.
This technical scheme also has many problems not solve, such as when Memory Controller Hub is to mixing memory request data, have sent an address to mixing internal memory, how mixing internal memory determines that the data corresponding to this address are stored in NCM, still be stored in DRAM, the physical address of NCM and the physical address of DRAM are again how to realize mapping, and this is all the technical leak adding NCM storage.
Summary of the invention
Realize the leak of mixing internal memory existence for NCM in prior art, the invention provides a kind of system for implementing hardware and the method that mix internal memory, promote the refresh cycle of DRAM array, reduce refresh power consumption.
The present invention adopts following technical scheme:
Mix a system for implementing hardware for internal memory, described system for implementing hardware comprises:
N number of DRAM storer, is divided into main distributive province and tail end distributive province according to the DRAM storage unit retention time by described DRAM storer, and N is positive integer;
At least one NCM storer, is connected with described DRAM storer, can substitute the data that the tail end distributive province stored in described DRAM storer stores;
Address search modular converter, be connected with described DRAM storer, described NCM storer respectively, and prestore in described address search modular converter and comprise tail end distributive province in described DRAM storer and store address information in order to tail end distributive province data in the described DRAM storer of alternative storage in the address information of data and NCM storer corresponding with it;
Control module, be connected with described address search modular converter, to obtain and to judge the source of the output channel of described system data according to described address information and described address mapping relation, and described control module generates according to the source of described output channel and exports control signal;
MUX, is connected with described control module, described DRAM storer, described NCM storer respectively, receives and selects data to export according to described control signal.
Preferably, described NCM storer is N number of, and all described with one the NCM storer of DRAM storer described in each is connected.
Preferably, described hardware implementing comprises:
Logic detection module, be connected with described DRAM storer, periodic detection also determines the retention time boundary of described DRAM storer tail end distributive province and described main distributive province, judges to be positioned at the address information that tail end distributive province described in DRAM storer stores data simultaneously.
Preferably, described address search modular converter comprises:
DRAM address storage array, stores the address information that tail end distributive province replaced in described DRAM storer stores data;
NCM address storage array, stores tail end distributive province in alternative described DRAM storer and stores the address information of the NCM storer of data.
Preferably, described system also comprises:
Search data register, be connected with described DRAM address storage array, and
When needs realize DRAM address search in described address search modular converter, data register is searched described in being inputed to described DRAM address, described to search data register by described DRAM address spaces be matched data line, mates one by one in described storage array.
Preferably, described system also comprises:
Read induction amplifier, be connected with described DRAM address storage array, described control module respectively, and
Described reading induction amplifier reads matched data according to the result of coupling.
Preferably, described system also comprises: described reading induction amplifier judges by the result reading matched line the described DRAM address that whether there is coupling in the storage array of described DRAM address.
Preferably, described system also comprises:
Code translator, is connected with described reading induction amplifier, described NCM address storage array, described control module respectively, and
In time there is the described DRAM address matched in the storage array of described DRAM address, code translator carries out decoding to the data of described coupling and is converted into the address of described NCM address storage array.
Mix a Hardware Implementation for internal memory, described Hardware Implementation comprises:
Step S1: send request of data respectively to DRAM storer, address search modular converter;
Step S2: described address search modular converter receives the physical address of described request of data, and judge whether the physical address of described request data is present in the DRAM address list in described address search modular converter; If so, then step S3 is performed, if not, then perform step S4.
Step S3: control module produces control signal and is sent to MUX, and MUX is selected to export in the data of NCM storer according to described control signal, and is sent in NCM storer by NCM physical address corresponding for the DRAM address of coupling.
Step S4: the data read in described DRAM storer export on data bus through described MUX by control module.
Preferably, described Hardware Implementation also comprises:
Step S31: after step S3, described NCM storer reads data according to described NCM physical address, and exports the data of reading to data bus through MUX.
The invention has the beneficial effects as follows:
The present invention proposes a kind of particular hardware implementation method mixing internal memory, stored the mapping relations of DRAM address and NCM address by address search conversion table, exported from DRAM or NCM by lookup result control data.The performance impact of this Hardware Implementation of the present invention to mixing internal memory is very little, but can obtain the lifting of the refresh cycle of DRAM array, reduces refresh power consumption.
Accompanying drawing explanation
Fig. 1 is proportion and the trend schematic diagram of DRAM refresh power consumption in prior art;
Fig. 2 a-2b is DRAM retention time distribution schematic diagram in prior art;
Fig. 3 is a kind of mixing DRAM structural representation in prior art;
Fig. 4 a-4b is the schematic diagram of the present invention's two kinds of mixing internal storage structure embodiments one;
Fig. 5 a-5b is the hardware implementing structural drawing of the present invention's mixing internal memory;
Fig. 6 is that the present invention adopts TCAM or CAM to realize the structural representation of address search conversion table;
Fig. 7 is a kind of schematic diagram mixing the Hardware Implementation embodiment two of internal memory of the present invention;
Fig. 8 is the browsing process schematic diagram of the present invention's mixing internal memory.
Embodiment
It should be noted that, when not conflicting, following technical proposals, can combine between technical characteristic mutually.
Below in conjunction with accompanying drawing, embodiment of the present utility model is further described:
Embodiment one
Fig. 4 a-4b is the schematic diagram of the present embodiment two kinds of mixing internal storage structure embodiments one, and the present embodiment proposes a kind of particular hardware implementation mixing internal memory.This mixing of the present embodiment internal memory comprises traditional DRAM memory block and novel memory devices (NCM) district, the minimum access bit wide of described DRAM memory block and NCM memory block should be consistent, 64 bit data can be read to DRAM read operation such as at present, so also 64 bit data should be read to NCM read operation.General memory all can be made up of multiple dram chip thus can parallel processing, quickening DRAM access speed and increase data bandwidth.
Mixing internal memory has two kinds of structures: the first only has a NCM storage chip, as shown in accompanying drawing 4a, suppose that the data bit width of single dram chip is n, dram chip number is N, so total to DRAM data bit width M is that the bit wide of n*N, NCM storage chip is also M; The second is the NCM chip that each dram chip has a data replacement, and as depicted in fig. 4b, bit wide and the single dram chip of each NCM chip are consistent.If adopt the first structure, benefit is that the chip on mixing internal memory mainboard is less, between DRAM and NCM, address maps conversion also more easily realizes, shortcoming is large to NCM capacity requirement, as long as because the data that a certain dram chip stores are positioned at tail end distributive province, just need to dump to together with the data (ensureing consistent data access bit wide) in other dram chip identical address in NCM chip.
Due to the randomness of DRAM storage unit retention time distribution, have more data conversion storage when the refresh cycle improves to NCM, thus cause the reduction mixing performance of memory system.If adopt the second structure, the NCM chip that each dram chip has independently data to replace, thus the data that each dram chip appears at tail end distributive province can dump to alone in respective NCM chip, can not influence each other between dram chip, therefore little to the storage capacity requirement of single NCM chip, but the NCM chip that shortcoming is each dram chip and correspondence thereof needs extra address maps conversion, realization is wanted complicated many, and the number of chips on mixing internal memory mainboard increases, add wiring, manufacturing cost can rise.Without loss of generality, dram chip is referred to as DRAM district, NCM chip is referred to as NCM district.
Such as, the memory capacity in DRAM district is the memory capacity in V_d, NCM district is V_n, so should have V_d much larger than V_n.The capacity of the whole mixing internal memory that system processor can be accessed is the memory capacity V_d in DRAM district, because the data of described NCM only on alternative DRAM tail end distribution memory cells address.Logic detection module should be had in mixing internal memory, determine the retention time boundary of tail end distributive province and main distributive province for periodic detection, judge to be arranged in DRAM tail end distributive province storage unit address information.When mixing DRAM is in non-busy state, the data be arranged on DRAM tail end distribution memory cells address are stored in the storage unit of NCM assigned address, then the refresh cycle of DRAM is improved, when the data being positioned on DRAM tail end distribution memory cells address described in system visits again next time, only read the data on assigned address in described NCM.
Fig. 5 a-5b is the hardware implementing structural drawing of the present embodiment mixing internal memory, the particular hardware of this mixing internal memory of the present embodiment realizes structure as shown in accompanying drawing 5a, wherein 1 is address search conversion table, 2 is control module, 3 is MUX module, have ignored the read-write control signal of access mixing internal memory in figure, but do not affect the elaboration particular hardware mixing internal memory described in the present embodiment being realized to structure.Described address search conversion table 1 have recorded NCM and stores the address mapping relation substituting DRAM and store, namely, when improve DRAM refresh cycle, the physical address comprising tail end distribution memory cells in DRAM is that should to dump to physical address in NCM be the storage unit in addr2 to the data in addr1.So, the physical address addr1 corresponding to DRAM just just defines group address mapping relations, as the address search conversion table in Fig. 5 b with the physical address addr2 corresponding to NCM.
When sometime, it is in the storage unit on addr2_n that the data conversion storage on DRAM physical address addr1_n has arrived NCM physical address, so scheduler should search conversion table, set up by the address mapping relation of addr1_n to addr2_n.Identical, if under DRAM is operated in busy state, in order to avoid the NCM that access reading speed is slow, can the data stored in NCM be written back in the storage unit in DRAM on assigned address, reduce the refresh cycle, so now also scheduler should search conversion table, delete corresponding address mapping relation.Described control module 2 comes from NCM or DRAM to control to mix the data output channel of internal memory: if the physical address addr1 of system request data is present in the address list corresponding to DRAM in address search conversion table 1, and so control module 2 sends a control signal to MUX 3 and selects to export from the data 2 in NCM; If the physical address addr1 of system request is not present in address search conversion table 1 correspond to the address list of DRAM, so control module 2 sends a control signal to MUX 3 and selects to export from the data 1 in DRAM.
Fig. 6 is that the present embodiment adopts TCAM or CAM to realize the structural representation of address search conversion table; The key mixing the particular hardware implementation method of internal memory described in the present embodiment is just how in address search conversion table, to realize DRAM address search fast, and the control signal that data output channel is selected must be ready before DRAM data reading.A kind of hardware circuit realizing searching and mate fast is exactly Content Addressable Memory (ContentAddressableMemory:CAM) circuit or triple CAM (TernaryCAM:TCAM).Realize the address search conversion table of the present embodiment with CAM or TCAM, specific implementation structure as shown in Figure 6.
Its inside at least comprises two storage arrays, one be DRAM physical address addr1 search array, another is the storage array of NCM physical address addr2, when needs realize DRAM address addr1 in address search conversion table, addr1 is inputed to and searches data register, then be converted into matched data line SL and SLb to mate, read induction amplifier judges whether to mate addr1 storage unit by the result reading matched line ML.Search array by CAM or TCAM and can complete the exact matching searching data within a hardware clock cycle, once coupling, the result reading induction amplifier is converted into the address of addr2 storage array again through decoding, thus is exported by the NCM address addr2 corresponding to addr1.The control signal that data output channel is selected can by the result (SML0 reading induction amplifier, SML1, SMLn) by or computing obtain, as long as the result namely reading induction amplifier has one for high level (coupling), so control signal is just high level, and the output of MUX is from the data 2 of NCM, otherwise the output of MUX is from the data 1 of DRAM.In sum, above-mentioned realizing circuit can realize DRAM address search fast, and DRAM address is to the conversion of NCM address.
The present embodiment can be the system for implementing hardware of mixing internal memory, and comprising N number of DRAM storer, according to the DRAM storage unit retention time, DRAM storer is divided into main distributive province and tail end distributive province, N is positive integer;
At least one NCM storer, is connected with DRAM storer, can substitute the data that the tail end distributive province stored in DRAM storer stores;
Address search modular converter, be connected with DRAM storer, NCM storer respectively, and prestore in address search modular converter and comprise tail end distributive province in DRAM storer and store address information in order to tail end distributive province data in alternative storage DRAM storer in the address information of data and NCM storer corresponding with it;
Control module, is connected with address search modular converter, and to obtain and to judge the source of the output channel of system data according to address information and address mapping relation, and control module generates according to the source of output channel and exports control signal;
MUX, is connected with control module, DRAM storer, NCM storer respectively, receives and selects data to export according to control signal.
In the present embodiment, address search modular converter can comprise address search conversion table, and DRAM memory block can comprise multiple DRAM storer, and in like manner NCM memory block also can comprise a multiple or NCM storer.
In the present invention's preferred embodiment, NCM storer is N number of, and each DRAM storer is all connected with a NCM storer.
In the present invention's preferred embodiment, hardware implementing comprises:
Logic detection module, is connected with DRAM storer, and periodic detection also determines the retention time boundary of DRAM storer tail end distributive province and main distributive province, judges to be arranged in the address information that DRAM storer tail end distributive province stores data simultaneously.
In the present invention's preferred embodiment, address search modular converter comprises:
DRAM address storage array, stores the address information that tail end distributive province replaced in DRAM storer stores data;
NCM address storage array, stores tail end distributive province in alternative DRAM storer and stores the address information of the NCM storer of data.
In the present invention's preferred embodiment, system also comprises:
Search data register, be connected with DRAM address storage array, and
When needs realize DRAM address search in address search modular converter, inputed to DRAM address and search data register, searching data register by DRAM address spaces is matched data line, mates one by one in storage array.
In the present invention's preferred embodiment, system also comprises:
Read induction amplifier, be connected with DRAM address storage array, control module respectively, and
Read induction amplifier and read matched data according to the result of coupling.
In the present invention's preferred embodiment, system also comprises: read induction amplifier and judge by the result reading matched line the DRAM address that whether there is coupling in the storage array of DRAM address.
In the present invention's preferred embodiment, system also comprises:
Code translator, is connected with reading induction amplifier, NCM address storage array, control module respectively, and
In time there is the DRAM address matched in the storage array of DRAM address, the data of code translator to coupling are carried out decoding and are converted into the address of NCM address storage array.
Embodiment two
Fig. 7 is a kind of schematic diagram mixing the Hardware Implementation embodiment two of internal memory of the present embodiment, a kind of Hardware Implementation mixing internal memory, and Hardware Implementation comprises:
Step S1: send request of data respectively to DRAM storer, address search modular converter;
Step S2: address search modular converter receives the physical address of request of data, and judges whether the physical address of request msg is present in the DRAM address list in address search modular converter; If so, then step S3 is performed, if not, then perform step S4.
Step S3: control module produces control signal and is sent to MUX, and MUX is selected to export in the data of NCM storer according to control signal, and is sent in NCM storer by NCM physical address corresponding for the DRAM address of coupling.
Step S4: the data read in DRAM storer export on data bus through MUX by control module.
In the present invention's preferred embodiment, Hardware Implementation also comprises:
Step S31: after step S3, NCM storer reads data according to NCM physical address, and exports the data of reading to data bus through MUX.
Fig. 8 is the browsing process schematic diagram of the present embodiment mixing internal memory, and as shown in Figure 8, its step mainly comprises as follows the particular hardware implementation method process flow diagram of the present embodiment mixing internal memory:
(1) system sends request of data to mixing internal memory, and the physical address of request of data is addr1, is sent to DRAM memory block on the one hand, is sent to address search conversion table on the one hand;
(2) judge whether address addr1 is present in the address list corresponding to DRAM in address search conversion table: if perform step 3, if not, perform step 4;
(3) control module controls signal to MUX and selects to export from the data of NCM, simultaneously, NCM physical address addr2 corresponding for DRAM physical address addr1 in address search conversion table to be sent in NCM memory block and to read data, finally the data 2 read in NCM being outputted on data bus through MUX.
(4) control module control MUX is selected to export from the data of DRAM, does not access NCM, finally the data 1 read in DRAM is outputted on data bus through MUX.
If read data finally come from DRAM, so compare traditional internal memory to read, the read latch of the present embodiment mixing internal memory only increases the time delay of data through MUX (3), compare the delay of sense data from DRAM array, the increase of the delay brought by MUX (3) can be ignored.If read data finally come from NCM, postpone to want much slow compared to DRAM although read, but the capacity of NCM will much smaller than DRAM, also very little on the impact of mixing internal memory performance, but the benefit brought greatly improves the refresh cycle, will greatly reduce by refreshing the power consumption caused, the raising of refresh cycle simultaneously also can make DRAM readwrite performance be improved.
In sum, the present invention proposes a kind of particular hardware implementation method mixing internal memory, stored the mapping relations of DRAM address and NCM address by address search conversion table, exported from DRAM or NCM by lookup result control data.The performance impact of this Hardware Implementation of the present invention to mixing internal memory is very little, but can obtain the lifting of the refresh cycle of DRAM array, reduces refresh power consumption.
By illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (10)
1. mix a system for implementing hardware for internal memory, it is characterized in that, described system for implementing hardware comprises:
N number of DRAM storer, is divided into main distributive province and tail end distributive province according to the DRAM storage unit retention time by described DRAM storer, and N is positive integer;
At least one NCM storer, is connected with described DRAM storer, can substitute the data that the tail end distributive province stored in described DRAM storer stores;
Address search modular converter, be connected with described DRAM storer, described NCM storer respectively, and prestore in described address search modular converter and comprise tail end distributive province in described DRAM storer and store address information in order to tail end distributive province data in the described DRAM storer of alternative storage in the address information of data and NCM storer corresponding with it;
Control module, be connected with described address search modular converter, to obtain and to judge the source of the output channel of described system data according to described address information and described address mapping relation, and described control module generates according to the source of described output channel and exports control signal;
MUX, is connected with described control module, described DRAM storer, described NCM storer respectively, receives and selects data to export according to described control signal.
2. the system for implementing hardware of mixing internal memory according to claim 1, is characterized in that, described NCM storer is N number of, and all described with one the NCM storer of DRAM storer described in each is connected.
3. the system for implementing hardware of mixing internal memory according to claim 1, is characterized in that, described hardware implementing comprises:
Logic detection module, be connected with described DRAM storer, periodic detection also determines the retention time boundary of described DRAM storer tail end distributive province and described main distributive province, judges to be positioned at the address information that tail end distributive province described in DRAM storer stores data simultaneously.
4. the system for implementing hardware of mixing internal memory according to claim 1, is characterized in that, described address search modular converter comprises:
DRAM address storage array, stores the address information that tail end distributive province replaced in described DRAM storer stores data;
NCM address storage array, stores tail end distributive province in alternative described DRAM storer and stores the address information of the NCM storer of data.
5. the system for implementing hardware of mixing internal memory according to claim 4, is characterized in that, described system also comprises:
Search data register, be connected with described DRAM address storage array, and
When needs realize DRAM address search in described address search modular converter, data register is searched described in being inputed to described DRAM address, described to search data register by described DRAM address spaces be matched data line, mates one by one in described storage array.
6. the system for implementing hardware of mixing internal memory according to claim 5, is characterized in that, described system also comprises:
Read induction amplifier, be connected with described DRAM address storage array, described control module respectively, and
Described reading induction amplifier reads matched data according to the result of coupling.
7. the system for implementing hardware of mixing internal memory according to claim 6, it is characterized in that, described system also comprises: described reading induction amplifier judges by the result reading matched line the described DRAM address that whether there is coupling in the storage array of described DRAM address.
8. the system for implementing hardware of mixing internal memory according to claim 6, is characterized in that, described system also comprises:
Code translator, is connected with described reading induction amplifier, described NCM address storage array, described control module respectively, and
In time there is the described DRAM address matched in the storage array of described DRAM address, code translator carries out decoding to the data of described coupling and is converted into the address of described NCM address storage array.
9. mix a Hardware Implementation for internal memory, it is characterized in that, described Hardware Implementation comprises:
Step S1: send request of data respectively to DRAM storer, address search modular converter;
Step S2: described address search modular converter receives the physical address of described request of data, and judge whether the physical address of described request data is present in the DRAM address list in described address search modular converter; If so, then step S3 is performed, if not, then perform step S4.
Step S3: control module produces control signal and is sent to MUX, and MUX is selected to export in the data of NCM storer according to described control signal, and is sent in NCM storer by NCM physical address corresponding for the DRAM address of coupling.
Step S4: the data read in described DRAM storer export on data bus through described MUX by control module.
10. the Hardware Implementation of mixing internal memory according to claim 9, is characterized in that, described Hardware Implementation also comprises:
Step S31: after step S3, described NCM storer reads data according to described NCM physical address, and exports the data of reading to data bus through MUX.
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| CN105938458B (en) * | 2016-04-13 | 2019-02-22 | 上海交通大学 | The isomery mixing EMS memory management process of software definition |
| CN106168928A (en) * | 2016-07-06 | 2016-11-30 | 上海新储集成电路有限公司 | A kind of solution mixes the probabilistic method of internal memory read latency |
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