CN105824767A - Circuit and method for controlling cutting positions and controller - Google Patents
Circuit and method for controlling cutting positions and controller Download PDFInfo
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Abstract
The invention provides a circuit and a method for controlling cutting positions and a controller. The circuit comprises a logic signal output unit and a logic signal control unit, wherein the logic signal output unit is connected with a DRAM (dynamic random access memory); the logic signal control unit is connected with the logic signal output unit, and is used for receiving multiple inputted logic signals and a cutting position control signal matched with a DRAM model, selecting a logic signal matched with the cutting position control signal from the inputted logic signals according to the cutting position control signal, and sending the matched logic signal to the logic signal output unit; the logic signal output unit is used for outputting the matched logic signal to the DRAM. The circuit has the advantages that the application of different models of DRAM is realized; the function of resistance gating signals is replaced by the selecting function of the logic signal control unit, so that complicated wiring is not needed, the defect of difficulty in wiring of the traditional cutting position control circuit can be effectively overcome; the area of an integrated circuit board is saved, and the design cost is reduced.
Description
Technical field
The present invention relates to electronic chip technology field, particularly relate to one and cut a control circuit and method and controller.
Background technology
Along with being growing more intense of computer flat panel and the TV box market competition, the cost control of design also becomes more acute.Internal memory is one of most important ingredient of whole embedded system, PCBA (PrintedCircuitBoardAssembly scheme business, printed circuit board (PCB)) in, DRAM (DynamicRandomAccessMemory, dynamic random access memory) is one of mostly important parts the most expensive in whole PCBA.
nullBut limitation and the complicated variety of semiconductor storage due to production technology，Produce the DRAM produced on line and some defective products the most inevitably occur，A certain partial address regional anomaly can be there is in part DRAM，But the situation that remainder memory area can normally use，Such as J、K、P、Q、The model DRAM granules such as L are exactly a kind of form of problem print，Wherein，The J of DRAM、K、P、Q、L-type number be according to each address pin of DRAM input unlike signal and specify，As，The A14 address pin of J-type DRAM must fixing input 0，The A14 address pin of K-type DRAM must fixing input 1，The A13 address pin of p-type DRAM must fixing input 0，A14 address pin must input A13 logical signal，The A13 address pin of Q type DRAM must fixing input 1，A14 address pin must input A13 logical signal，A13 address pin and the A14 address pin of L-type DRAM must input A13 logical signal.The partial address pin of these DRAM above-mentioned need to be newly defined as new address signal, these DRAM become and cut a DRAM, cut price is normal DRAM price about the 2/3 of a DRAM, can apply suitably if these cut a DRAM, just can be substantially reduced the design cost of scheme business.
What a DRAM was cut in traditional support cuts a control circuit as depicted in figs. 1 and 2, it supports the DRAM of different model by the resistance in gating circuit, thus need the position of reserved resistance in the printed circuit board (PCB) the highest with regard to integrated level, add the wiring difficulty of printed circuit board (PCB).
Summary of the invention
In consideration of it, be necessary to cut, for traditional, the problem that a control circuit adds printed circuit board wiring difficulty, it is provided that one cuts a control circuit and method and controller.
For reaching goal of the invention, it is provided that one cuts a control circuit, described circuit includes:
Logical signal output unit, for being connected with DRAM；
Logical signal control unit, it is connected with described logical signal output unit, for receiving the multiple logical signal of input and cutting a control signal with described DRAM type number matches, and select to cut, with described, the logical signal that a control signal matches from the multiple described logical signal of input according to a described control signal of cutting, and the described logical signal matched is sent to described logical signal output unit；
Described logical signal output unit, the logical signal being additionally operable to match described in output is to described DRAM.
Wherein in an embodiment, described logical signal output unit include the first logical signal output unit to N logical signal output unit, wherein N >=2；
Described first logical signal output unit connects to described N logical signal output unit for address pin corresponding with described DRAM respectively；
Described logical signal control unit is connected to described N logical signal output unit with described first logical signal output unit respectively, receives the multiple logical signal inputted for obtaining and described cuts a control signal；
Described logical signal control unit is additionally operable to described in basis cut a control signal and selects to cut, with described, the logical signal that a control signal matches from the multiple logical signal of input, and the described logical signal matched is sent to the appropriate address pin of described DRAM by corresponding logical signal output unit.
Wherein in an embodiment, the multiple logical signal that described logical signal control unit receives includes all logical signals needed for DRAM.
Wherein in an embodiment, described logical signal control unit include the first logical signal control unit to N logical signal control unit, wherein N >=2；
Described first logical signal control unit is connected with described first logical signal output unit, a control signal is cut for receiving the first of the appropriate address pin of the described DRAM being connected with described first logical signal output unit, and according to described first cut a control signal from input multiple logical signal select cut, with described first, the logical signal that a control signal matches, and the described logical signal matched is sent to described first logical signal output unit, the logical signal matched described in described first logical signal output unit output to described DRAM；
Described N logical signal control unit is connected with described N logical signal output unit, a control signal is cut for receiving the N of the appropriate address pin of the described DRAM being connected with described N logical signal output unit, and according to described N cut a control signal from input multiple logical signal select cut, with described N, the logical signal that a control signal matches, and the described logical signal matched is sent to described N logical signal output unit, the logical signal matched described in the output of described N logical signal output unit to described DRAM.
Wherein in an embodiment, the quantity of the described logical signal that described first logical signal control unit to described N logical signal control unit receives increases successively.
The present invention also provides for one and cuts a control method, and described method includes:
What the reception of logical signal control unit and DRAM type number matched cuts a control signal, and described logical signal output unit is connected with described logical signal control unit；
Described logical signal control unit receives the multiple logical signal of input；
Described logical signal control unit according to described in cut a control signal and select to cut, with described, the logical signal that a control signal matches from the multiple logical signal of input, and the described logical signal matched is sent to described logical signal output unit；
The described logical signal matched is exported to described DRAM by described logical signal output unit.
Wherein in an embodiment, also include:
The first of first address pin of the described logical signal control unit described DRAM of acquisition cuts a control signal, first address pin of described DRAM is connected with the first logical signal output unit, and described first logical signal output unit is connected with described logical signal control unit；
Described logical signal control unit receives the multiple logical signal of input；
Described logical signal control unit is cut a control signal according to described first and is selected to cut, with described first, the logical signal that a control signal matches from the multiple described logical signal of input, and the described logical signal matched is sent to described first logical signal output unit；
The described logical signal matched is exported to described first address pin of described DRAM by described first logical signal output unit；
The N of the N address pin that described logical signal control unit obtains described DRAM cuts a control signal, and the N address pin of described DRAM is connected with N logical signal output unit, and described N logical signal output unit is connected with described logical signal control unit；
Described logical signal control unit receives the multiple logical signal of input；
Described logical signal control unit is cut a control signal according to described N and is selected to cut, with described N, the logical signal that a control signal matches from the multiple described logical signal of input, and the described logical signal matched is sent to described N logical signal output unit；
The described logical signal matched is exported to the described N address pin of described DRAM, wherein, N >=2 by described N logical signal output unit.
Wherein in an embodiment, the multiple logical signal that described logical signal control unit receives includes all logical signals needed for DRAM.
Wherein in an embodiment, also include:
The first of first address pin of the first logical signal control unit described DRAM of acquisition cuts a control signal, first address pin of described DRAM is connected with the first logical signal output unit, and described first logical signal output unit is connected with described first logical signal control unit；
Described first logical signal control unit receives the multiple logical signal of input；
Described first logical signal control unit is cut a control signal according to described first and is selected to cut, with described first, the logical signal that a control signal matches from the multiple logical signal of input, and the described logical signal matched is sent to described first logical signal output unit；
The described logical signal matched is exported to described first address pin of described DRAM by described first logical signal output unit；
The N of the address pin that N logical signal control unit obtains the N address pin of described DRAM cuts a control signal, the N address pin of described DRAM is connected with N logical signal output unit, and described N logical signal output unit is connected with described N logical signal control unit；
Described N logical signal control unit receives the multiple logical signal of input；
Described N logical signal control unit is cut a control signal according to described N and is selected to cut, with described N, the logical signal that a control signal matches from the multiple logical signal of input, and the described logical signal matched is sent to described N logical signal output unit；
The described logical signal matched is exported to the described N address pin of described DRAM, wherein, N >=2 by described N logical signal output unit.
Wherein in an embodiment, the quantity of the described logical signal that described first logical signal control unit to described N logical signal control unit receives increases successively.
The present invention also provides for a kind of controller, including main control chip, also includes:
Logical signal output unit, for being connected with DRAM；
Logical signal control unit, it is connected with described main control chip and described logical signal output unit respectively, for receiving multiple logical signal that described main control chip provides and cutting a control signal with described DRAM type number matches, and select to cut, with described, the logical signal that a control signal number matches from the multiple described logical signal of input according to a described control signal of cutting, and the described logical signal matched is sent to described logical signal output unit；
Described logical signal output unit, the logical signal being additionally operable to match described in output is to described DRAM.
The beneficial effect comprise that
Above-mentioned cut a control circuit and method and controller, logical signal control unit selects from the multiple logical signal of input according to cutting a control signal and cuts the logical signal that a control signal matches, and the logical signal matched is exported to DRAM by logical signal output unit, thus realize the application of different model DRAM, and it utilizes the selection function of logical signal control unit to instead of the function of resistance gating signal, without complicated wiring, therefore, effectively overcome tradition and cut a defect for control circuit difficult wiring, simultaneously, also reduce the area of surface-mounted integrated circuit, reduce design cost.
Accompanying drawing explanation
Fig. 1 is traditional connection diagram cutting a control circuit, controller and DRAM；
Fig. 2 is traditional structural representation cutting a control circuit；
Fig. 3 is the structural representation cutting a control circuit in an embodiment；
Fig. 4 is the structural representation cutting a control circuit in another embodiment；
Fig. 5 is the schematic flow sheet cutting a control method in an embodiment；
Fig. 6 is the structural representation of the controller in an embodiment.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples the present invention cut a control circuit and method and controller is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
In one embodiment, as shown in Figure 3, it is provided that one cuts a control circuit, this circuit includes:
Logical signal output unit 100, for being connected with DRAM.Logical signal control unit 200, it is connected with logical signal output unit 100, for receiving the multiple logical signal of input and cutting a control signal with DRAM type number matches, and select from the multiple logical signal of input according to cutting a control signal and cut the logical signal that a control signal matches, and the logical signal matched is sent to logical signal output unit 100.Logical signal output unit 100, is additionally operable to export the logical signal matched to DRAM.
nullIn the present embodiment，The multiple logical signal of offer that the main control chip of controller is logical signal control unit 200 and cut a control signal，Wherein，Main control chip can cut a control signal according to the difference output cutting a DRAM connected is different，Owing to the input signal of every kind of address pin corresponding for DRAM is fixing，So logical signal control unit 200 just can cut, according to what its input inputted, the logical signal that a control signal selects the input signal with DRAM address pin to match from the multiple logical signal of input，And by logical signal output unit 100, the logical signal matched is exported to DRAM，So that the function of DRAM can completely be suitable for，Performance can be substantially unaffected，So can effectively support to cut a DRAM，It is made to complete corresponding function，About the 2/3 of normal DRAM price is only had owing to cutting the price of a DRAM，Therefore, it is possible to be substantially reduced cost.Wherein, the model of DRAM includes conventional DRAM, J-type DRAM, K-type DRAM, p-type DRAM, Q type DRAM and L-type DRAM.Cut a control signal to be generated according to the DRAM type number being connected with logical signal output unit by main control chip, and export to logical signal control unit 200.
Traditional employing as shown in Figure 2 cut a control circuit when supporting to cut DRAM, need reserved 6 resistance position in integrated printed circuit board (PCB), give the wiring difficulty that the printed circuit board (PCB) that natively cabling is the most intensive increases, and the control circuit of cutting in the present embodiment utilizes the selection function of logical signal control unit 200 to instead of the function of resistance gating signal, without complicated wiring, only need to simply connect, therefore can effectively overcome tradition to cut a defect for control circuit difficult wiring.Meanwhile, because without to components and parts reserved location, and logical signal control unit 200 can be components and parts the least, as: MUX (Multiplexers, MUX), it is possible to the effective area reducing printed circuit board (PCB), utilize product to tend to sophistication.And, a traditional control circuit of cutting is when supporting to cut DRAM, it is required for 2 extra resistance and carrys out gating signal, so every printed circuit board is required for increasing corresponding Material Cost, if when producing in enormous quantities, also will expend a considerable expense, and the present embodiment cuts a control circuit when supporting to cut DRAM, select logical signal by logical signal control unit, therefore carry out gating signal without resistance, greatly reduce the waste of Material Cost.
In one embodiment, logical signal output unit 100 include the first logical signal output unit to N logical signal output unit, wherein N >=2.First logical signal output unit connects to N logical signal output unit for address pin corresponding with described DRAM respectively.Logical signal control unit 200 is connected to N logical signal output unit with the first logical signal output unit respectively, for receiving the multiple logical signal of input and cutting a control signal.Logical signal control unit 200 is additionally operable to according to cutting a control signal multiple logical signal selection from input and cutting the logical signal that a control signal matches, and the logical signal matched is sent to the appropriate address pin of DRAM by corresponding logical signal output unit.
Cutting a control circuit and the DRAM of "abnormal" can only be had effective for A13 address pin as shown in Figure 2, if being changed to other a DRAM that cuts, then needs again to make printed circuit board (PCB), spends high time and efforts.In order to meet the DRAM of different model, multiple logical signal output unit is set, a kind of address pin of each logical signal output unit correspondence DRAM, thus can be suitable for different address pin and have the DRAM of "abnormal", perfect can be suitable for the DRAM of various model, substantially increase practicality and the compatibility cutting a control circuit.And on the basis of existing DRAM type number, also it being prefixed the address pin being the most likely suitable for, extensibility is strong, further increases practicality and the compatibility cutting a control circuit.
Preferably, in one embodiment, the multiple logical signal that logical signal control unit 200 receives includes all logical signals needed for DRAM.
So logical signal control unit just can provide various required logical signal for multiple logical signal output units, it is to avoid because the defect not supporting certain model DRAM that the disappearance of certain logical signal is brought.Required all logical signals obtain according to the model of the most existing DRAM.
Wherein, logical signal includes logic zero signal, logic 1 signal, A13 logical signal, A14 logical signal and A15 logical signal.
In one embodiment, described logical signal control unit include the first logical signal control unit to N logical signal control unit, wherein N >=2.First logical signal control unit is connected with the first logical signal output unit, a control signal is cut for receiving the first of the appropriate address pin of the DRAM being connected with the first logical signal output unit, and according to first cut a control signal from input multiple logical signal select cut, with first, the logical signal that a control signal matches, and the logical signal matched is sent to the first logical signal output unit, the logical signal that the first logical signal output unit output matches to described DRAM.N logical signal control unit is connected with N logical signal output unit, a control signal is cut for receiving the N of the DRAM appropriate address pin being connected with N logical signal output unit, and according to N cut a control signal from input multiple logical signal select cut, with N, the logical signal that a control signal matches, and the logical signal matched is sent to described N logical signal output unit, the logical signal matched described in the output of N logical signal output unit to described DRAM.
Switch is selected to be connected the circuit confusion brought and problem that circuit easily breaks down in order to avoid logical signal control unit and all of logical signal output unit, logical signal control unit is set also for multiple, and with multiple logical signal output unit one_to_one corresponding, the most each logical signal output unit and a logical signal control unit connect, so can realize supporting the function of various model DRAM, moreover it is possible to avoid the problem that circuit is chaotic and fault easily occurs.Wherein, the logical signal of each logical signal control unit input can include all signals needed for DRAM.
Preferably, in one embodiment, the quantity of the described logical signal that the first logical signal control unit receives to described N logical signal control unit increases successively.
From the characteristic cutting a DRAM in the market, address pin occurs that the situation of "abnormal" is usually address pin and fixes input logic 0 signal, logic 1 signal, or what current address pin inputted is the logical signal of a upper address pin, and the DRAM of routine the most only need to input normal logical signal.Therefore, first logical signal control unit only needs input logic 0 signal, logic 1 signal and normal first logical signal, second logical signal control unit only needs input logic 0 signal, logic 1 signal, the first logical signal and the second logical signal ... N logical signal control unit output logic zero signal, logic 1 signal, the first logical signal, the second logical signal ..., N logical signal, so, the DRAM of various models present on market can be met, minimizing logic circuit that again can be relative, reduces design complexities and the cost of surface-mounted integrated circuit.
It is described in detail below in conjunction with the embodiment shown in Fig. 4: in the embodiment shown in fig. 4, cuts a control circuit and include the first logical signal control unit, the second logical signal control unit and the 3rd logical signal control unit.The first logical signal output unit that wherein the first logical signal control unit outfan connects is A13 logical signal output unit, and the logical signal of the first logical signal control unit input includes logic zero signal, logic 1 signal and A13 logical signal；The second logical signal output unit that second logical signal control unit outfan connects is A14 logical signal output unit, and the logical signal of the second logical signal control unit input includes logic zero signal, logic 1 signal, A13 logical signal and A14 logical signal；It is A15 logical signal output unit that 3rd logical signal control unit outfan connects the 3rd logical signal output unit, and the logical signal of the 3rd logical signal control unit input includes logic zero signal, logic 1 signal, A13 logical signal, A14 logical signal and A15 logical signal.Wherein, A13 logical signal output unit is for being connected with the A13 address pin of DRAM, and A14 logical signal output unit is for being connected with the A14 address pin of DRAM, and A15 logical signal output unit is for being connected with the A15 address pin of DRAM.When cutting a control circuit and supporting different DRAM, when being J-type DRAM such as DRAM, first logical signal control unit selects A13 logical signal, and A13 logical signal is exported to the A13 address pin of DRAM, second logical signal control unit selects logic zero signal, and logic zero signal is exported to the A14 address pin of DRAM, owing to J-type DRAM does not has A15 address pin, therefore the 3rd logical signal control unit is without selecting, the most just the function of J-type DRAM can be made to be able to complete being suitable for, use J-type DRAM on the basis of reducing system cost, meet the performance requirement of system.Or, when being p-type DRAM such as DRAM, first logical signal control unit selects logic zero signal, and logic zero signal is exported to the A13 address pin of DRAM, second logical signal control unit selects A13 logical signal, and A13 logical signal is exported to the A14 address pin of DRAM, owing to p-type DRAM does not has A15 address pin, therefore the 3rd logical signal control unit is without selecting, the most just the function of p-type DRAM can be made to be able to complete being suitable for, use p-type DRAM on the basis of reducing system cost, meet the performance requirement of system.Being similar to, the control circuit of cutting in the present embodiment is also applied for K-type DRAM, Q type DRAM and L-type DRAM, and here is omitted.Three the exportable logical signals of logical signal output unit cutting a control circuit in this embodiment are as shown in table 1, and the logical signal that three logical signal control units are selected according to the different model of DRAM is as shown in table 2.
Table 1
Table 2
| DRAM type | A13_out | A14_out | A15_out |
| Conventional | A13 | A14 | A15 |
| J | A13 | logic 0 | / |
| K | A13 | logic 1 | / |
| P | logic 0 | A13 | / |
| Q | logic 1 | A13 | / |
| L | A13 | A13 | / |
Can be seen that from above-described embodiment, cutting a control circuit and can support the DRAM of different model in the present embodiment, and select or different printed circuit board (PCB) of remaking without the DRAM according to different model, reduce design cost, improve the suitability and the compatibility of circuit.When cutting the DRAM that a control circuit supports different model, only the address pin of DRAM need to be connected on corresponding logical signal output unit, logical signal control unit just can select matched logical signal according to the model of DRAM voluntarily, gating signal without unnecessary components and parts (such as resistance), reduce Material Cost to a certain extent, wiring is simple, the area occupied that can make circuit is less, so that surface-mounted integrated circuit more they tends to smart littleization, meet the existing market requirement to electronic product sophistication.
In one embodiment, as it is shown in figure 5, additionally provide one to cut a control method, the method includes:
S100, what the reception of logical signal control unit and DRAM type number matched cuts a control signal, and DRAM is connected with logical signal output unit, and logical signal output unit is connected with described logical signal control unit.
S200, logical signal control unit receives the multiple logical signal of input.
S300, logical signal control unit selects from the multiple logical signal of input according to cutting a control signal and cuts the logical signal that a control signal matches, and the logical signal matched is sent to logical signal output unit.
S400, the logical signal matched is exported to DRAM by logical signal output unit.
The present embodiment cuts a control method, logical signal control unit receives the multiple logical signal of input and cuts a control signal, owing to the input signal that the address pin of the DRAM of every kind of model is corresponding is fixing, therefore main control chip just can export according to the model of DRAM and suitably cut a control signal, logical signal control unit selects from the multiple logical signal of input and cuts the logical signal that a control signal matches, and the logical signal matched is exported to DRAM by logical signal output unit, thus realize the application of different model DRAM, and it utilizes the selection function of logical signal control unit to instead of the function of resistance gating signal, without complicated wiring, only need to simply connect, therefore tradition can be effectively overcome to cut a defect for control circuit difficult wiring.Meanwhile, because without to components and parts reserved location, and logical signal control unit can be components and parts the least, so also reducing the area of surface-mounted integrated circuit, utilizes product to tend to sophistication.And it is without components and parts such as extra resistance, reduces design cost.
In one embodiment, also include:
S100a, the first of first address pin of the first logical signal control unit reception DRAM cuts a control signal, and first address pin of DRAM is connected with the first logical signal output unit, and the first logical signal output unit is connected with logical signal control unit.
S200a, logical signal control unit receives the multiple logical signal of input.
S300a, logical signal control unit is cut a control signal according to described first and is selected to cut, with described first, the logical signal that a control signal matches from the multiple described logical signal of input, and the described logical signal matched is sent to described first logical signal output unit.
S400a, the described logical signal matched is exported to described first address pin of described DRAM by the first logical signal output unit.
S100b, the N of the N address pin that logical signal control unit obtains DRAM cut a control signal, and the N address pin of DRAM is connected with N logical signal output unit, and N logical signal output unit is connected with logical signal control unit.
S200b, logical signal control unit receives the multiple logical signal of input.
S300b, logical signal control unit is cut a control signal according to described N and is selected to cut, with N, the logical signal that a control signal matches from the multiple logical signal of input, and the logical signal matched is sent to N logical signal output unit.
The logical signal matched is exported to the N address pin of DRAM by S400b, N logical signal output unit, wherein, and N >=2.
In one embodiment, the multiple logical signal that described logical signal control unit receives includes all logical signals needed for DRAM.
In one embodiment, also include:
S110a, the first of first address pin of the first logical signal control unit acquisition DRAM cuts a control signal, and first address pin of DRAM is connected with the first logical signal output unit, and the first logical signal output unit and the first logical signal control unit connect.
S210a, the first logical signal control unit receives the multiple logical signal of input.
S310a, first logical signal control unit is cut a control signal according to described first and is selected to cut, with described first, the logical signal that a control signal matches from the multiple logical signal of input, and the described logical signal matched is sent to described first logical signal output unit.
S410a, the described logical signal matched is exported to described first address pin of described DRAM by the first logical signal output unit.
S110b, the N of the address pin that N logical signal control unit obtains the N address pin of described DRAM cuts a control signal, the N address pin of DRAM is connected with N logical signal output unit, and N logical signal output unit is connected with described N logical signal control unit.
S210b, N logical signal control unit receives the multiple logical signal of input.
S310b, N logical signal control unit is cut a control signal according to described N and is selected to cut, with described N, the logical signal that a control signal matches from the multiple logical signal of input, and the described logical signal matched is sent to described N logical signal output unit.
The logical signal matched is exported to the N address pin of DRAM by S410b, N logical signal output unit, wherein, and N >=2.
In one embodiment, the quantity of the described logical signal that described first logical signal control unit receives to described N logical signal control unit increases successively.
Owing to the method solves the principle of problem, cut a control circuit to aforementioned one similar, and therefore the enforcement of the method may refer to the enforcement of aforementioned circuit, repeats no more in place of repetition.
One of ordinary skill in the art will appreciate that all or part of flow process realizing in above-described embodiment method, can be by computer program and complete to instruct relevant hardware, described program can be stored in a computer read/write memory medium, this program is upon execution, it may include such as the flow process of the embodiment of above-mentioned each method.Wherein, described storage medium can be magnetic disc, CD, read-only store-memory body (Read-OnlyMemory, ROM) or random store-memory body (RandomAccessMemory, RAM) etc..
In one embodiment, as shown in Figure 6, also provide for a kind of controller, including main control chip, also include: logical signal output unit 100, for being connected with DRAM.Logical signal control unit 200, it is connected with main control chip and logical signal output unit respectively, for receiving multiple logical signal that main control chip provides and cutting a control signal with DRAM type number matches, and select from the multiple logical signal of input according to cutting a control signal and cut the logical signal that a control signal matches, and the described logical signal matched is sent to logical signal output unit.Logical signal output unit 100, is additionally operable to export the logical signal matched to DRAM.
Controller in the present embodiment has cuts the technique effect that a control circuit has, in addition, a traditional control circuit of cutting is arranged on the outside of controller, the logical signal of logical signal output unit 100 output begins to bifurcated in distance DRAM place farther out, change due to bifurcation impedance, inevitably cause the reflection that signal transmits, thus disturb the quality of the DRAM termination collection of letters number, have a strong impact on the performance of controller, and the control circuit of cutting in the present embodiment is integrated in controller, controller is directly attached with DRAM, apart from close, therefore reflection during signal transmission can be effectively reduced, promote the quality of the DRAM termination collection of letters number, thus the overall performance of controller of deducting a percentage.
Each technical characteristic of embodiment described above can combine arbitrarily, for making description succinct, the all possible combination of each technical characteristic in above-described embodiment is not all described, but, as long as the combination of these technical characteristics does not exist contradiction, all it is considered to be the scope that this specification is recorded.
Embodiment described above only have expressed the several embodiments of the present invention, and it describes more concrete and detailed, but can not therefore be construed as limiting the scope of the patent.It should be pointed out that, for the person of ordinary skill of the art, without departing from the inventive concept of the premise, it is also possible to make some deformation and improvement, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (11)
1. cut a control circuit for one kind, it is characterised in that described circuit includes:
Logical signal output unit, for being connected with DRAM；
Described logical signal control unit, it is connected with described logical signal output unit, for receiving the multiple logical signal of input and cutting a control signal with described DRAM type number matches, and select to cut, with described, the logical signal that a control signal matches from the multiple described logical signal of input according to a described control signal of cutting, and the described logical signal matched is sent to described logical signal output unit；
Described logical signal output unit, the logical signal being additionally operable to match described in output is to described DRAM.
The most according to claim 1 cut a control circuit, it is characterised in that described logical signal output unit include the first logical signal output unit to N logical signal output unit, wherein N >=2；
Described first logical signal output unit connects to described N logical signal output unit for address pin corresponding with described DRAM respectively；
Described logical signal control unit is connected to described N logical signal output unit with described first logical signal output unit respectively, is used for receiving the multiple logical signal of input and described cuts a control signal；
Described logical signal control unit is additionally operable to described in basis cut a control signal and selects to cut, with described, the logical signal that a control signal matches from the multiple logical signal of input, and the described logical signal matched is sent to the appropriate address pin of described DRAM by corresponding logical signal output unit.
The most according to claim 2 cut a control circuit, it is characterised in that the multiple logical signal that described logical signal control unit receives includes all logical signals needed for DRAM.
The most according to claim 2 cut a control circuit, it is characterised in that described logical signal control unit include the first logical signal control unit to N logical signal control unit, wherein N >=2；
Described first logical signal control unit is connected with described first logical signal output unit, a control signal is cut for receiving the first of the appropriate address pin of the described DRAM being connected with described first logical signal output unit, and according to described first cut a control signal from input multiple logical signal select cut, with described first, the logical signal that a control signal matches, and the described logical signal matched is sent to described first logical signal output unit, the logical signal matched described in described first logical signal output unit output to described DRAM；
Described N logical signal control unit is connected with described N logical signal output unit, a control signal is cut for receiving the N of the appropriate address pin of the described DRAM being connected with described N logical signal output unit, and according to described N cut a control signal from input multiple logical signal select cut, with described N, the logical signal that a control signal matches, and the described logical signal matched is sent to described N logical signal output unit, the logical signal matched described in the output of described N logical signal output unit to described DRAM.
The most according to claim 4 cut a control circuit, it is characterised in that the quantity of the described logical signal that described first logical signal control unit to described N logical signal control unit receives increases successively.
6. cut a control method for one kind, it is characterised in that described method includes:
What the reception of logical signal control unit and DRAM type number matched cuts a control signal, and described DRAM is connected with logical signal output unit, and described logical signal output unit is connected with described logical signal control unit；
Described logical signal control unit receives the multiple logical signal of input；
Described logical signal control unit according to described in cut a control signal and select to cut, with described, the logical signal that a control signal matches from the multiple logical signal of input, and the described logical signal matched is sent to described logical signal output unit；
The described logical signal matched is exported to described DRAM by described logical signal output unit.
The most according to claim 6 cut a control method, it is characterised in that also include:
The first of first address pin of the described logical signal control unit described DRAM of acquisition cuts a control signal, first address pin of described DRAM is connected with the first logical signal output unit, and described first logical signal output unit is connected with described logical signal control unit；
Described logical signal control unit receives the multiple logical signal of input；
Described logical signal control unit is cut a control signal according to described first and is selected to cut, with described first, the logical signal that a control signal matches from the multiple described logical signal of input, and the described logical signal matched is sent to described first logical signal output unit；
The described logical signal matched is exported to described first address pin of described DRAM by described first logical signal output unit；
The N of the N address pin that described logical signal control unit obtains described DRAM cuts a control signal, and the N address pin of described DRAM is connected with N logical signal output unit, and described N logical signal output unit is connected with described logical signal control unit；
Described logical signal control unit receives the multiple logical signal of input；
Described logical signal control unit is cut a control signal according to described N and is selected to cut, with described N, the logical signal that a control signal matches from the multiple described logical signal of input, and the described logical signal matched is sent to described N logical signal output unit；
The described logical signal matched is exported to the described N address pin of described DRAM, wherein, N >=2 by described N logical signal output unit.
The most according to claim 7 cut a control method, it is characterised in that the multiple logical signal that described logical signal control unit receives includes all logical signals needed for DRAM.
The most according to claim 7 cut a control method, it is characterised in that also include:
The first of first address pin of the first logical signal control unit described DRAM of acquisition cuts a control signal, first address pin of described DRAM is connected with the first logical signal output unit, and described first logical signal output unit is connected with described first logical signal control unit；
Described first logical signal control unit receives the multiple logical signal of input；
Described first logical signal control unit is cut a control signal according to described first and is selected to cut, with described first, the logical signal that a control signal matches from the multiple logical signal of input, and the described logical signal matched is sent to described first logical signal output unit；
The described logical signal matched is exported to described first address pin of described DRAM by described first logical signal output unit；
The N of the address pin that N logical signal control unit obtains the N address pin of described DRAM cuts a control signal, the N address pin of described DRAM is connected with N logical signal output unit, and described N logical signal output unit is connected with described N logical signal control unit；
Described N logical signal control unit receives the multiple logical signal of input；
Described N logical signal control unit is cut a control signal according to described N and is selected to cut, with described N, the logical signal that a control signal matches from the multiple logical signal of input, and the described logical signal matched is sent to described N logical signal output unit；
The described logical signal matched is exported to the described N address pin of described DRAM, wherein, N >=2 by described N logical signal output unit.
The most according to claim 9 cut a control method, it is characterised in that the quantity of the described logical signal that described first logical signal control unit to described N logical signal control unit receives increases successively.
11. 1 kinds of controllers, including main control chip, it is characterised in that also include:
Logical signal output unit, for being connected with DRAM；
Logical signal control unit, it is connected with described main control chip and described logical signal output unit respectively, for receiving multiple logical signal that described main control chip provides and cutting a control signal with described DRAM type number matches, and select to cut, with described, the logical signal that a control signal matches from the multiple described logical signal of input according to a described control signal of cutting, and the described logical signal matched is sent to described logical signal output unit；
Described logical signal output unit, the logical signal being additionally operable to match described in output is to described DRAM.
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| CN101262405A (en) * | 2008-04-11 | 2008-09-10 | 华南理工大学 | High-speed secure virtual private network channel based on network processor and its realization method |
| CN101477831A (en) * | 2009-01-22 | 2009-07-08 | 上海广电（集团）有限公司中央研究院 | DRAM controller based on FPGA device |
| CN105373348A (en) * | 2015-10-23 | 2016-03-02 | 上海新储集成电路有限公司 | Hardware implementation system and method for hybrid memory |
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| CN101262405A (en) * | 2008-04-11 | 2008-09-10 | 华南理工大学 | High-speed secure virtual private network channel based on network processor and its realization method |
| CN101477831A (en) * | 2009-01-22 | 2009-07-08 | 上海广电（集团）有限公司中央研究院 | DRAM controller based on FPGA device |
| CN105373348A (en) * | 2015-10-23 | 2016-03-02 | 上海新储集成电路有限公司 | Hardware implementation system and method for hybrid memory |
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