WO2014062543A2 - Memory rank and odt configuration in a memory system - Google Patents

Memory rank and odt configuration in a memory system Download PDF

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Publication number
WO2014062543A2
WO2014062543A2 PCT/US2013/064781 US2013064781W WO2014062543A2 WO 2014062543 A2 WO2014062543 A2 WO 2014062543A2 US 2013064781 W US2013064781 W US 2013064781W WO 2014062543 A2 WO2014062543 A2 WO 2014062543A2
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WO
WIPO (PCT)
Prior art keywords
memory
package
odt
ranks
memory package
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Application number
PCT/US2013/064781
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French (fr)
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WO2014062543A3 (en
Inventor
Minghui HAN
Amir Amirkhany
Ravindranath Kollipara
Ralf Michael SCHMITT
Original Assignee
Rambus Inc.
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Application filed by Rambus Inc. filed Critical Rambus Inc.
Priority to US14/408,955 priority Critical patent/US9747230B2/en
Publication of WO2014062543A2 publication Critical patent/WO2014062543A2/en
Publication of WO2014062543A3 publication Critical patent/WO2014062543A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0635—Configuration or reconfiguration of storage systems by changing the path, e.g. traffic rerouting, path reconfiguration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Definitions

  • Memory systems can include a number of memory modules that are connected to a common transmission channel.
  • the number of memory modules has an impact on the signal integrity of the transmission channel due to factors such as the loading on the transmission channel and increased signal reflections, which in turn limits the data rate of the transmission channel.
  • a memory system with two dual-rank modules connected to the same transmission channel may be able to reach a data rate of 1000 Mbps, whereas a memory system with three dual-rank modules connected to the same transmission channel may be limited to a data rate of 800 Mbps.
  • increasing the capacity of a memory system by increasing the number of memory modules connected to the same transmission channel comes at the expense of reduced data rates.
  • FIG. 1 is schematic illustration of a memory system, according to one embodiment.
  • FIG. 3 is cross-sectional view of the memory system from FIG. 1, according to an embodiment.
  • the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package.
  • Other embodiments may include memory modules that have a different number of memory ranks, such as one module with two memory ranks and another module with four memory ranks.
  • FIG. 1 is schematic illustration of a memory system 10, according to one embodiment.
  • the memory system 10 includes a memory controller 20 and two dual inline memory modules (DIMMs) 30 interconnected via a data channel 12 and a command and address (C/A) channel 14.
  • DIMMs 30 are in a multi-drop configuration where DIMMA 30A is positioned closer to the memory controller 20 than DIMMB 3 OB.
  • Each memory DIMM 30 includes several memory device packages MP that store and output data under the control of the memory controller 20.
  • the memory device packages MP are organized into two different memory groups that represent three memory ranks.
  • a memory rank may refer to a set of memory connected to the same chip select signal that can be accessed simultaneously.
  • a memory rank may be 64 bits wide.
  • Memory group A and memory group B are positioned asymmetrically on each DIMM 30. That is, memory group B is closer to the memory controller 20 than memory group A. As a result, for each DIMM 30, the average length of the data channel 12 between the memory controller 20 and the group A memory packages MP is substantially longer than the average length of the data channel 12 between the memory controller 20 and the group B memory packages MP.
  • Each memory package MP also has on-die termination (ODT) 60 coupled between the data channel 12 and a termination voltage (VTT).
  • ODT may include several different resistors that are configurable to present a proper equivalent impedance to the data channel 12, which minimizes signal integrity issues such as signal reflections.
  • the value of the ODT is set in accordance with control information received from the memory controller 20. Additionally, the ODT for each memory group can be set independently of the ODT for the other memory groups.
  • the DIMMs 30 may represent any type of DIMMs, such as a small outline DIMMs (SO-DIMMs), unbuffered DIMMs, or buffered DIMMs.
  • SO-DIMMs small outline DIMMs
  • unbuffered DIMMs unbuffered DIMMs
  • buffered DIMMs buffered DIMMs
  • the data channel 12 includes multiple signal lines for carrying data signals (DQ) and data strobe (DQS) signals between the memory controller 20 and the memory packages MP.
  • the C/A channel 14 includes multiple signal lines for carrying C/A signals such as address signals (ADDR), chip select signals (CS), clock signals (CLK), ODT signals, as well as other types of control signals to the memory packages MP.
  • ADDR address signals
  • CS chip select signals
  • CLK clock signals
  • ODT signals ODT signals
  • the memory controller 20 is an integrated circuit (IC) chip that controls the operation of the memory system 10.
  • Examples of a memory controller 20 include a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC), etc.
  • Memory controller 20 includes a control circuit section 50 and an interface circuit 52.
  • the control circuit 50 generates ODT control information for setting the ODT values of the memory packages MP, in addition to other general control information and memory commands.
  • the settings for the ODT values can vary depending on whether data is being read from or written to the DIMMs.
  • the ODT settings can also vary depending on which memory group is being accessed. The ODT settings are explained in greater detail in conjunction with FIG. 4.
  • FIG. 2 is a more detailed view of a DIMM 30, according to an embodiment.
  • the DIMM 30 is suitable for use as DIMMA 30A or DIMMB 30B from FIG. 1.
  • the DIMM 30 includes a row of connector pins 202 at the bottom edge of the DIMM 30 through which the MPs can communicate with the memory controller 20.
  • the connector pins 202 may include pins for the data channel 12, pins for the C/A channel 14, and pins for power and ground.
  • the portion of the data channel 12 on the DIMM is comprised of individual signaling lines (e.g., 12A-12D) that connect the memory packages MP to the connector pins 202.
  • the signaling lines may be metal traces or other types of electrically conductive structures that create a path for carrying electrical signals to the memory packages MP.
  • each MP is shown as being coupled to only a single data signaling line (e.g., 12A, 12B, 12C or 12D). In practice, there may be multiple (e.g. sixteen) data signaling lines 12A-12D connected to each MP.
  • the total length of the data signaling line 12A to memory group A is substantially greater than the total length of the data signaling line 12A to memory group B (L3+L2).
  • the total length of the data signaling line 12A to memory group A is substantially greater than the total length of the data signaling line 12A to memory group B (L4+L2).
  • the average length of the data channel 12 to memory group A is substantially greater than the average length of the data channel 12 to memory group B.
  • FIG. 4 is a table illustrating ODT settings for the memory system 10 of FIG. 1, according to an embodiment.
  • Three different ODT settings are possible for each memory group: no termination (i.e., a high impedance, indicated as "No term” in Fig. 4), a smaller impedance of 25 ohms, and a larger impedance of 45 ohms.
  • the ODT is considered disabled if set to a no termination state and enabled when set to an impedance such as 25 or 45 ohms.
  • the active DIMM refers to the DIMM being accessed during the memory access operation, either for reading data or writing data.
  • the idle DIMM refers to the DIMM that is not being accessed during the memory access operation.
  • the idle DIMM is configured so that the ODT of group A of the idle DIMM is enabled while the ODT of group B of the idle DIMM is disabled. Terminating the furthest memory group of the idle DIMM minimizes signal reflections that would otherwise be caused by the signal stub of the idle DIMM.
  • the ODT of DIMMB group A is set to 25 ohms and DIMMB group B is not terminated.
  • the ODT of DIMMA group A is set to 25 ohms and DIMMA group B is not terminated.
  • FIG. 5 is cross-sectional view of a memory system 10, according to another embodiment.
  • the memory system 10 of FIG. 5 is similar to the memory system of FIG. 3, but now includes different DIMMs 530A and 530B.
  • LI represents the approximate length of the data signaling line 12A between the connector 305 and a memory package MP of memory group C.
  • L2 represents the
  • LI is substantially greater than L2.
  • the total length of the data signaling line 12A to memory group D (L4+L1) is substantially greater than the total length of the data signaling line 12A to memory group C (L4+L2).
  • the average length of the data channel 12 to memory group C is substantially greater than the average length of the data channel 12 to memory group D.
  • DIMMB group C During read operations from DIMMB group C, the ODT of DIMMB group D is set to 40 ohms and DIMMB group C is left unterminated. Terminating DIMMB group D, which is further from the memory controller 20, minimizes signal reflections that would otherwise be caused by DIMMB group D. Also, during read operations from DIMM B, the ODT for DIMMA group A is set to 15 ohms and DIMMA group B is unterminated. During read operations from DIMMA, DIMMA is left unterminated. The ODT for DIMMB group C is set to 30 ohms and DIMMB group D is left unterminated.

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
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Abstract

A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks. For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.

Description

MEMORY RANK AND ODT CONFIGURATION IN A MEMORY
SYSTEM
INVENTORS
Minghui Han
Amir Amirkhany
Ravindranath Kollipara
Ralf Michael Schmitt
BACKGROUND
[0001] Memory systems can include a number of memory modules that are connected to a common transmission channel. The number of memory modules has an impact on the signal integrity of the transmission channel due to factors such as the loading on the transmission channel and increased signal reflections, which in turn limits the data rate of the transmission channel. For example, a memory system with two dual-rank modules connected to the same transmission channel may be able to reach a data rate of 1000 Mbps, whereas a memory system with three dual-rank modules connected to the same transmission channel may be limited to a data rate of 800 Mbps. As a result, increasing the capacity of a memory system by increasing the number of memory modules connected to the same transmission channel comes at the expense of reduced data rates.
BRIEF DESCRIPTION OF THE DRAWINGS
[0002] The teachings of the embodiments herein can be readily understood by considering the following detailed description in conjunction with the accompanying drawings.
[0003] Figure (FIG.) 1 is schematic illustration of a memory system, according to one embodiment.
[0004] FIG. 2 is a more detailed view of a DIMM from FIG. 1, according to an embodiment.
[0005] FIG. 3 is cross-sectional view of the memory system from FIG. 1, according to an embodiment.
[0006] FIG. 4 is a table of ODT settings for the memory system of FIG. 1, according to an embodiment.
[0007] FIG. 5 is cross-sectional view of a memory system, according to another embodiment. [0008] FIG. 6 is a table of ODT settings for the memory system of FIG. 5, according to an embodiment.
DETAILED DESCRIPTION OF EMBODIMENTS
[0009] Embodiments of the present disclosure relate to a memory system where memory capacity may be increased without impacting data rates. In one embodiment a memory system includes two memory modules and a memory controller. The first memory module includes at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks. The second memory module includes at least a third memory package corresponding to the first number of memory ranks (e.g. one memory rank) and a fourth memory package corresponding to the second number of memory ranks (e.g. two memory ranks).
[0010] For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. Other embodiments may include memory modules that have a different number of memory ranks, such as one module with two memory ranks and another module with four memory ranks.
[0011] The memory controller is coupled to the memory packages via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages. Through control of the ODT settings, the memory system can have increased storage capacity while still operating at a high data rate.
[0012] Reference will now be made in detail to several embodiments of the present disclosure, examples of which are illustrated in the accompanying figures. It is noted that wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict embodiments of the present disclosure for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles, or benefits touted, of the disclosure described herein.
[0013] FIG. 1 is schematic illustration of a memory system 10, according to one embodiment. The memory system 10 includes a memory controller 20 and two dual inline memory modules (DIMMs) 30 interconnected via a data channel 12 and a command and address (C/A) channel 14. The DIMMs 30 are in a multi-drop configuration where DIMMA 30A is positioned closer to the memory controller 20 than DIMMB 3 OB.
[0014] Each memory DIMM 30 includes several memory device packages MP that store and output data under the control of the memory controller 20. The memory device packages MP are organized into two different memory groups that represent three memory ranks. A memory rank may refer to a set of memory connected to the same chip select signal that can be accessed simultaneously. In one embodiment, a memory rank may be 64 bits wide.
[0015] Memory group A represents a single rank of memory. Each memory package MP in memory group A may include a single memory die. Memory group B represents two ranks of memory and each memory package MP in group B is a part of both ranks of memory. Each memory package MP may include two memory dies that can be addressed independently of each other with different chip select signals to provide dual-rank
functionality. For example, the memory packages MP in memory group B may include stacked memory dies. In one embodiment, the memory packages MP include dynamic random access memory (DRAM) or other types of memory.
[0016] Memory group A and memory group B are positioned asymmetrically on each DIMM 30. That is, memory group B is closer to the memory controller 20 than memory group A. As a result, for each DIMM 30, the average length of the data channel 12 between the memory controller 20 and the group A memory packages MP is substantially longer than the average length of the data channel 12 between the memory controller 20 and the group B memory packages MP.
[0017] Each memory package MP also has on-die termination (ODT) 60 coupled between the data channel 12 and a termination voltage (VTT). The ODT may include several different resistors that are configurable to present a proper equivalent impedance to the data channel 12, which minimizes signal integrity issues such as signal reflections. For each memory group, the value of the ODT is set in accordance with control information received from the memory controller 20. Additionally, the ODT for each memory group can be set independently of the ODT for the other memory groups.
[0018] Simulation results show that the asymmetric placement of memory groups combined with precise control of the ODT settings across the different memory groups in the two triple-rank DIMMS 30 of FIG. 1 results in a memory system 10 that has better signal integrity than memory systems using three dual-rank DIMMs. The improved signal integrity allows the memory system 10 to have a fast data rate that is comparable to lower capacity memory systems that use only two dual-rank DIMMs 10. Thus, the disclosed memory system 10 with two triple-rank DIMMs 30 is able to increase storage capacity without sacrificing on performance.
[0019] In some embodiments, the DIMMs 30 may represent any type of DIMMs, such as a small outline DIMMs (SO-DIMMs), unbuffered DIMMs, or buffered DIMMs.
Additionally, in FIG. 1, each rank of memory includes four memory packages MP. In other embodiments, each rank of memory may include a different number of memory packages MP, such as eight or more memory packages MP.
[0020] The data channel 12 includes multiple signal lines for carrying data signals (DQ) and data strobe (DQS) signals between the memory controller 20 and the memory packages MP. The C/A channel 14 includes multiple signal lines for carrying C/A signals such as address signals (ADDR), chip select signals (CS), clock signals (CLK), ODT signals, as well as other types of control signals to the memory packages MP.
[0021] In one embodiment, the memory controller 20 is an integrated circuit (IC) chip that controls the operation of the memory system 10. Examples of a memory controller 20 include a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC), etc. Memory controller 20 includes a control circuit section 50 and an interface circuit 52. The control circuit 50 generates ODT control information for setting the ODT values of the memory packages MP, in addition to other general control information and memory commands. The settings for the ODT values can vary depending on whether data is being read from or written to the DIMMs. The ODT settings can also vary depending on which memory group is being accessed. The ODT settings are explained in greater detail in conjunction with FIG. 4.
[0022] The interface circuit 52 receives the ODT control information from the control circuit 50 and transmits the ODT control information to the memory packages MP 30 via the C/A channel 14. In one embodiment, setting the ODT values is a two step process. During initialization, the memory controller 20 transmits a mode register command that configures the possible resistance values (e.g. 25 ohm, 45 ohm, unterminated) that the ODT can be set to during future memory operations. Setting the resistance values to unterminated effectively disables the ODT. This information can be stored within mode registers (not shown) inside the MPs. During memory access operations, the memory controller 20 toggles one or more ODT control signals within the C/A channel 14 that selects one of the possible resistance values, as indicated by the mode register setting. Each memory group may be controlled by its own set of ODT control signals so the ODT settings for different memory groups are independent of each other.
[0023] FIG. 2 is a more detailed view of a DIMM 30, according to an embodiment. The DIMM 30 is suitable for use as DIMMA 30A or DIMMB 30B from FIG. 1. The DIMM 30 includes a row of connector pins 202 at the bottom edge of the DIMM 30 through which the MPs can communicate with the memory controller 20. The connector pins 202 may include pins for the data channel 12, pins for the C/A channel 14, and pins for power and ground.
[0024] The portion of the data channel 12 on the DIMM is comprised of individual signaling lines (e.g., 12A-12D) that connect the memory packages MP to the connector pins 202. The signaling lines may be metal traces or other types of electrically conductive structures that create a path for carrying electrical signals to the memory packages MP. For ease of illustration, each MP is shown as being coupled to only a single data signaling line (e.g., 12A, 12B, 12C or 12D). In practice, there may be multiple (e.g. sixteen) data signaling lines 12A-12D connected to each MP.
[0025] Each data signaling line 12A-12D is coupled to and shared between two memory packages MP: one memory package MP in group A and another memory package MP in group B. LI represents the approximate length of the data signaling lines 12A-12D between the connector pins 202 and the memory packages MP of memory group A. L2 represents the approximate length of the data signaling lines 12A-12D between the connector pins 202 and the memory packages MP of memory group B. Due to the asymmetric placement of the memory groups, LI is substantially greater than L2. When the data channel 12 is viewed as a whole, the average length of the data channel 12 to memory group A is substantially longer than the average length of the data channel 12 to memory group B. Simulation results have generally shown that, to achieve satisfactory signal integrity and data rates, LI should be greater than L2 by at least 10% of the height H of the memory package MP. Thus, in one embodiment, LI is substantially greater than L2 if it exceeds L2 by at least 10% of a height H of a memory package MP. For example, if MP is 10 mm tall, LI should be greater than L2 by at least 1 mm.
[0026] In FIG. 2, both memory groups are located on the same side of the DIMM 30. In other embodiments, the memory groups may be on opposite sides of the DIMM 30. For example, memory group A may be attached to the back side of the DIMM 30 while memory group B may be attached to the front side of the DIMM 30. The memory groups on opposite DIMM sides may also be partially overlapping to create an asymmetric clamshell-like configuration that reduces the height of the DIMM 30 while still maintaining the benefits of the asymmetric configuration.
[0027] FIG. 3 is cross-sectional view of a memory system 10, according to an embodiment. The memory controller 20 is coupled to a printed circuit board (PCB) 130, for example, through an integrated circuit socket or by being directly soldered to the PCB 130. The DIMMs 30 are coupled to the PCB 130 through DIMM connectors 305.
[0028] Only one data signaling line 12A of the data channel 12 is shown in FIG. 3. The data signaling line 12A includes a portion that is routed through the PCB and other portions that are routed across the DIMMs 30. L3 represents the length of the signaling line 12A between the memory controller 20 and DIMMA 3 OA. L4 represents the length of the signaling line 12A between the memory controller 20 and DIMMB 30B. L4 is greater than L3 due to the staggered configuration of the DIMMs 30.
[0029] For DIMMA 3 OA, the total length of the data signaling line 12A to memory group A (L3+L1) is substantially greater than the total length of the data signaling line 12A to memory group B (L3+L2). Similarly, for DIMMB 30B, the total length of the data signaling line 12A to memory group A (L4+L1) is substantially greater than the total length of the data signaling line 12A to memory group B (L4+L2). When the signals of the data channel 12 are viewed as a whole, for each DIMM, the average length of the data channel 12 to memory group A is substantially greater than the average length of the data channel 12 to memory group B.
[0030] The shape of the data signal line 12A includes signal stubs that can create signal reflections if the impedance throughout the signal line 12A is not properly matched. For example, when writing to the memory packages MP of DIMMA, the portion of the signal line 12A that is routed on DIMMB is a signal stub that can cause signal reflections. As another example, when reading from group B of DIMMA, the portion of the signal line 12A extending from DIMMA group B to DIMMA group A forms another signal stub that can create signal reflections. These signal integrity issues are addressed through independent control of the ODT across the memory groups, which are explained in conjunction with FIG. 4.
[0031] FIG. 4 is a table illustrating ODT settings for the memory system 10 of FIG. 1, according to an embodiment. Three different ODT settings are possible for each memory group: no termination (i.e., a high impedance, indicated as "No term" in Fig. 4), a smaller impedance of 25 ohms, and a larger impedance of 45 ohms. The ODT is considered disabled if set to a no termination state and enabled when set to an impedance such as 25 or 45 ohms. As used herein, the active DIMM refers to the DIMM being accessed during the memory access operation, either for reading data or writing data. The idle DIMM refers to the DIMM that is not being accessed during the memory access operation.
[0032] During both read and write operation to the active DIMM, the idle DIMM is configured so that the ODT of group A of the idle DIMM is enabled while the ODT of group B of the idle DIMM is disabled. Terminating the furthest memory group of the idle DIMM minimizes signal reflections that would otherwise be caused by the signal stub of the idle DIMM. Specifically, during write operations to DIMMA, the ODT of DIMMB group A is set to 25 ohms and DIMMB group B is not terminated. During write operations to DIMMB, the ODT of DIMMA group A is set to 25 ohms and DIMMA group B is not terminated. During read operations from DIMMA, the ODT of DIMMB group A is set to 25 ohms and DIMMB group B is not terminated. During read operations from DIMMB, the ODT of DIMMA group A is set to 25 ohms and DIMMA group B is not terminated.
[0033] During write operations, for the active DIMM, the termination of the group being written to is disabled and the termination of the other group is enabled. Terminating the memory group that is not being written to mitigates signal reflections that can be caused, for example, by the parasitic input capacitance associated with the memory groups.
Specifically, when writing to DIMMA group A, DIMMA group A is unterminated and the ODT of DIMMA group B is set to forty five ohms. When writing to DIMMA group B, DIMMA group B is unterminated and the ODT of DIMMA group A set to forty five ohms. When writing to DIMMB group A, DIMMB group A is unterminated and the ODT of DIMMB group B is set to forty five ohms. When writing to DIMMB group B, DIMMB group B is unterminated and the ODT of DIMMB group A set to forty five ohms.
[0034] During read operations from group B of the active DIMM, the ODT on the active DIMM for group A is set to 45 ohms and group B of the active DIMM is left unterminated. Activating the termination on group A prevents reflections that would otherwise be caused by the signals read out from group B. During read operations from group A of the active DIMM, the ODT for both groups of the active DIMM is unterminated.
[0035] Beneficially, simulation testing on an impedance model of the data channel 12 and memory packages MP have shown that these ODT settings, when used in combination with two triple rank memory DIMMs, maintains good signal integrity at high data rates. These particular ODT settings shown in FIG. 4 are merely examples of possible ODT settings that have been selected based one particular channel 12 configuration. In other embodiments, the ODT values may have different impedances depending on factors such as the target data rate and trace impedance.
[0036] FIG. 5 is cross-sectional view of a memory system 10, according to another embodiment. The memory system 10 of FIG. 5 is similar to the memory system of FIG. 3, but now includes different DIMMs 530A and 530B.
[0037] DIMMA 530A is a dual-rank memory module. DIMMA 530A includes two groups of memory packages MP, group A and group B. Group A and group B each represent a single rank of memory. Group A and group B are located on opposite sides of the DIMMA 530A in a clamshell configuration. Because group A and group B are symmetric, the length of the data signaling line 12A to the group A memory package MP is substantially equal to the length of the data signaling line 12 A to the group B memory package MP.
[0038] DIMMB 530B is a quad-rank memory module. DIMMB 530B includes two groups of memory packages MP, group C and group D. Group C represents two memory ranks, and group D represents another two memory ranks. Each of the memory packages MP in group C and group D spans two memory ranks.
[0039] LI represents the approximate length of the data signaling line 12A between the connector 305 and a memory package MP of memory group C. L2 represents the
approximate length of the data signaling line 12A between the connector 305 and a memory package MP of memory group D. Due to the asymmetric placement of the memory groups, LI is substantially greater than L2. The total length of the data signaling line 12A to memory group D (L4+L1) is substantially greater than the total length of the data signaling line 12A to memory group C (L4+L2). When the data channel 12 is viewed as a whole, the average length of the data channel 12 to memory group C is substantially greater than the average length of the data channel 12 to memory group D.
[0040] FIG. 6 is a table illustrating ODT settings for the memory system 10 of FIG. 5, according to an embodiment. During write operations to DIMMB, group C is always unterminated and group D is terminated, regardless of whether the write operation is to group C or group D. Simulation results have shown that terminating group D instead of group C results in better signal integrity, which can be attributed in part to group D having a large input capacitance (e.g. twice as much as group A). Specifically, when writing to group C, the ODT for group D is set to 50 ohms. When writing to group D, the ODT for group D is set to 80 ohms. Group C and group D have different termination values because group C and group D are in different locations of the data channel 12. Also, during write operations to DIMMB, the ODT for group A of DIMMA is set to 15 ohms and group B of DIMM A is unterminated. [0041] During write operations to DIMMA, the ODT of the group being written to is set to 80 ohms and the other group is left unterminated. Additionally, the ODT of DIMMB group C is set to 15 ohms and group D is left unterminated.
[0042] During read operations from DIMMB group C, the ODT of DIMMB group D is set to 40 ohms and DIMMB group C is left unterminated. Terminating DIMMB group D, which is further from the memory controller 20, minimizes signal reflections that would otherwise be caused by DIMMB group D. Also, during read operations from DIMM B, the ODT for DIMMA group A is set to 15 ohms and DIMMA group B is unterminated. During read operations from DIMMA, DIMMA is left unterminated. The ODT for DIMMB group C is set to 30 ohms and DIMMB group D is left unterminated.
[0043] Embodiments disclosed herein include both triple rank DIMM configurations as well as dual-rank / quad-rank DIMM configurations. Both configurations have fewer signal stubs than triple DIMM systems without losing storage capacity by placing more memory ranks on a DIMM. The effect of remaining signal stubs and varying input capacitances across the memory system 10 is addressed by asymmetrically locating the memory packages MP and tightly controlling the ODT values across the different DIMMs. As a result, the memory system 10 has a high storage capacity while still operating at a high data rate.
[0044] Upon reading this disclosure, those of skill in the art may appreciate still additional alternative designs for ODT and rank configuration in a memory system. Thus, while particular embodiments and applications of the present disclosure have been illustrated and described, it is to be understood that the disclosure is not limited to the precise construction and components disclosed herein. Various modifications, changes and variations which may be apparent to those skilled in the art may be made in the arrangement, operation and details of the method and apparatus of the present disclosure herein without departing from the spirit and scope of the disclosure as defined in the appended claims.

Claims

WHAT IS CLAIMED IS:
1. A memory module, comprising:
a data line;
a connector pin coupled to the data line;
a first memory package coupled to the data line, the first memory package
corresponding to a first number of memory ranks; and
a second memory package coupled to the data line, the second memory package corresponding to a second number of memory ranks that is greater than the first number of memory ranks.
2. The memory module of claim 1, wherein a first length of the data line between the connector pin and the first memory package is substantially greater than a second length of the data line between the connector pin and the second memory package.
3. The memory module of claim 2, wherein the first length of the data line is greater than the second length of the data line by at least ten percent of a height of the second memory package.
4. The memory module of claim 1 , wherein the first memory package and the second memory package are on a same side of the memory module.
5. The memory module of claim 1, wherein the first memory package and the second memory package are on opposing sides of the memory module.
6. The memory module of claim 1 , wherein the first number of memory ranks is one memory rank and the second number of memory ranks is two memory ranks.
7. The memory module of claim 1, wherein on-die termination (ODT) of the first memory package is disabled and ODT of the second memory package is enabled for write operations to the first memory package.
8. A memory system, comprising:
a first memory module that includes a first memory package corresponding to a first number of memory ranks and a second memory package corresponding to a second number of memory ranks that is greater than the first number of memory ranks; and a memory controller coupled to the first memory package and second memory package via a common data line.
9. The memory system of claim 8, wherein a first length of the data line between the memory controller and the first memory package is substantially greater than a second length of the data line between the memory controller and the second memory package.
10. The memory system of claim 8, wherein the first number of memory ranks is a single memory rank and the second number of memory ranks is two memory ranks.
11. The memory system of claim 8, wherein the memory controller disables on-die termination (ODT) of the first memory package and enables ODT of the second memory package for write operations to the first memory package.
12. The memory system of claim 8, wherein the memory controller enables on-die termination (ODT) of the first memory package and disables the ODT of the second memory package for write operations to the second memory package.
13. The memory system of claim 8, wherein the memory controller enables the on-die termination (ODT) of the first memory package and disables the ODT of the second memory package for read operations from the second memory package.
14. The memory system of claim 8, further comprising:
a second memory module that includes a third memory package corresponding to the first number of memory ranks and a fourth memory package corresponding to the second number of memory ranks,
wherein the memory controller transfers data with the third memory package and the fourth memory package via the common data line.
15. The memory system of claim 14, wherein a third length of the data line between the memory controller and the third memory package is substantially greater than a fourth length of the data line between the memory controller and the fourth memory package.
16. The memory system of claim 14, wherein the second memory module is positioned further from the memory controller than the first memory module.
17. The memory system of claim 14, wherein the memory controller enables the on-die termination (ODT) of the first memory package and disables the ODT of the second memory package for both read and write operations to the third memory package and the fourth memory package of the second memory module.
18. A memory controller comprising :
control logic to generate on-die termination (ODT) control information, the ODT control information to control a first memory module, the first memory module including a first memory package corresponding to a first number of memory ranks and a second memory package corresponding to a second number of memory ranks that is greater than the first number of memory ranks; and
an interface to be coupled to the first memory package and second memory package via a common data line, the interface transmitting the ODT control information to the first memory module.
19. The memory controller of claim 18, wherein the interface transmits the ODT control information via a first ODT control signal for controlling ODT of the first memory package and a second ODT control signal for controlling ODT of the second memory package.
20. The memory controller of claim 18, wherein the ODT control information disables the ODT of the first memory package and enables ODT of the second memory package for write operations to the first memory package.
21. The memory controller of claim 18, wherein the ODT control information enables the ODT of the first memory package and disables ODT of the second memory package for write operations to the second memory package.
22. The memory controller of claim 18, wherein the ODT control information enables ODT of the first memory package and disables ODT of the second memory package for read operations from the second memory package.
23. The memory controller of claim 18, wherein the ODT control information further controls a second memory module that includes a third memory package corresponding to the first number of memory ranks and a fourth memory package corresponding to the second number of memory ranks, and the interface is coupled to the third memory package and fourth memory package via the common data line, the interface transmitting the ODT control information to the second memory module.
24. The memory controller of claim 23, wherein the ODT control information enables the ODT of the first memory package and disables ODT of the second memory package for both read and write operations to the third memory package and the fourth memory package of the second memory module.
25. A method of operation in a memory system, comprising:
generating on-die termination (ODT) control information to control a first memory module, the first memory module including a first memory package corresponding to a first number of memory ranks and a second memory package corresponding to a second number of memory ranks that is greater than the first number of memory ranks, the first and second memory package coupled to a memory controller via a common data line; and
transmitting the ODT control information to the first memory module.
26. The method of claim 25, wherein the ODT control information disables the ODT of the first memory package and enables ODT of the second memory package for write operations to the first memory package.
27. The method of claim 25, wherein the ODT control information enables the ODT of the first memory package and disables ODT of the second memory package for write operations to the second memory package.
28. The method of claim 25, wherein the ODT control information enables ODT of the first memory package and disables ODT of the second memory package for read operations from the second memory package.
29. The method of claim 25, wherein the ODT control information further controls a second memory module that includes a third memory package corresponding to the first number of memory ranks and a fourth memory package corresponding to the second number of memory ranks, the third memory package and fourth memory package coupled to the memory controller via the common data line, and the ODT control information enables the ODT of the first memory package and disables ODT of the second memory package for both read and write operations to the third and fourth memory packages of the second memory module.
30. A memory system, comprising:
a first memory module including a first memory package and a second memory
package each corresponding to a first number of memory ranks; a second memory module including a third memory package and a fourth memory package each corresponding to a second number of memory ranks that is greater than the first number of memory ranks; and
a memory controller coupled to the first, second, third and fourth memory packages via a common data line.
31. The memory system of claim 30, wherein a first length of the data line between the memory controller and the first memory package is substantially equal to a second length of the data line between the memory controller and the second memory package.
32. The memory system of claim 31 , wherein a third length of the data line between the memory controller and the third memory package is substantially greater than a fourth length of the data line between the memory controller and the fourth memory package.
33. The memory system of claim 30, wherein the second memory module is positioned further from the memory controller than the first memory module.
34. The memory system of claim 30, wherein the memory controller enables on-die termination (ODT) of the third memory package and disables ODT of the fourth memory package for write operations to the fourth memory package.
35. The memory system of claim 30, wherein the memory controller disables on-die termination (ODT) of the third memory package and enables ODT of the fourth memory package for read operations from the third memory package.
36. The memory system of claim 30, wherein the first number of memory ranks is one memory rank and the second number of memory ranks is two memory ranks.
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