CN104820659A - Multi-mode dynamic configurable high-speed memory access interface for coarse grain reconfigurable system - Google Patents
Multi-mode dynamic configurable high-speed memory access interface for coarse grain reconfigurable system Download PDFInfo
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Abstract
A multi-mode dynamic configurable high-speed memory access interface for a coarse grain reconfigurable system is based on a traditional memory access interface and additionally provided with an access mode configurable function and can dynamically configure four corresponding access modes including a single data transfer mode, a burst data transfer mode, a two-dimensional data transfer mode and a chain data transfer mode for different types of data distribution when the system runs. The multi-mode dynamic configurable high-speed memory access interface for the coarse grain reconfigurable system can initiate a plurality of data access requests to an off-chip synchronous dynamic memory in advance according to configuration information and forms of data distribution so as to reduce access delay of data and configuration.
Description
Technical field
The present invention relates to imbedded reconfigurable design field, a kind of multi-mode towards coarseness flow for dynamic reconfigurable system dynamically can join high speed memory access Interface design, can be used for high-performance reconfigurable system, to realize and the data accelerating the outer synchronous dynamic random access memory of reconfigurable processor and sheet are transmitted.
Background technology
General processor and special IC (ASIC) are all two kinds of main computation schemas all the time.Improve constantly along with to the requirement of counting yield, a kind of Reconfigurable Computing Technology taking into account general processor dirigibility and special IC high efficiency starts to enter people's eyes.A certain algorithm, by the configuration to arithmetic element, can be converted to the form of data stream by Reconfigurable Computing Technology, improves operation efficiency.Here the coarseness dynamic reconfigurable processor mentioned is exactly a kind of on-chip system chip based on Reconfigurable Computing Technology (SOC).
Reconfigurable data memory access interface in the present invention for the outer synchronous dynamic random access memory of sheet be DDR2 SDRAM storage chip.This storer has three-dimensional structure, has needed selection and the activation of page, row, column before reading and writing data, and the activation of wherein going and pre-charge process need the plenty of time.For such external memory characteristic, the mechanism that major part memory interface all adopts page to reset, storer not same page is relatively independent, can carry out activation and the precharge of page simultaneously, by adjacent twice accessing operation being distributed in not on same page, can the activation of cover row and precharge time effectively.The present invention adds the memory access mechanism for multiple access module on this basis.
Summary of the invention
The object of the invention is to: in reconfigurable processor chip design process, the design relation of the external memory access interface of high-throughput to the performance of whole chip, the memory access demand of the various algorithm of demand fulfillment.The memory access interface of current reconfigurable processor is only optimized for a certain class algorithm, or memory access optimization is not carried out to algorithm, the present invention proposes the wider memory access interface of an optimization range, memory access optimization can be carried out for 13 large class algorithms, be applicable to the external memory access interface of reconfigurable processor, take suitable scheme to improve L2 cache hit rate, reduce internal storage access time delay, improve processor memory system data throughput, promote processor chips performance.
Technical scheme of the present invention is as follows: be applied to and dynamically can join by system bus, reconfigurable processor, multi-mode the restructural external memory access system that outside high speed memory access interface, sheet, synchronous dynamic random access memory is formed, wherein system bus and reconfigurable processor initiate request of data to memory access interface, after memory access interface completes process to request of data, outside sheet, synchronous dynamic random access memory initiates external memory request of access, completing the access of data. multi-mode dynamically can join high speed memory access interface for different Data distribution8 types, can in system operation, dynamically be configured to corresponding four kinds of access modules, comprise: forms data transmission mode, burst of data transmission mode, 2-D data transmission mode, chained record transmission mode, and according to configuration information and Data distribution8 form, initiate multiple data access request in advance, thus minimizing data access delay.
Described multi-mode dynamically can be joined high speed memory access interface and be comprised configuration interface, reconfigurable system data-interface, bus interface, Configuration Control Unit, function execution module, external memory interface; Wherein, Configuration Control Unit can resolve the configuration information sent from reconfigurable processing unit; Reconfigurable system data-interface is used for the data interaction that multi-mode dynamically can join high speed memory access interface and reconfigurable arrays; Access request in bus interface completion system bus; Function execution module completes the reconstruct of data path according to configuration information, comprise forms data transport module, burst of data transport module, 2-D data transport module, chained record transport module, these modules support forms data transmission mode, burst of data transmission mode, 2-D data transmission mode, chained record transmission mode respectively accordingly; Forms data transport module is identical with the definition in AHB host-host protocol with burst of data transmission mode; External memory interface and the outer synchronous dynamic random access memory of sheet carry out alternately, completing the transmission of data.
2-D data transport module in described function execution module, comprises data line address caching, the long buffer memory of data line, jump length buffer memory, data line entry number buffer memory, data line counter, data directory counter, request of data address caching; Wherein, data line address caching, jump length buffer memory, data line entry number buffer memory are used for the relevant configuration information that buffer memory accepts from configuration module; Data line counter is for recording current data request row information within the data block; Data directory counter is for recording current data request positional information within the data block; Request of data address caching is for recording the physical address of current data request.
Chained record transmission mode in described function execution module comprises row 1 node first address buffer memory, 7 node redirect step-length buffer memorys, 8 node ' s length buffer memorys, nodes buffer memory, node counter, data directory counter, request of data address cachings; Wherein, 1 node first address buffer memory, 7 node redirect step-length buffer memorys, 8 node ' s length buffer memorys, nodes buffer memorys are used for the relevant configuration information that buffer memory accepts from configuration module; Node counter is for recording current data request in N number of node of Data-Link; Data directory counter is positioned at the N number of of present node for recording current data request; Request of data address caching is for recording the physical address of current data request.
Described multi-mode dynamically can join high speed memory access interface when working with 2-D data transmission mode, main flow is: (1) obtains the data line address of two-dimensional blocks of data from configuration information, data line length, jump length, data line entry number, data directory counter and data line counter are set to 0, (2) begin through external memory interface and send request of data to synchronous dynamic random access memory outside sheet, the request of data number that usage data call number counter records current line has been initiated, (3) when data directory counter is equal with data line length, data line counter adds 1, request of data address caching adds jump length, (4) when data line counter is equal with line number, the transmission of end data request, (5) when the outer synchronous dynamic random access memory of sheet sends the full signal of request buffer memory, suspend the transmission of request of data.
Described multi-mode dynamically can join high speed memory access interface when working with chained record transmission mode, main flow is: (1) obtains N-1 node redirect step-length from configuration information, 1 node first address, the node ' s length of N number of Data-Link, nodes N(N is not more than 8), data counter and node counter are set to 0, (2) begin through external memory interface and send request of data to synchronous dynamic random access memory outside sheet, the request of data number that usage data counter records present node has been initiated, (3) when data directory counter is equal with present node length, node counter adds 1, request of data address caching adds present node jump length, (4) when node counter is equal with nodes, the transmission of end data request, (5) when the outer synchronous dynamic random access memory of sheet sends the full signal of request buffer memory, suspend the transmission of request of data.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, and forms a part for instructions, together with embodiments of the present invention for explaining the present invention, is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is that multi-mode dynamically can join high speed memory access interface structure block diagram
Fig. 2 is 2-D data transport module structured flowchart;
Fig. 3 is chained record transport module structured flowchart;
Fig. 4 is 2-D data transport module flowchart;
Fig. 5 is chained record transport module flowchart.
Embodiment
Below in conjunction with accompanying drawing, the present invention is illustrated further.
As shown in Figure 1, the present invention is applied to and dynamically can joins by system bus, reconfigurable processor, multi-mode the restructural external memory access system that outside high speed memory access interface, sheet, synchronous dynamic random access memory is formed.Wherein system bus and reconfigurable processor initiate request of data to memory access interface, and after memory access interface completes process to request of data, outside sheet, synchronous dynamic random access memory initiates external memory request of access, completes the access of data.Multi-mode dynamically can be joined high speed memory access interface and be comprised configuration interface, reconfigurable system data-interface, bus interface, Configuration Control Unit, function execution module, external memory interface.Wherein, Configuration Control Unit can resolve the configuration information sent from reconfigurable processing unit; Reconfigurable system data-interface is used for the data interaction that multi-mode dynamically can join high speed memory access interface and reconfigurable arrays; Access request in bus interface completion system bus; Function execution module completes the reconstruct of data path according to configuration information, comprise forms data transport module, burst of data transport module, 2-D data transport module, chained record transport module, these modules support forms data transmission mode, burst of data transmission mode, 2-D data transmission mode, chained record transmission mode respectively accordingly.Forms data transport module is identical with the definition in traditional AMBA2.0 AHB host-host protocol with burst of data transmission mode.External memory interface and the outer synchronous dynamic random access memory of sheet carry out alternately, completing the transmission of data.
As shown in Figure 2, the 2-D data transport module in function execution module, comprises data line address caching, the long buffer memory of data line, jump length buffer memory, data line entry number buffer memory, data line counter, data directory counter, request of data address caching.Wherein, data line address caching, data line length buffer memory, jump length buffer memory, data line entry number buffer memory are used for the relevant configuration information that buffer memory accepts from configuration module; Data line counter is for recording current data request row information within the data block; Data directory counter is for recording current data request positional information within the data block; Request of data address caching is for recording the physical address of current data request.
As shown in Figure 3, the chained record transmission mode in function execution module comprises row 1 node first address buffer memory, 7 node redirect step-length buffer memorys, 8 node ' s length buffer memorys, nodes buffer memory, node counter, data directory counter, request of data address cachings.Wherein, 1 node first address buffer memory, 7 node redirect step-length buffer memorys, 8 node ' s length buffer memorys, nodes buffer memorys are used for the relevant configuration information that buffer memory accepts from configuration module; Node counter is for recording current data request in N number of node of Data-Link; Data directory counter is positioned at the N number of of present node for recording current data request; Request of data address caching is for recording the physical address of current data request.
As shown in Figure 4, multi-mode dynamically can join high speed memory access interface when working with 2-D data transmission mode, main flow is: from configuration information, first obtain the data line address of two-dimensional blocks of data, data line length, jump length, data line entry number, and data directory counter and data line counter are set to 0.Then begin through external memory interface and send request of data to synchronous dynamic random access memory outside sheet, the request of data number that usage data call number counter records current line has been initiated.Then when data directory counter is equal with data line length, data line counter adds 1, and request of data address caching adds jump length, simultaneously when data line counter is equal with line number, and the transmission of end data request.Finally when the outer synchronous dynamic random access memory of sheet sends the full signal of request buffer memory, suspend the transmission of request of data.
As shown in Figure 5, multi-mode dynamically can join high speed memory access interface when working with chained record transmission mode, main flow is: from configuration information, first obtain N-1 node redirect step-length, 1 node first address, the node ' s length of N number of Data-Link, nodes N(N are not more than 8), data counter and node counter are set to 0.Then request of data is sent by external memory interface to synchronous dynamic random access memory outside sheet, the request of data number that usage data counter records present node has been initiated.Then, when data directory counter is equal with present node length, node counter adds 1, and request of data address caching adds present node jump length, time when node counter is equal with nodes, the transmission of end data request.Finally, when the outer synchronous dynamic random access memory of sheet sends the full signal of request buffer memory, the transmission of request of data is suspended.
Below in conjunction with example, the present invention is further described.
This example carries out emulation experiment on FPGA.Adopt following test macro: reconfigurable processor comprising 4 8*8 computing arrays, ARM7 flush bonding processor, two panels capacity are the memory access interface that the outer synchronous dynamic random access memory of DDR2 sheet of 256MB and the present invention describe.Comparison system adopts traditional memory access interface, is connected with reconfigurable processor by AMBA2.0 ahb bus, and other modules of comparison system are identical with test macro of the present invention.On reconfigurable processor, FFT(Fast Fourier Transform (FFT) is run during experiment) algorithm, the working time of compare test system and comparison system.Because both all use identical reconfigurable processor, so performance difference is embodied in the performance of memory access interface.Experimental result shows, when external clock is 40Mhz, the fft algorithm of 64 runs and once needs 9.01us on test macro, comparison system runs and once needs 11.55 us, and the external memory access efficiency of fft algorithm improves 32% as can be seen here.
Claims (6)
1. the multi-mode towards coarseness reconfigurable system dynamically can join a high speed memory access interface, is applied to and dynamically can joins by system bus, reconfigurable processor, multi-mode the restructural external memory access system that outside high speed memory access interface, sheet, synchronous dynamic random access memory is formed; Wherein system bus and reconfigurable processor initiate request of data to memory access interface, and after memory access interface completes process to request of data, outside sheet, synchronous dynamic random access memory initiates external memory request of access, completes the access of data; It is characterized in that, multi-mode dynamically can join high speed memory access interface for different Data distribution8 types, can in system operation, dynamically be configured to corresponding four kinds of access modules, comprise: forms data transmission mode, burst of data transmission mode, 2-D data transmission mode, chained record transmission mode, and according to configuration information and Data distribution8 form, initiate multiple data access request in advance, thus reduce data access delay.
2. the multi-mode towards coarseness flow for dynamic reconfigurable system according to claim 1 dynamically can join high speed memory access interface, it is characterized in that, multi-mode dynamically can be joined high speed memory access interface and be comprised configuration interface, reconfigurable system data-interface, bus interface, Configuration Control Unit, function execution module, external memory interface; Wherein, Configuration Control Unit can resolve the configuration information sent from reconfigurable processing unit; Reconfigurable system data-interface is used for the data interaction that multi-mode dynamically can join high speed memory access interface and reconfigurable arrays; Access request in bus interface completion system bus; Function execution module completes the reconstruct of data path according to configuration information, comprise forms data transport module, burst of data transport module, 2-D data transport module, chained record transport module, these modules support forms data transmission mode, burst of data transmission mode, 2-D data transmission mode, chained record transmission mode respectively accordingly; External memory interface and the outer synchronous dynamic random access memory of sheet carry out alternately, completing the transmission of data.
3. the multi-mode towards coarseness flow for dynamic reconfigurable system according to claim 2 dynamically can join high speed memory access interface, it is characterized in that, 2-D data transport module in function execution module, comprises data line address caching, the long buffer memory of data line, jump length buffer memory, data line entry number buffer memory, data line counter, data directory counter, request of data address caching; Wherein, data line address caching, data line length buffer memory, jump length buffer memory, data line entry number buffer memory are used for the relevant configuration information that buffer memory accepts from configuration module; Data line counter is for recording current data request row information within the data block; Data directory counter is for recording current data request positional information within the data block; Request of data address caching is for recording the physical address of current data request.
4. the multi-mode towards coarseness flow for dynamic reconfigurable system according to claim 2 dynamically can join high speed memory access interface, it is characterized in that, the chained record transmission mode in function execution module comprises row 1 node first address buffer memory, 7 node redirect step-length buffer memorys, 8 node ' s length buffer memorys, nodes buffer memory, node counter, data directory counter, request of data address cachings; Wherein, 1 node first address buffer memory, 7 node redirect step-length buffer memorys, 8 node ' s length buffer memorys, nodes buffer memorys are used for the relevant configuration information that buffer memory accepts from configuration module; Node counter is for recording current data request in N number of node of Data-Link; Data directory counter is positioned at the N number of of present node for recording current data request; Request of data address caching is for recording the physical address of current data request.
5. the multi-mode towards coarseness flow for dynamic reconfigurable system according to claim 1 dynamically can join high speed memory access interface, it is characterized in that, multi-mode dynamically can join high speed memory access interface when working with 2-D data transmission mode, main flow is: (1) obtains the data line address of two-dimensional blocks of data from configuration information, data line length, jump length, data line entry number, data directory counter and data line counter are set to 0, (2) begin through external memory interface and send request of data to synchronous dynamic random access memory outside sheet, the request of data number that usage data call number counter records current line has been initiated, (3) when data directory counter is equal with data line length, data line counter adds 1, request of data address caching adds jump length, (4) when data line counter is equal with line number, the transmission of end data request, (5) when the outer synchronous dynamic random access memory of sheet sends the full signal of request buffer memory, suspend the transmission of request of data.
6. the multi-mode towards coarseness flow for dynamic reconfigurable system according to claim 1 dynamically can join high speed memory access interface, it is characterized in that, multi-mode dynamically can join high speed memory access interface when working with chained record transmission mode, main flow is: (1) obtains N-1 node redirect step-length from configuration information, 1 node first address, the node ' s length of N number of Data-Link, nodes N(N is not more than 8), data counter and node counter are set to 0, (2) begin through external memory interface and send request of data to synchronous dynamic random access memory outside sheet, the request of data number that usage data counter records present node has been initiated, (3) when data directory counter is equal with present node length, node counter adds 1, request of data address caching adds present node jump length, (4) when node counter is equal with nodes, the transmission of end data request, (5) when the outer synchronous dynamic random access memory of sheet sends the full signal of request buffer memory, suspend the transmission of request of data.
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