CN104699641A - EDMA (enhanced direct memory access) controller concurrent control method in multinuclear DSP (digital signal processor) system - Google Patents
EDMA (enhanced direct memory access) controller concurrent control method in multinuclear DSP (digital signal processor) system Download PDFInfo
- Publication number
- CN104699641A CN104699641A CN201510123172.2A CN201510123172A CN104699641A CN 104699641 A CN104699641 A CN 104699641A CN 201510123172 A CN201510123172 A CN 201510123172A CN 104699641 A CN104699641 A CN 104699641A
- Authority
- CN
- China
- Prior art keywords
- edma
- read
- request
- write
- dsp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bus Control (AREA)
Abstract
The invention discloses an EDMA (enhanced direct memory access) controller concurrent control method in a multinuclear DSP (digital signal processor) system, and belongs to the field of digital signal processing. The method specifically includes that an EDMA request response channel is arranged in each DSP processing unit in the multinuclear DSP system, and a corresponding EDMA request processing channel is arranged outside each DSP processing unit; the EDMA request response channel is connected with the EDMA request processing channel through a read-write request separated double-bus; the EDMA request processing channel is connected to a bus arbitration system through a read-write request separated double-bus; a read-write request separates transmitted request parameters into a read operation request and a write operation request via a register block in the EDMA request processing channel, and the read operation request and the write operation request enter a read request processing logic unit and a write request processing logic unit respectively and enter the bus arbitration system via a logic circuit. The EDMA controller concurrent control method has the advantages that read-write operation is separated, request processing procedure concurrency is achieved through read-write control logic, and the structural basis is provided for implementation of assembly line type operation.
Description
Technical field
The present invention discloses the method for a kind of EDMA controller parallel control, belongs to digital processing field; The specifically method of EDMA controller parallel control in a kind of multi-nuclear DSP system.
Background technology
Along with the development of Digital Signal Processing, the attainable function more sophisticated of DSP, performance is also more and more higher, has become the part that multi-media processing and radio art cannot or lack.The continuous increase of quantity of information, the difficult problem that DSP is faced also grows with each passing day, and mononuclear structure can not satisfy the demands gradually.And DSP performance generally can not realize by promoting clock frequency, the power dissipation overhead of dsp chip will be made like this to become very large, and the benefit that even improving performance brings cannot offset the harm that power consumption increase brings.Development multi-nuclear DSP system becomes trend, and for strengthening the degree of parallelism of chip, the direction of development mainly concentrates on chip multi-core configuration aspects, but the method be not shaped at present solves the problem of multi-nuclear DSP system parallel control.The invention provides the method for EDMA controller parallel control in a kind of multi-nuclear DSP system, arrange multi-nuclear DSP system to transmit data, by the mode of function and resources duplication, each DSP core has identical request response and treatment channel, after process, request mails to object space through bus, when realizing single request parallel transmission control, add data buffering module, achieve the stream line operation of read-write requests process.Being separated read-write operation, by Read-write Catrol logic, having achieved the parallel of request processing procedure, simultaneously for realizing the architecture basics that pipeline operations provides.
EDMA, Enhanced Direct Memory Access, enhancement mode direct memory access, it is the important technology for fast data exchange in digital signal processor DSP, there is the ability of the backstage bulk data transfer independent of CPU, the requirement of scan picture high speed data transmission can be met.The transfer efficiency of view data can not only be improved by control EDMA flexibly, and can give full play to: the high speed performance of DSP.The EDMA data transmission initiated has non-synchronized manner: when needing transmission, the corresponding positions that CPU arranges ESR register is 1, thus trigger the generation of an EDMA event, channel parameters corresponding to event is sent to address hardware and completes corresponding process, and the real-time Data Transmission of this non-synchronized manner is without the need to setting EER register.Also have event triggered fashion EDMA data transmission and the method for synchronization: the event that peripheral hardware sends over preserved by ER register, once the corresponding positions that CPU arranges EER register is after 1, event in ER just can submit to event code device, and causes the address that sends to of relevant transformation parameter to produce hardware further; If the position corresponding to certain event in EER does not put 1, then the event in ER register will retain, once put 1, trigger the transmission of EDMA, and this characteristic can be applied to EDMA transmission.
Summary of the invention
The present invention is directed to the method be not shaped at present and solve multi-nuclear DSP system parallel control, strengthen the problem of the degree of parallelism of chip, the method of EDMA controller parallel control in a kind of multi-nuclear DSP system is provided, when realizing single request parallel transmission control, add data buffering module, achieve the stream line operation of read-write requests process.Being separated read-write operation, by Read-write Catrol logic, having achieved the parallel of request processing procedure, simultaneously for realizing the architecture basics that pipeline operations provides.
The concrete scheme that the present invention proposes is:
EDMA controller concurrency control method in a kind of multi-nuclear DSP system, concrete steps are:
EDMA is set in each DSP processing unit in multi-nuclear DSP system and asks response channel, corresponding EDMA is set outside each DSP processing unit and asks treatment channel; EDMA asks response channel to connect EDMA by the dual bus that read-write requests is separated and asks treatment channel, and the dual bus that EDMA asks treatment channel to be separated by read-write requests is connected to bus arbitration system;
Read-write requests is asked to enter EDMA after response channel response through EDMA and is asked treatment channel, ask the Parasites Fauna in treatment channel that the required parameter of transmission is separated into read operation request and write operation requests by EDMA, enter read request processing logic unit and write request processing logic unit respectively, enter bus arbitration system by logical circuit; When the bus free that read-write requests is corresponding, corresponding read write command will be sent, send confirmation signal to Parasites Fauna, to complete the amendment of respective request parameter in Parasites Fauna simultaneously.
Described EDMA asks to be provided with data buffering processing unit in treatment channel, is responsible for buffer memory and the extraction of the read-write requests data in read request processing logic unit and write request processing logic unit.
When read operation request constantly sends to bus arbitration system, bus arbitration system returns read operation data to read request processing logic unit, read request processing logic unit constantly sends data in data buffering processing unit, if data wherein meet the transmission requirement of write operation requests, then read-write operation request is concurrent.
Usefulness of the present invention is: present invention employs the mode that stratification is parallel, while realizing internuclear parallel work-flow, adds the parallel work-flow that request is inner, and effectively adopts pipeline organization, thus significantly promote the data rate of chip.Be specially each DSP core and distribute EDMA passage independent of each other, respond while achieving multiple core request, when the dual-bus structure of the device resource difference that their are accessed, use, it is concurrent that EDMA not only can realize read-write in single passage, also control parallel work-flow between different IPs, the read-write that request treatment channel realizes transmission request by separation read write order is concurrent, process while realizing multiple transmission request.In addition the present invention is by increasing data buffering, the data returned by read operation are kept in, as long as source device is not in a hurry and data buffering is non-full, read operation controls constantly to send read operation and return data, and write operation simultaneously controls from data buffering sense data, to send together with write order.
Accompanying drawing explanation
The internuclear parallel transmission of Fig. 1 multi-core DSP controls schematic diagram;
Fig. 2 EDMA asks parallel transmission to control schematic diagram.
Embodiment
By reference to the accompanying drawings, the present invention will be further described.
For 4 core dsp systems, DSP1 access memory equipment, DSP4 accesses External memory equipment.EDMA is set in each DSP processing unit in 4 core dsp systems and asks response channel, corresponding EDMA is set outside each DSP processing unit and asks treatment channel; EDMA asks response channel to connect EDMA by the dual bus that read-write requests is separated and asks treatment channel, and the dual bus that EDMA asks treatment channel to be separated by read-write requests is connected to bus arbitration system;
When two requests arrive simultaneously, they access different DSP spaces, and use different EDMA passages, enter different bus arbitration system;
Read-write requests is asked to enter EDMA after response channel response through EDMA and is asked treatment channel, ask Parasites Fauna R1 and R2 in treatment channel that the required parameter of transmission is separated into read operation request and write operation requests by EDMA, enter read request processing logic unit and write request processing logic unit respectively, enter bus arbitration system by logical circuit;
EDMA asks to be provided with data buffering processing unit in treatment channel, is responsible for buffer memory and the extraction of the read-write requests data in read request processing logic unit and write request processing logic unit;
When the bus free that read-write requests is corresponding, corresponding read write command will be sent, send confirmation signal to Parasites Fauna, to complete the amendment of respective request parameter in Parasites Fauna simultaneously; When read operation request constantly sends to bus arbitration system, bus arbitration system returns read operation data to read request processing logic unit, read request processing logic unit constantly sends data in data buffering processing unit, if data wherein meet the transmission requirement of write operation requests, then read-write operation request is concurrent.
Above-mentioned read-write requests is by adopting pipelined operation, and data transmission is approximately the twice of serial transmission.If by amendment host-host protocol, equipment bit wide is expanded to 128, speed will reach 8 times of common 32 bit serial transmission.
The beat number of n data can be transmitted, in table 1 referring to during parallel transmission.
Claims (3)
1. an EDMA controller concurrency control method in multi-nuclear DSP system, is characterized in that concrete steps are:
EDMA is set in each DSP processing unit in multi-nuclear DSP system and asks response channel, corresponding EDMA is set outside each DSP processing unit and asks treatment channel; EDMA asks response channel to connect EDMA by the dual bus that read-write requests is separated and asks treatment channel, and the dual bus that EDMA asks treatment channel to be separated by read-write requests is connected to bus arbitration system;
Read-write requests is asked to enter EDMA after response channel response through EDMA and is asked treatment channel, ask the Parasites Fauna in treatment channel that the required parameter of transmission is separated into read operation request and write operation requests by EDMA, enter read request processing logic unit and write request processing logic unit respectively, enter bus arbitration system by logical circuit; When the bus free that read-write requests is corresponding, corresponding read write command will be sent, send confirmation signal to Parasites Fauna, to complete the amendment of respective request parameter in Parasites Fauna simultaneously.
2. the method for EDMA controller parallel control in a kind of multi-nuclear DSP system according to claim 1, it is characterized in that described EDMA asks to be provided with data buffering processing unit in treatment channel, be responsible for buffer memory and the extraction of the read-write requests data in read request processing logic unit and write request processing logic unit.
3. the method for EDMA controller parallel control in a kind of multi-nuclear DSP system according to claim 2, it is characterized in that when read operation request constantly sends to bus arbitration system, bus arbitration system returns read operation data to read request processing logic unit, read request processing logic unit constantly sends data in data buffering processing unit, if data wherein meet the transmission requirement of write operation requests, then read-write operation request is concurrent.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510123172.2A CN104699641A (en) | 2015-03-20 | 2015-03-20 | EDMA (enhanced direct memory access) controller concurrent control method in multinuclear DSP (digital signal processor) system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510123172.2A CN104699641A (en) | 2015-03-20 | 2015-03-20 | EDMA (enhanced direct memory access) controller concurrent control method in multinuclear DSP (digital signal processor) system |
Publications (1)
Publication Number | Publication Date |
---|---|
CN104699641A true CN104699641A (en) | 2015-06-10 |
Family
ID=53346787
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510123172.2A Pending CN104699641A (en) | 2015-03-20 | 2015-03-20 | EDMA (enhanced direct memory access) controller concurrent control method in multinuclear DSP (digital signal processor) system |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN104699641A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105260331A (en) * | 2015-10-09 | 2016-01-20 | 天津国芯科技有限公司 | Dual-bus memory controller |
CN105354012A (en) * | 2015-12-09 | 2016-02-24 | 浪潮电子信息产业股份有限公司 | EDMA controller parallel control method in multi-core DSP system |
CN105487991A (en) * | 2015-12-18 | 2016-04-13 | 广州慧睿思通信息科技有限公司 | Method for sharing single EDMA (Enhanced Direct Memory Access) channel by multiple cores |
CN105843771A (en) * | 2016-04-11 | 2016-08-10 | 浪潮电子信息产业股份有限公司 | Method for communication among EDMA (enhanced direct memory access) devices with different bandwidths in multi-core DSP (digital signal processor) |
CN107092778A (en) * | 2017-03-30 | 2017-08-25 | 江苏骏龙光电科技股份有限公司 | A kind of optical fiber measurement parallel calculating method based on multi-core CPU |
CN108121685A (en) * | 2017-08-07 | 2018-06-05 | 鸿秦(北京)科技有限公司 | A kind of embedded multi-core cpu firmware operation method |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6925641B1 (en) * | 2000-02-04 | 2005-08-02 | Xronix Communications, Inc. | Real time DSP load management system |
CN102567256A (en) * | 2011-12-16 | 2012-07-11 | 龙芯中科技术有限公司 | Processor system, as well as multi-channel memory copying DMA accelerator and method thereof |
-
2015
- 2015-03-20 CN CN201510123172.2A patent/CN104699641A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6925641B1 (en) * | 2000-02-04 | 2005-08-02 | Xronix Communications, Inc. | Real time DSP load management system |
CN102567256A (en) * | 2011-12-16 | 2012-07-11 | 龙芯中科技术有限公司 | Processor system, as well as multi-channel memory copying DMA accelerator and method thereof |
Non-Patent Citations (1)
Title |
---|
张永照: ""X-QDSP中EDMA控制器的设计与验证"", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105260331A (en) * | 2015-10-09 | 2016-01-20 | 天津国芯科技有限公司 | Dual-bus memory controller |
CN105260331B (en) * | 2015-10-09 | 2018-08-28 | 天津国芯科技有限公司 | A kind of dual bus Memory Controller Hub |
CN105354012A (en) * | 2015-12-09 | 2016-02-24 | 浪潮电子信息产业股份有限公司 | EDMA controller parallel control method in multi-core DSP system |
CN105487991A (en) * | 2015-12-18 | 2016-04-13 | 广州慧睿思通信息科技有限公司 | Method for sharing single EDMA (Enhanced Direct Memory Access) channel by multiple cores |
CN105487991B (en) * | 2015-12-18 | 2018-04-06 | 广州慧睿思通信息科技有限公司 | A kind of method that multinuclear shares single EDMA passages |
CN105843771A (en) * | 2016-04-11 | 2016-08-10 | 浪潮电子信息产业股份有限公司 | Method for communication among EDMA (enhanced direct memory access) devices with different bandwidths in multi-core DSP (digital signal processor) |
WO2017177704A1 (en) * | 2016-04-11 | 2017-10-19 | 浪潮电子信息产业股份有限公司 | Method for communication between edma devices having different bandwidths in multi-core dsp |
CN107092778A (en) * | 2017-03-30 | 2017-08-25 | 江苏骏龙光电科技股份有限公司 | A kind of optical fiber measurement parallel calculating method based on multi-core CPU |
CN108121685A (en) * | 2017-08-07 | 2018-06-05 | 鸿秦(北京)科技有限公司 | A kind of embedded multi-core cpu firmware operation method |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104699641A (en) | EDMA (enhanced direct memory access) controller concurrent control method in multinuclear DSP (digital signal processor) system | |
CN110741356B (en) | Relay coherent memory management in multiprocessor systems | |
US5313594A (en) | Methods and apparatus for data transfer between source and destination modules using a ready signal | |
US8190803B2 (en) | Hierarchical bus structure and memory access protocol for multiprocessor systems | |
US8661199B2 (en) | Efficient level two memory banking to improve performance for multiple source traffic and enable deeper pipelining of accesses by reducing bank stalls | |
WO2021207919A1 (en) | Controller, storage device access system, electronic device and data transmission method | |
US8046505B2 (en) | Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features | |
CN103744644B (en) | The four core processor systems built using four nuclear structures and method for interchanging data | |
US20040177184A1 (en) | Computer architecture and system for efficient management of bi-directional bus | |
WO2016078307A1 (en) | Configurable on-chip interconnection system and method and apparatus for implementing same, and storage medium | |
JP2013025792A (en) | Flexible flash command | |
CN106776458B (en) | Communication device and communication method between DSPs (digital Signal processors) based on FPGA (field programmable Gate array) and HPI (high Performance Integrated interface) | |
CN103207846A (en) | Memory controller and method thereof | |
CN106844263B (en) | Configurable multiprocessor-based computer system and implementation method | |
CN108256643A (en) | A kind of neural network computing device and method based on HMC | |
JP2013025794A (en) | Effective utilization of flash interface | |
CN108234147B (en) | DMA broadcast data transmission method based on host counting in GPDSP | |
CN104035896B (en) | Off-chip accelerator applicable to fusion memory of 2.5D (2.5 dimensional) multi-core system | |
WO2009009133A2 (en) | Dual bus system and method | |
CN117435251A (en) | Post quantum cryptography algorithm processor and system on chip thereof | |
CN112527522B (en) | Partition message subscribing and publishing method based on two-stage data pool | |
CN115328832A (en) | Data scheduling system and method based on PCIE DMA | |
CN204496486U (en) | Expanded function unit and computing equipment expanding system | |
CN210038775U (en) | System on chip | |
CN108062282B (en) | DMA data merging transmission method in GPDSP |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150610 |