CN100414524C - Method for controlling data transmission between two different speed buses - Google Patents
Method for controlling data transmission between two different speed buses Download PDFInfo
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- CN100414524C CN100414524C CNB2005100864461A CN200510086446A CN100414524C CN 100414524 C CN100414524 C CN 100414524C CN B2005100864461 A CNB2005100864461 A CN B2005100864461A CN 200510086446 A CN200510086446 A CN 200510086446A CN 100414524 C CN100414524 C CN 100414524C
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Abstract
This invention discloses a control method for data transfer between two main lines with different transfer speed. It includes the following aspects: read FIFO and write FIFO for data transfer in different direction; write buffer 0 and 1 for collecting data from the write FIFO; a read buffer. The advantages of this invention are as follows: the control logic of read and write is brief; less write depth could show perfect efficiency; the write data stay in write FIFO for a short time so that the write operation can be generated earlier; data transfer can be managed with a flow style, etc.
Description
Technical field
The present invention relates to the method that data transmit between control bus, the method that data transmit between two kinds of buses with different speeds of particularly a kind of control.
Background technology
Usually use a kind of chip of bridge that cries that different buses is isolated mutually in the computer system.When the equipment on the bus will be asked resource on other bus, be responsible for the operation on this bus is converted to operation on its request resource place bus by bridge.Because bus can only a limited number of equipment of carry on every bus in physics and structural restriction.Therefore a lot of computer systems structurally use many buses of isolating mutually that the expansion of systemic-function is provided.These buses of isolating mutually can be used same protocol, also can use different agreement.Protocol conversion between different bus is responsible for finishing by the bridge that is used for isolating these buses.Equipment in the conversion through passing a bridge, bus just can with the mutual swap data of the equipment on other bus.Usually, bridge is transparent for the equipment on the bus that is attached thereto.Equipment on a bus, bridge also are the equipment on this bus.Equipment on the bus by send to bridge read-write requests come with other bus that links to each other with bridge on devices exchange data.
At present, the method that data transmit between two kinds of buses with different speeds of known control, such as document 1:Low costdata streaming mechanism (U.S. Patent number: 6,460,108) disclosed method in, the major programme of this method is: in writing transmission, the interface of initiator's bus writes FIFO (First Input First Output with data, FIFO is the formation of organizing in first in first out mode, hereinafter to be referred as FIFO), the target side bus interface judges to write whether have enough data to initiate one time write operation among the FIFO on the target side bus by the control signal of writing FIFO, has enough data just to initiate write operation in the target side bus among the FIFO if write; In reading transmission, initiator's bus interface is after the target side bus interface is submitted request to, the target side bus interface is initiated operation and the data that receive is write study in FIFO on the target side bus, initiator's bus interface began return data on initiator's bus when data length reached threshold value in reading FIFO, when read FIFO full or when on initiator's bus, having returned enough data the target side bus interface terminate in read operation on the target side bus.
But, the deficiency of method is in the document 1: the steering logic of reading FIFO and writing FIFO and need more complicated shows the length of the valid data among the FIFO, write data need stop the long time in writing FIFO, need the FIFO that writes of the big degree of depth in order to improve the efficient of initiator's bus when writing transmission.Method when the width of initiator's bus and target side bus is inconsistent in the document 1 is just inapplicable, and document 1 does not mention that in reading transport process the what state that stops read operation as target side bus interface initiator when writing data in reading FIFO is handled.
Summary of the invention
The objective of the invention is to overcome the deficiency of known technology, the method that data transmit between two kinds of buses with different speeds of a kind of control is provided, this method is handled read-write requests between bus apparatus by the mode of flowing water, can finish visit quickly and efficiently.
In order to achieve the above object, the technical scheme taked of the present invention is as follows:
The method that data transmit between two kinds of buses with different speeds of a kind of control, wherein second bus has than wideer data width of first bus and the frequency of Geng Gao; For the write data process, comprise the steps:
A) interface of bridge device first bus side finds that the equipment on this first bus will send the data to second bus;
B) bridge device receives the write request of equipment on first bus and address of being write and data is write FIFO successively;
C) as long as interface of bridge device second bus side find is write the FIFO non-NULL and just will write data among the FIFO and read in first compose buffer and write completely or read in last data that first bus apparatus writes until first compose buffer;
D) interface of bridge device second bus side is the data in running through first compose buffer on second bus of ready data read in first compose buffer, the interface with bridge device second bus side when the data read of first compose buffer is on second bus continue to write data among the FIFO write that data in first compose buffer in second compose buffer have all transmitted on second bus or second compose buffer completely or last data of writing of first bus, one side apparatus enter second compose buffer;
E) do you judge that second compose buffer is ready to? (second compose buffer is ready to be meant: second compose buffer last data full or that first bus apparatus writes enter second compose buffer) is if carry out next step f); If not, continuation reading of data from write FIFO is ready to until second compose buffer in second compose buffer, then execution in step f);
F) position of exchange second compose buffer and first compose buffer;
G) repeating step f)-e) last write data up to first bus apparatus is sent on second bus;
For reading data course, comprise the steps:
1) interface of bridge device first bus side finds that equipment on first bus will ask the data of second bus, one side;
2) bridge device receives the read request of equipment on first bus and address of being asked and corresponding Data Identification is write FIFO;
3) read request that will read from write FIFO of the interface of bridge device second bus side is converted to the read request on second bus;
4) when first data on second bus are returned, if the address of the address of the first bus side equipment read request and the request that sends on second bus does not line up, then the interface of second bus side writes direct the data of the first bus side device request earlier and reads FIFO;
5) interface of second bus side continue request on second bus subsequently data and the data that obtain are put into read buffer zone buffer zone equipment full or first bus side has been read last data of its expectation or the data volume of having read has reached threshold value until reading;
6) when reading buffer zone when full, the request that suspends on second bus reaches half-full up to the item number of reading the buffer zone free time;
The data importing that to read in the buffer zone when 7) interface of second bus side has the data of the data and first bus side also not read last data of its expectation in reading buffer zone is read among the FIFO;
8) when the equipment of first bus side during, if the interface of first bus side sees that reading the FIFO non-NULL just will read equipment that data among the FIFO return to the request first bus side request msg and become up to reading FIFO that sky or equipment are read last data of its expectation or the data returned have reached threshold value in request msg;
9) repeating step 5)-8) data length having read last data of its expectation or returned to equipment up to the equipment of first bus side reached threshold value.
In technique scheme, described first bus refers to that pci bus, lpc bus or other take over party do not know to transmit the bus of data length when address cycle, and described second bus refers to the internal bus that DDR bus or bridge sheet device interior link to each other with Memory Controller Hub.
In technique scheme, pci bus is the bus of 32 bit wide 33MHZ usually, and DDR is the above frequencies of 64 bit wide 100MHZ.
In technique scheme, the length of described each compose buffer is set as the cache line length of bridge device system of living in or the burst length that the DDR internal memory uses.
In technique scheme, each byte of described each compose buffer all has the position choosing of oneself to show whether the data of this byte are effective.
In technique scheme, the address of the lowest byte of described each compose buffer is with the cache line of bridge device system of living in alignment.
In technique scheme, each of the described FIFO of writing comprises data, position choosing, flag, and this flag identifies the type of this item number certificate, as write address, read address, common write data or last write data of once writing etc.; Wherein the width of data is identical with the data width of first bus, and the width of position choosing and the position of first bus select width identical.
In technique scheme, described first bus refers to that pci bus, lpc bus or other take over party do not know to transmit the bus of data length when address cycle.
In technique scheme, described second bus refers to the internal bus that DDR bus or bridge chip inside link to each other with Memory Controller Hub.
In technique scheme, described threshold value is made as the degree of depth of reading FIFO usually or once allows bus one side apparatus to transmit the maximal value of data length.
In technique scheme, described " equipment of first bus side has been read last data of its expectation " be meant on the pci bus equipment in the end data during the cycle bridge device effective.
In technique scheme, each comprises the described FIFO of reading data and identifies whether these data are the data that reach threshold value.
Compared with prior art, the invention has the advantages that:
1) steering logic of reading and writing FIFO is simple relatively;
2) write the FIFO degree of depth and just can on initiator's bus, obtain desirable efficient with less;
3) time of in writing FIFO, stopping of write data short, can on the target side bus, initiate write operation as soon as possible;
4) handling read data ground in the mode of flowing water transmits;
5) pass through target side bus interface ground read-write buffer zone processing initiator's bus and target side highway width situation inconsistently.
Description of drawings
Fig. 1 represents that an embodiment is used for connecting the logical organization of data transferring method of the bridge chip control PCI device access DDR internal memory of pci bus and DDR bus.
Embodiment
PCI (Peripheral Components Interconnect) bus is the most general the most common peripheral bus in the current computer system.The bridge that links to each other with pci bus on the pci bus simultaneously as a master (initiator) and a target (response side) on the pci bus.On pci bus, the typical DMA working method of equipment is to pass through the PCI master interface of bridge to the equipment transmitting control commands by processor.Equipment is sent to the appointed area of internal memory according to the order of receiving with the PCI TARGET interface of data by bridge or from the appointed area reading of data of internal memory.Equipment sends new order by the interrupt notification processor after the data transmission is finished.
Data on the pci bus transmit carries out in the burst mode.Before last data of a transfer operation were transmitted, target was the length of not knowing current transmission.The rambus that the bridge chip of existing connection pci bus and rambus (for example 440BX chip of Intel) is connected is the sdram memory bus normally.Along with the rambus standard of main flow changes the DDR standard into by the SDRAM standard, use the bridge chip of original connection PCI and SDRAM to fade away, the bridge sheet that the thing followed directly connects pci bus and rambus will change the bridge chip that is connected pci bus and DDR bus into.Different with the dirigibility of sdram memory on burst length, the DDR internal memory can only use the burst operation of regular length.Because the variation of rambus behavior, the mechanism of control PCI device access DDR internal memory need be formulated according to the characteristics of DDR internal memory and could obtain perfect performance.
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail:
The data of utilizing method provided by the invention to solve PCI device access DDR internal memory transmit, and the read-write requests of handling PCI equipment by the mode of flowing water makes PCI equipment can finish visit to the DDR internal memory quickly and efficiently.
Fig. 1 is the structure of logic of the data transfer mechanism of one embodiment of the invention bridge chip control PCI device access DDR internal memory of being used for connecting pci bus and DDR bus, provided the present invention among the figure and has been used for handling main storage that PCI equipment read/write memory resource relates to and the relation between the control module.Be description below to the concrete function of these modules.
Present embodiment provides a kind of method of the PCI of control device access storage resources, and needed hardware configuration comprises: the PCI TARGET interface logic that links to each other with pci bus, be used to receive the FIFO that writes of write request that PCI equipment submits to and write data and read request, be used for the FIFO that reads that read data with the PCI device request returns, go forward to be used for from writing the compose buffer that FIFO collects data write data being submitted to the internal bus that links to each other with Memory Controller Hub, be used for the data that Memory Controller Hub returns are write the buffer zone of reading of studying in translation data width before the FIFO and carrying out Flow Control, according to write read/write command that FIFO sends to internal bus that Memory Controller Hub links to each other on initiate read/write operation internal bus MASTER interface.
Each that write FIFO comprises C/BE and two control bits of 32 4 of data.This is address or data for a bit-identify in the control bit, and whether another one identifies this is last data of a write operation.
Whether each that read FIFO comprises data and a sign current data of 32 is the flag of last data.
The request that PCI TARGET interface logic is responsible for monitoring equipment on the pci bus, and corresponding response is made in these requests according to the PCI standard:
The process of processing write requests:
When PCI TARGET interface logic received the write request of PCI equipment, PCI TARGET interface checked that at first writing the FIFO control signal writes FIFO with judgement and whether have enough spaces (write FIFO and have two rooms at least) to receive write address and at least one write data.Do not have enough spaces if write FIFO when the write request of PCI equipment arrives, PCI TARGET interface will be carried out the retry operation in the PCI agreement.When writing FIFO and have enough space to receive new PCI write operation, PCI TARGET interface writes the address of write request and data among the FIFO up to having received last write data that PCI equipment submits to or having write FIFO full successively.Appearing at write data on the pci bus when writing also surplus last room of FIFO is written into as last data of a write operation and writes FIFO.When PCI TARGET interface had begun to receive write data and write FIFO only to remain last room, PCI TARGET interface was carried out the disconnect operation in the PCI agreement.
Handle the process of read request:
PCI TARGET interface need noted the read request that this has been submitted to simultaneously in interface inside when writing FIFO submission read request.The record that is used to write down this read request of having submitted to comprise 32 read whether effectively flag of address and record.When PCI TARGET interface logic receives the read request of PCI equipment, PCI TARGET interface check read record and the control signal of writing FIFO.If the read record flag is invalid and write FIFO less than the just current request of record and write read request among the FIFO and carry out the retry operation of PCI agreement in read record of, PCI TARGET interface.If the read record flag effectively and in the address of read request and the read record be not inconsistent or to write FIFO full, PCI TARGET interface is carried out the retry operation of PCI agreement.When read record flag conforming to effectively and in the address of read request and the read record, the non-spacing wave of the FIFO that continue such as PCI TARGET interface.PCI TARGET interface begins to return read data on pci bus when reading the FIFO non-NULL.If return data in the time of the initial latent period permission that PCI TARGET interface can not be in the PCI agreement, PCI TARGET interface is carried out the retry operation.Whenever return a read data, corresponding increase is just done in the address in the read record.When beginning to return read data, read FIFO in case become empty, PCI TARGET interface is just carried out the disconnect operation.The current data of returning of control bit sign of having read last data of its request or having read FIFO when the equipment of request msg be internal bus MASTER interface this time return last data the time, the significance bit of PCI TARGET interface clear read record.When the equipment of request msg had been read last data of its request, PCI TARGET interface was to internal bus MASTER interface and read signal that stops read operation of FIFO transmission.
Internal bus MASTER interface logic is responsible for and will be converted to read/write operation on the internal bus by writing read/write command that FIFO sends, and be responsible for writing among the FIFO the data importing compose buffer and with the data importing of returning on the internal bus read buffer zone and control write FIFO read enable and read writing of FIFO and enable.
It is as follows that internal bus MASTER interface is handled the flow process of writing transmission:
Compose buffer is divided into two storage areas that size is identical.The length of data that each storage area is preserved is determined by the maximum burst length that the DDR controller adopts.Narration for convenience claims that here one of them storage area is a compose buffer 0, and another storage area is a compose buffer 1.
A) after internal bus MASTER interface is seen effective write order from the read port of writing FIFO, internal bus MASTER interface is written into the address interface from write FIFO address counter begins to load the process of compose buffer subsequently;
B) after write FIFO and loaded the address, internal bus MASTER interface as long as find write the FIFO non-NULL just will write data among the FIFO read in the compose buffer 0 until compose buffer 0 write completely or reading device in last data of once writing in the transmission;
C) finish the loading of compose buffer 0 after, internal bus MASTER interface is the data in running through compose buffer 0 to the internal bus of ready data read in the compose buffer 0, internal bus MASTER interface when the data read of compose buffer 0 is to internal bus is continued to write new data that arrive among the FIFO write that data in compose buffer 0 in the compose buffer 1 have all transmitted on internal bus or compose buffer 1 completely or equipment last data of this time writing transmission write compose buffer 1;
D) if compose buffer 1 also is not ready for (compose buffer 1 is ready to be meant: compose buffer 1 last data full or that bus 1 equipment writes enter compose buffer 1), continuation reading of data from write FIFO is ready to until compose buffer 1 in compose buffer 1;
E) position of exchange compose buffer 1 and compose buffer 0;
F) e d repetition c))) writing last write data of transmission up to this is sent on the internal bus.
It is as follows that internal bus MASTER interface is handled the flow process of reading to transmit:
A) after internal bus MASTER interface is seen effective read command from the read port of writing FIFO, internal bus MASTER interface is written into the address interface from write FIFO address counter begins to send read request at internal bus subsequently;
B) when first data on the internal bus are returned, if the address of the address of PCI equipment read request and the request that sends on internal bus does not line up, the data that internal bus MASTER interface does not line up the address are earlier write direct and are read FIFO;
C) internal bus MASTER interface continue on internal bus request subsequently data and dash until read buffer zone full or receive the stop signal of PCI TARGET interface transmission or the data length that receive reached threshold value to reading slow district the data buffering that returns;
D) when reading buffer zone when full, the request that suspends on internal bus reaches half-full up to the item number of reading the buffer zone free time;
To read data in the buffer zone when e) internal bus MASTER interface has data and PCI TARGET interface not to send stop signal in reading buffer zone reads in and reads among the FIFO;
F) e d repetition c))) up to receiving that stop signal that PCI TARGET interface sends or the data length of having read have reached threshold value.
The threshold value is here determined according to the maximum length of reading the degree of depth of FIFO or once transmitting data.
Because it is fast that read data returns on internal bus speed is write the speed of studying in FIFO than internal bus MASTER interface with read data, internal bus MASTER interface need use to be read buffer zone the data of returning on the internal bus is cushioned earlier.Can enter under the prerequisite of reading FIFO and to improve the efficient of internal bus MASTER interface on internal bus not influencing read data like this.
The stop signal that PCI TARGET interface sends need be given and be read FIFO and internal bus MASTER interface.Reading FIFO need empty when receiving stop signal and read FIFO (all address pointer playback).Internal bus MASTER interface is received to need to stop after the stop signal data are write and is studied in FIFO, cancels the operation on internal bus and empty and read buffer zone.
Present embodiment has solved a following difficult problem: finish quickly and efficiently the transmission of PCI equipment write data, efficiently solve the problem of returning of PCI equipment read data, under the typical application condition (pci bus of 32 33MHZ, 64 DDR buses more than the 100MHZ) reduced writing the demand of FIFO capacity.Because PCI agreement, bridge sheet can't be known equipment and will transmit how many data on earth in this transmits before transmitting last data.In writing transmission, if by the time the bridge sheet has received equipment and has once write the request that the data that will write transmission after all data of transmission again are converted to other interface, FIFO is full and write request that can not handle new arrival influence the bandwidth that PCI equipment obtains when carrying out write operation thereby the bridge sheet is easy to, and the bridge sheet for the higher bandwidth of acquisition in writing transmission often need the use capacity bigger write FIFO.
In the present embodiment, the main effect of writing FIFO is not to transmit once writing of PCI equipment to store write data before finishing but allow write data flow to bridge sheet clock internal territory from the clock zone of PCI.The read port from writing FIFO that internal bus MASTER interface does not stop is collected the write data that newly enters, and just initiates a write operation in case collect the data of neat specified length on internal bus.In order to accelerate the collection of write data, internal bus MASTER interface continues to collect the data that write operation needs on the next internal bus when carrying out write operation.Under the typical application condition, internal bus MASTER interface is collected the speed of the speed of write data greater than PCI equipment submission write data, internal bus MASTER interface is collected the data of uneven next write operation in the process of carrying out write operation, internal bus MASTER interface needs to continue uncompleted collection work before the next write operation of beginning.Like this write data submitted to of PCI equipment only in writing FIFO, do brief stay just can be processed.And the each write operation of internal bus MASTER interface all has enough length to make full use of the bandwidth of Memory Controller Hub.Owing to receiving that read request back axle sheet do not know that the equipment expectation obtains data how long, the read request of PCI equipment is difficult request of efficiently handling in reading to transmit.In the present embodiment, the read request of PCI equipment is used as the signal that starts the reading streamline.In case internal bus MASTER interface sees that this signal just begins ceaselessly to obtain last data of its expectation or the data length that returns on the bus has internally reached setting at request read data on the internal bus up to PCI equipment.Use in this patent and read buffer zone and enter the buffering and the utilization of reading before the FIFO as read data on the internal bus and read the Flow Control that buffer zone carries out read operation on the internal bus.Can begin to return first read data and return remaining read data continuously before the initial latent period end 16 of PCI agreement fully in the treatment mechanism that this patent under the typical application environment uses.
In the realization of adopting this patent on the fpga chip Altera Straix II EP2S60 bridging chip between pci bus and the DDR bus.The Wishbone bus interface that the bridging chip internal bus adopts the OpenCores tissue to be issued.
Claims (8)
1. the method that data transmit between two kinds of buses with different speeds of a control, wherein second bus has than wideer data width of first bus and the frequency of Geng Gao; For the write data process, comprise the steps:
A) interface of bridge device first bus side finds that the equipment on this first bus will send the data to second bus;
B) bridge device receives the write request of equipment on first bus and address of being write and data is write FIFO successively;
C) as long as interface of bridge device second bus side find is write the FIFO non-NULL and just will write data among the FIFO and read in first compose buffer and write completely or read in last data that first bus apparatus writes until first compose buffer;
D) interface of bridge device second bus side is with the data in running through first compose buffer on second bus of ready data read in first compose buffer, with when the data read of first compose buffer is on second bus, the interface of bridge device second bus side continue to write data among the FIFO write that data in first compose buffer in second compose buffer have all transmitted on second bus or second compose buffer completely or last data of writing of first bus, one side apparatus enter second compose buffer;
E) judge whether second compose buffer is ready to, if carry out next step f); If not, continuation reading of data from write FIFO is ready to until second compose buffer in second compose buffer, then execution in step f);
F) position of exchange second compose buffer and first compose buffer;
G) repeating step c)-e) last write data up to first bus apparatus is sent on second bus; For reading data course, comprise the steps:
1) interface of bridge device first bus side finds that equipment on first bus will ask the data of second bus, one side;
2) bridge device receives the read request of equipment on first bus and address of being asked and corresponding Data Identification is write FIFO;
3) read request that will read from write FIFO of the interface of bridge device second bus side is converted to the read request on second bus;
4) when first data on second bus are returned, if the address of the address of the first bus side equipment read request and the request that sends on second bus does not line up, then the interface of second bus side writes direct the data of the first bus side device request earlier and reads FIFO;
5) interface of second bus side continue request on second bus subsequently data and the data that obtain are put into read buffer zone buffer zone equipment full or first bus side has been read last data of its expectation or the data volume of having read has reached threshold value until reading;
6) when reading buffer zone when full, the request that suspends on second bus reaches half-full up to the item number of reading the buffer zone free time;
The data importing that to read in the buffer zone when 7) interface of second bus side has the data of the data and first bus side also not read last data of its expectation in reading buffer zone is read among the FIFO;
8) when the equipment of first bus side during, if the interface of first bus side sees that reading the FIFO non-NULL just will read equipment that data among the FIFO return to the request first bus side request msg and become up to reading FIFO that sky or equipment are read last data of its expectation or the data returned have reached threshold value in request msg;
9) repeating step 5)-8) data length having read last data of its expectation or returned to equipment up to the equipment of first bus side reached threshold value.
2. the method that data transmit between two kinds of buses with different speeds of control according to claim 1, it is characterized in that, described first bus is the take over party does not know to transmit data length when address cycle a bus, described first bus is pci bus or lpc bus, and described second bus refers to the internal bus that DDR bus or bridge device inside link to each other with Memory Controller Hub.
3. the method that data transmit between two kinds of buses with different speeds of control according to claim 1, it is characterized in that the length of described first compose buffer and described second compose buffer is set as the cacheline length of bridge device system of living in or the burst length that the DDR internal memory uses.
4. the method that data transmit between two kinds of buses with different speeds of control according to claim 2 is characterized in that, each byte of described first compose buffer and described second compose buffer all has the position choosing of oneself to show whether the data of this byte are effective; The address of the lowest byte of described first compose buffer and described second compose buffer is with the cache line of bridge device system of living in alignment.
5. the method that data transmit between two kinds of buses with different speeds of control according to claim 1, it is characterized in that, each of the described FIFO of writing comprises data, position choosing, flag, last write data that the type that this flag identifies this item number certificate is write address, read address, common write data or once write; Wherein the width of data is identical with the data width of first bus, and the width of position choosing and the position of first bus select width identical.
6. the method that data transmit between two kinds of buses with different speeds of control according to claim 1 is characterized in that, the threshold value in the described step 5) is made as the degree of depth of reading FIFO or once allows first bus, one side apparatus to transmit the maximal value of data length.
7. the method that data transmit between two kinds of buses with different speeds of control according to claim 1 and 2, it is characterized in that, last data that the equipment of described first bus side has been read its expectation be meant on the pci bus equipment in the end data during the cycle bridge device effective.
8. the method that data transmit between two kinds of buses with different speeds of control according to claim 1 is characterized in that, each of the described FIFO of reading comprises data and whether these data of sign are the data that reach threshold value.
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| CNB2005100864461A CN100414524C (en) | 2005-09-20 | 2005-09-20 | Method for controlling data transmission between two different speed buses |
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| CNB2005100864461A CN100414524C (en) | 2005-09-20 | 2005-09-20 | Method for controlling data transmission between two different speed buses |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101441610B (en) * | 2007-11-21 | 2010-09-01 | 中兴通讯股份有限公司 | System and method for implementing data parallel-to-serial conversion seamless output |
| CN101694646B (en) * | 2009-09-30 | 2012-04-18 | 中国科学院计算技术研究所 | Method and system for controlling reading transfer among buses with different speeds |
| CN101882126B (en) * | 2010-07-13 | 2012-01-04 | 中国科学院计算技术研究所 | Device and method for bridging multiple HT (Hyper Transport) buses to single PCIe (Peripheral Component Interface Express) bus |
| CN102103740B (en) * | 2010-12-20 | 2013-01-02 | 福州瑞芯微电子有限公司 | Method and circuit for processing written address and width unaligned image |
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