CN107590085B - A kind of dynamic reconfigurable array data path and its control method with multi-level buffer - Google Patents
A kind of dynamic reconfigurable array data path and its control method with multi-level buffer Download PDFInfo
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Abstract
The invention discloses a kind of dynamic reconfigurable array data paths and its control method with multi-level buffer, the system includes the interface module in the coarseness operators m esh arrays and data path of the multilevel cache system of 4 grades of caching compositions, the reconfigurable control module of multi-level buffer, support multi-level buffer, wherein：Multilevel cache system under the control of configuration code, for complete the data in data path storage, data exchange it is synchronous with data；Multi-level buffer reconfigurable control module completes the mapping control between mesh arrays read-write read-write variable and multi-level buffer address under the control of configuration code；Coarseness operators m esh arrays calculate link used for forming, and under the control of configuration code, read and write variable to it according to the definition of data flow diagram and control.The configurable dynamic reconfigurable array data path and its method with multi-level buffer of the present invention has data sharing degree high, and data tape is roomy, can improve the computational efficiency of assembly line and nonpipeline type.
Description
Technical field
The present invention relates to imbedded reconfigurable system regions, and in particular, to a kind of dynamic with multi-level buffer can weigh
Structure array data access and its control method.
Background technology
Due to including special reconfigurable processing unit, reconfigurable arrays are gone back in the case where obtaining the superiority condition of performance and power consumption
The flexibility of application can be kept, therefore is the idealized model during special field calculates.There are two features for reconfigurable arrays framework：
First, it is made of reconfigurable data access and reconstructing controller on hardware configuration.Reconfigurable data access uses basic operation
The array architecture of unit composition；Second, processor control is flowed and data stream separation.Reconfigurable data access is used to handle data
Stream, and reconstructing controller controls stream to control reconfigurable data access for performing.
Reconfigurable data access includes operator array, memory and interface.Under conditions of array scale is not increased, improve
The method of the performance of reconfigurable data access mainly has the following：The concurrency calculated in first raising data path, uses
Operation grade is parallel and data level carries out data calculating processing parallel.Second improves the hardware utilization of assembly line, reduces data and reads
Idle running in the especially iterative type assembly line of assembly line caused by write delay.
For above performance requirement, main technological means includes at present：Improve the shared journey of memory in data path
Degree so that same memory multiple operators in the same clock cycle is by operator array are read simultaneously, and can be by another operator
Update, this method can effectively improve the concurrency of data, reduce the idle running of assembly line.Second, improve the data band of memory
Width, by improving the working frequency of memory and increasing memory data bit wide so that memory is with data path with frequency, storage
Device data width is equal to the maximum bit wide of data path single treatment.
But there is situations about mutually restricting for the degree of share of memory and data bandwidth.As degree of share increases,
Memory need to have a plurality of address wire and data cable, and internal logical delay is linearly increasing.This can reduce the read-write band of memory
Width can further cause the reduction of the flow work frequency.
In conclusion in the implementation of the present invention, it is found by the applicant that storage system in existing reconfigurable data access
Cannot meet the needs of high shared and high bandwidth simultaneously, so as to limit reconfigurable arrays performance boost.
The content of the invention
It is an object of the present invention to existing problem and shortage for the above-mentioned prior art, proposes a kind of reconfigurable arrays
In have multi-level buffer structure data path, data processing degree of parallelism in reconfigurable data access can be effectively improved and improved
Assembly line execution efficiency.
To achieve the above object, the technical solution adopted by the present invention is：There is multi-level buffer knot in a kind of reconfigurable system
The data path of structure, including multiple coarseness operators m esh arrays：By between arithmetic element (PE) array of isomorphism and they
Interconnection unit composition, interconnected by a network element based on displacement between two adjacent row PE units, Ke Yiling
The various topological structure DFG figures of support living；The multilevel cache system in interface module, data path in data path.
The coarseness operators m esh arrays, by arithmetic element (PE) array of isomorphism and the interconnection unit between them
Composition.It is interconnected, can flexibly be supported each by a network element based on displacement between two adjacent row PE units
Kind topological structure DFG figures.Such array has n (n sizes are from 1 to 4) in data path.
Interface in the data path, for reading data from external memory and the information being sent to multilevel cache system
In.
The multilevel cache system is made of 4 grades of cachings：For completing the storage of the data in data path, data exchange
It is synchronous with data.
Wherein, the multilevel cache system includes：
1st grade of caching：Between the PE units being connected positioned at two, delay for the data in mesh array internal pipelines
It deposits and data exchange, is realized using register.
Level 2 cache memory：Between the mesh arrays being connected, for data in the assembly line of multiple mesh arrays composition
Caching and data exchange, it can also be used to which the caching and data exchange of nonpipeline data between mesh arrays have 2n (n mesh
Array quantity) a read port and 2n write port, it can be realized simultaneously by all mesh array accesses using register file.
3rd level caches：Caching and exchange for data in nonpipeline between mesh arrays have 1 read port and 1
A write port, is realized using dual port RAM.
4th grade of caching：For the data buffer storage of data-interface, and input data is synchronized to the 2nd grade or 3rd level caching,
It reads the output result of the 2nd grade or 3rd level caching and is sent to output interface, realized using FIFO.
Wherein, described two PE units being connected：The PE units of adjacent rows in mesh arrays, and two PE units
There is signal wire connection between having.
Wherein, the assembly line inside the mesh arrays：M (m values are in 1-8) is between row PE units and PE in mesh arrays
Interconnection logic under the control of configurator, m level production lines can be formed.Calculation function at different levels is complete by PE units in assembly line
Into the interconnecting relation of assembly line is completed by the interconnection logic between PE.
Wherein, the assembly line of multiple mesh arrays composition：N (n values are in 1-4) a mesh arrays, in each array
There are m (m values are in 1-8) row PE units, n*m level production lines can be formed, assembly line calculation function at different levels is completed by PE units, mesh
The interconnecting relation of assembly line is completed by the interconnection logic between PE in array, and the interconnection between mesh arrays passes through slow to the 2nd grade
The address deposited, which accesses, completes.
Wherein, the configuration code function of multi-level buffer is：To the 1st grade cache, by reconfigurable arrays PE configuration codes control PE it
Between interconnecting relation, while also complete the 1st grade of buffer control；2nd grade and 3rd level are cached, by buffer control in mesh arrays
Device is controlled, which reads the 2nd grade and 3rd level caching by clock cycle precision according to mesh array configuration codes
It writes；4th grade is cached, is controlled by cache controller in mesh arrays, the controller is according to mesh array configuration codes, by the
The hollow full scale will of FIFO and mesh array operation sequences are written and read operation in 4 grades of cachings.
Wherein, when the reconfigurable control module of the multi-level buffer is to 1 grade of buffer control, the register of access is by configuration code
It is definite, it is remained unchanged in single with postponing；When controlling the 2nd grade of storage, it is necessary to the register of different address be accessed, by reading and writing
Controller completes the control of its accessing operation, and the reading of the 2nd grade of storage and writing all is completed in signal period, and control instruction is write
Enter with readout without waiting for its completion；When controlling 3rd level storage, since read-write can could be completed within multiple cycles, need
To increase reading in its control instruction and write effective mark, to reduce the additional wait generated due to the 2nd grade of storage of read-write
Time；, it is necessary to the sky in respective cache be waited to expire signal, as the starting point of mesh array computations when controlling the 4th grade of storage
And terminal.
The present invention also provides a kind of collocation method of the data path applied to reconfigurable arrays multi-level buffer structure, bags
Include following steps：
Step 1) is by new duty mapping into reconfigurable arrays.
If the new task of step 2) includes non-iterative type pile line operation, if the assembly line is by one mesh gusts
Row perform, then the input data in assembly line and output data are mapped in level 2 cache memory, other intermediate data are mapped to the 1st
In grade caching；If assembly line is made of multiple mesh arrays, by the input data of assembly line, output data and across difference
The data of mesh arrays are mapped to level 2 cache memory, other intermediate data are mapped in the 1st grade of caching.
If the new task of step 3) includes iterative type assembly line, if the assembly line is held by a mesh array
Row, then by assembly line input data, output data and need feedback iteration handle data be mapped in level 2 cache memory, other
Intermediate data is mapped in the 1st grade of caching；If the assembly line is made of multiple mesh arrays, by the input number of assembly line
Level 2 cache memory is mapped to according to, output data, across the data of different mesh arrays and the data of feedback iteration, other intermediate data
It is mapped in the 1st grade of caching.
Advantageous effect：Technical scheme is used for the dynamic reconfigurable array data with multi-level buffer by a kind of
Access and its control method improve the degree of share of memory and the data bandwidth of storage system in reconfigurable arrays operation,
The structure and collocation method of storage system in traditional reconfigurable array are changed, so as to improve the operation of reconfigurable arrays effect
Rate.
Description of the drawings
Attached drawing is used for providing a further understanding of the present invention, and a part for constitution instruction, the reality with the present invention
Example is applied together for explaining the present invention, is not construed as limiting the invention.In the accompanying drawings：
Fig. 1 is the dynamic reconfigurable array data path architecture schematic diagram with multi-level buffer；
Fig. 2 is the data structure in multi-level buffer in data path；
Fig. 3 is the collocation method figure of the data path of reconfigurable arrays multi-level buffer structure.
Specific embodiment
The preferred embodiment of the present invention is illustrated below in conjunction with attached drawing, it should be understood that preferred reality described herein
It applies example to be merely to illustrate and explain the present invention, be not intended to limit the present invention.
As shown in Figure 1, the reconfigurable data access of the present embodiment includes multiple coarseness operators m esh arrays：By isomorphism
Arithmetic element (PE) array and the interconnection unit between them form, and are based on putting by one between two adjacent row PE units
The network element changed is interconnected；Interface in data path：For from external memory read operands and by configuration information
It is sent in multilevel cache system；1 grade of caching in data path：Between the PE units being connected positioned at two, for mesh gusts
Data buffer storage and data exchange in row internal pipeline, are realized using register；Level 2 cache memory in data path：Positioned at phase
Between the mesh arrays of connection, for data buffer storage and data exchange in the assembly line of multiple mesh arrays composition, it can also be used to
The caching and data exchange of nonpipeline data between mesh arrays；3 grades of cachings in data path：For non-between mesh arrays
The caching of data and exchange in assembly line；4 grades of cachings in data path：For the data buffer storage of data-interface, and will input
Data are synchronized in 2 grades or 3 grades cachings.
As shown in Fig. 2, the caching key data structure in reconfigurable arrays data path：Mesh times are stored in 1 grade of caching
Pipeline data in row, there are in the register monopolized in PE for these data.When assembly line is run, each 1 grade of cycle is slow
Data in depositing all are updated；The data exchanged between mesh arrays are stored in level 2 cache memory, these data can be used as occupancy more
The pipeline data of a mesh arrays, the data that can be also operated as nonpipeline.During as pipeline data, each cycle this
A little data are all updated.During as nonpipeline data, after higher level mesh arrays are completed to operate, which is just updated；3 grades
Buffer memory nonpipeline data, therefore the readwrite bandwidth of 3 grades of cachings is less than 2 level production lines.3 level production lines also can be by 2 simultaneously
The data cached monolithic backup of grade.Such case can occur when the flowing water that level 2 cache memory participates in is interrupted；4 grades of caching conducts can weigh
The caching that structure array and external data exchange.After external data inputs reconfigurable arrays, these data store in 4 grades of cachings
And it is switched in level 2 cache memory.And the result of calculation in level 2 cache memory can be read by 4 grades of cachings by external bus.
As shown in figure 3, the collocation method cached in the data path with multi-level buffer：For assembly line executive mode,
The data of assembly line link in same mesh arrays are mapped in the occupied 1 grade of caching of link PE.And across mesh battle array
The assembly line link of row, data are stored in level 2 cache memory.When assembly line interrupts, the data in level 2 cache memory are cached to 3
In grade caching.When assembly line recovers, the data in 3 grades of cachings are restored in level 2 cache memory.And level 2 cache memory is as mesh gusts
The input of row, can be recovered according to the configuration of mesh arrays according to mesh array pipelining line series in PE 1 grade are data cached；It is right
In nonpipeline executive mode, it is configured to across the data of mesh arrays in 3 grades of cachings, after the mesh arrays are finished,
Next mesh arrays read the variable from 3 grades of cachings and continue to calculate.
Claims (8)
1. a kind of dynamic reconfigurable array data path with multi-level buffer, which is characterized in that formed including 4 grades of cachings more
Grade caching system, the reconfigurable control module of multi-level buffer, the coarseness operators m esh arrays and data path of support multi-level buffer
In interface module；
The function that the multilevel cache system is required according to configuration code, for completing the storage of the data in data path, data are handed over
It changes synchronous with data；
Interface module in the data path, for reading data from external memory and the data being sent to multi-level buffer system
In system；
The reconfigurable control module under the control of configuration code, complete mesh arrays read-write read-write variable and multi-level buffer address it
Between mapping control；
The coarseness operators m esh arrays calculate link used for forming, and under the control of configuration code, according to data
The definition of flow graph is read and write variable to it and is controlled.
2. the dynamic reconfigurable array data path according to claim 1 with multi-level buffer, it is characterised in that described
Multilevel cache system include,
1st grade of caching, between the PE units being connected positioned at two, for the data buffer storage in mesh array internal pipelines and
Data exchange,
Level 2 cache memory is made of the memory that pipeline data exchange is carried out between mesh arrays, and the memory is by multiple mesh
Array is shared；
3rd level caches, and is made of the caching that data exchange in nonpipeline is carried out between mesh arrays, between mesh arrays
The caching of data and exchange in nonpipeline；
4th grade of caching, is made of the shared memory between reconfigurable data access and external interface, for the number of data-interface
2 grades or 3 grades cachings are synchronized to according to caching, and by input data, the output result of 2 grades or 3 grades cachings is read and is sent to output
Interface.
3. the dynamic reconfigurable array data path according to claim 2 with multi-level buffer, it is characterised in that described
The 1st grade caching using register realize, level 2 cache memory using register file realize, 3rd level caching using dual port RAM realization,
4th grade of caching is realized using FIFO.
4. the dynamic reconfigurable array data path according to claim 2 with multi-level buffer, it is characterised in that described
The 1st grade caching in store mesh arrays in pipeline data, these data there are in PE monopolize register in, in flowing water
When line is run, the data in each 1 grade of caching of cycle are updated；The data exchanged between mesh arrays are stored in level 2 cache memory,
These data as the pipeline data for occupying multiple mesh arrays, can also be used as the data of nonpipeline operation, wherein
During as pipeline data, each cycle, these data were updated, during as nonpipeline data, when higher level's mesh arrays are complete
Into after operation, which is just updated；3rd level buffer memory nonpipeline data, while the flowing water quilt participated in level 2 cache memory
During interruption, 3rd level assembly line is by level 2 cache memory data monolithic backup；4th grade of caching is handed over as reconfigurable arrays and external data
The caching changed, after external data inputs reconfigurable arrays, these data store in the 4th grade of caching and are switched to the 2nd grade
In caching, and the result of calculation in level 2 cache memory is read by the 4th grade of caching by external bus.
5. the dynamic reconfigurable array data path according to claim 1 with multi-level buffer, it is characterised in that described
Configuration code function be：1st grade is cached, by interconnecting relation between reconfigurable arrays PE configuration codes control PE, the 1st grade is completed and delays
Deposit control；Level 2 cache memory and 3rd level are cached, controlled by cache controller in mesh arrays, the controller is according to mesh
Array configuration code is written and read the 2nd grade and 3rd level caching by clock cycle precision；4th grade is cached, by mesh arrays
Cache controller is controlled, the controller according to mesh array configuration codes, by the hollow full scale will of FIFO in the 4th grade of caching and
Mesh array operation sequences are written and read operation.
6. the dynamic reconfigurable array data path according to claim 1 with multi-level buffer, it is characterised in that described
Multi-level buffer reconfigurable control module to 1 grade of buffer control when, what the register of access was determined by configuration code, configured in single
After remain unchanged；When controlling the 2nd grade of storage, it is necessary to access the register of different address, its memory access is completed by read-write controller
The control of operation, the reading and writing of the 2nd grade of storage are all completed in signal period, and the write-in of control instruction and readout need not
Wait its completion；When controlling 3rd level storage, since read-write can could be completed within multiple cycles, it is necessary in its control instruction
Increase and read and write effective mark, to reduce the additional stand-by period generated due to the 2nd grade of storage of read-write；The 4th grade is controlled to deposit
, it is necessary to the sky in respective cache be waited to expire signal, as the beginning and end of mesh array computations during storage.
7. the dynamic reconfigurable array data path according to claim 1 with multi-level buffer, it is characterised in that described
Support multi-level buffer coarseness operators m esh arrays, the arithmetic element array by isomorphism and the interconnection unit between them
Composition, arithmetic element in arithmetic element array mainly by ALU units and store the register group of ephemeral data into each computing
The calculation function that the execution dispensing unit of unit independence is specified, the basic granularity of each arithmetic element is 8 bits, with phase in a line
4 adjacent PE units form the reconfigurable cell group of a 32 bit bit wides, support the arithmetic operation of 32 bit bit wides, adjacent
It is interconnected between two row PE units by a network element based on displacement.
8. a kind of dynamic reconfigurable array data path with multi-level buffer applied to described in claim 1-7 any one
Control method, it is characterised in that include the following steps：
Step 1）By new duty mapping into reconfigurable arrays；
Step 2）If new task includes non-iterative type pile line operation, if the assembly line is held by a mesh array
Input data in assembly line and output data, then be mapped in level 2 cache memory, other intermediate data are mapped to 1 grade of caching by row
In；If assembly line is made of multiple mesh arrays, by the input data of assembly line, output data and across different mesh arrays
Data be mapped to level 2 cache memory, other intermediate data be mapped to 1 grade caching in；
Step 3）If new task includes iterative type assembly line, if the assembly line is performed by a mesh array,
By assembly line input data, output data and the data of feedback iteration processing is needed to be mapped in level 2 cache memory, other intermediate data
It is mapped in 1 grade of caching；If the assembly line is made of multiple mesh arrays, by the input data of assembly line, output data,
Level 2 cache memory is mapped to across the data of different mesh arrays and the data of feedback iteration, other intermediate data are mapped to 1 grade of caching
In.
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| CN109446110A (en) * | 2018-10-16 | 2019-03-08 | 西安邮电大学 | The continuous U-shaped layout tile caching method of data address can be achieved |
| WO2021227552A1 (en) * | 2020-12-28 | 2021-11-18 | 西安交通大学 | Multifunctional data reorganization network |
| CN112967172B (en) * | 2021-02-26 | 2024-09-17 | 成都商汤科技有限公司 | Data processing device, method, computer equipment and storage medium |
| CN113986816B (en) * | 2021-12-09 | 2023-05-02 | 北京奕斯伟计算技术股份有限公司 | Reconfigurable computing chip |
| CN114528248A (en) * | 2022-04-24 | 2022-05-24 | 广州万协通信息技术有限公司 | Array reconstruction method, device, equipment and storage medium |
| CN117271391B (en) * | 2023-06-20 | 2024-04-16 | 海光信息技术股份有限公司 | Cache structure and electronic equipment |
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