CN203706196U - Coarse-granularity reconfigurable and layered array register file structure - Google Patents

Abstract

The utility model discloses a coarse-grained reconfigurable hierarchical array register file structure, which includes a global register file, a local register file and a distributed register file. Global register file: As a shared register connecting the system control core and the reconfigurable array, it not only satisfies the problem of parameter transfer when the system calls the reconfigurable architecture, but also serves as a register that can be connected to each unit on the array, and has reconfigurable The largest fan-out factor in the array; local register file: as the private register of the reconfigurable processing unit, the data is only for its own use; distributed register file: as the data storage and transmission channel of the partially reconfigurable computing unit in the reconfigurable array. The utility model solves the storage and transmission problem of array data in the reconfigurable computing process through the hierarchical reconfigurable array register file structure design, and improves the storage efficiency of data variables in the array and the reconfigurable computing performance.

Description

A Coarse-grained Reconfigurable Hierarchical Array Register File Structure

technical field

The utility model relates to a coarse-grained reconfigurable hierarchical array register file structure, which belongs to the embedded reconfigurable design technology.

Background technique

With the emergence of field programmable array reconfigurable technology, the traditional embedded design method has been greatly changed. Reconfigurable computing, as a new type of space-time domain computing mode, has a wide range of embedded and high-performance computing fields. The application prospect has become the development trend of the current embedded system. Algorithms in media application fields such as image processing and modern communication have large-scale parallelism and require a large number of matrix operations. The register file design allows flexible reordering and shifting operations. Read/write data selection into different registers is achieved through a multiplexer. Compared with delay chains and shift registers, register files consume more power during write operations. Consumption includes the associated logic for decoding and selection. Therefore, the loss of power consumption can be offset only when the register file is used as long-term data storage. Registers are not an optimal choice for short-lived data.

The existing reconfigurable register file architecture can be divided into two categories according to the impact on the computing performance of the array: one is the slice access register outside the array, and the other is the distributed register inside the array. The data access optimization of the reconfigurable array can be realized by reducing the memory access delay through the on-chip access register outside the array on the one hand, and on the other hand by optimizing the memory access mode of the on-chip access register. By optimizing the distributed register structure in the array, the scheduling performance degradation caused by architectural constraints in the data calculation process can be reduced, and the computing performance of the array can be improved through the hierarchical register file design and scheduling strategy.

The register organization form, sharing mechanism, replacement strategy, and partition mechanism involved in reconfigurable on-chip access registers need to be studied according to the specific array structure and memory access characteristics in order to trade off between low access latency and high hit rate with a compromise. Through the research on the data access path outside the array, including the design of on-chip memory, the unit structure of prefetching and reuse, and the design of register files based on vector and scalar, the data flow path outside the array is formed.

The memory access methods of reconfigurable arrays and global registers have an increasingly prominent impact on memory access efficiency, and have a huge impact on bandwidth performance for fast continuous and dense data. The interconnection form of the reconfigurable array and the global register obviously restricts the memory access performance of the array. The cross-interconnection structure and the ring structure used in the existing design achieve the goal of efficient access and meet the requirements of low latency, high bandwidth, and low power consumption. Storage access requirements; or use a two-dimensional access mode to accelerate multimedia data access.

How to achieve flexible partitioning of row vector registers and column vector registers at a lower cost, that is, to design a reconfigurable hierarchical array register file, is still a hot issue in this field.

Utility model content

Purpose of the invention: In order to overcome the deficiencies in the prior art, the utility model provides a coarse-grained reconfigurable hierarchical array register file structure to solve the problem of registering and transmitting array data in the process of reconfigurable calculations, so as to improve Advantages of data variable storage efficiency and reconfigurable computing performance in arrays.

Technical scheme: in order to achieve the above object, the technical scheme adopted in the utility model is:

A coarse-grained reconfigurable hierarchical array register file structure, which is used to realize the parameter transfer between the reconfigurable array arranged in an m×n rectangular array and the system control core, and at the same time complete the data registration on the reconfigurable array and transmission, realized through hardware connection, including global register file, local register file and distributed register file:

The global register file: as a shared register connecting the system control core and the reconfigurable array, as a register used for passing parameters when the system control core calls the reconfigurable array, and as a register that can be connected to each reconfigurable processing unit, Has the largest fan-out factor among reconfigurable arrays;

The local register file: each reconfiguration processing unit is correspondingly connected with a local register, and the local register is used as a private register of the corresponding reconfiguration processing unit, and the data is only used by the corresponding reconfiguration processing unit ;

The distributed register file: connected to the reconfigurable array, serves as a data storage and transmission channel between some reconfigurable processing units in the reconfigurable array.

Preferably, the global register file includes n global registers, and the data bit width of the global register file is consistent with the data bit width of the reconstruction processing unit; the global register file is used as a data transmission channel for transmitting input parameters and return values, and both the system control core and the reconfigurable array can access global registers.

Preferably, the global register file is directly interconnected with the reconfigurable array, and the specific implementation method is: design the m global registers at the top of the global register file and the 1 global register at the bottom to adopt full mesh interconnection and bus interconnection, which can be used by all The rest of the global registers are connected by the bus; when the loop input parameters are greater than m and exceed the top m global registers, the extra parameters need to be accessed through the bus; the bottom global register is used for the transfer function return value.

Preferably, the local register file is mainly used to store variables with a long life cycle and a fixed spatial location, and its input and output objects are only its private reconstruction processing unit (corresponding reconstruction processing unit); The local register can complete the preparation of the output data to the input data in one cycle; the writing of the local register is controlled by the enable bit in the configuration word, and when the position is enabled, it can be completed in one cycle and will reconfigure The calculation result of the processing unit is written into the local register file of the local register.

Preferably, the distributed register file is composed of distributed registers arranged in an m×n rectangular array, each row of register groups and each column of register groups share a distributed register, and the positions of the distributed register and the reconstruction processing unit are the same One-to-one correspondence; each reconfiguration processing unit can operate two sets of registers, which are respectively a row of registers and a column of registers where the distributed registers are placed in the corresponding position; each reconfiguration processing unit can only operate one set of registers at the same time, The read and write operations between multiple reconfiguration processing units are selected through multiplexers; multiple reconfiguration processing units can simultaneously write to cross-row domain register groups; multiple reconfiguration processing units can simultaneously perform write operations on the same distributed register read operation.

Preferably, the cross-domain register group is interconnected in the form of row interconnection or column interconnection. When the reconstruction processing unit located in the i-th row and j-th column writes data into the cross-domain register, the i-th row or j-th All reconstruction processing units on a column can obtain data through cross-domain registers.

Preferably, the distributed register file adopts a multi-input, multi-output data access form. In order to avoid different reconstruction processing units from simultaneously accessing the same distributed register, the following two methods are used to avoid:

Method 1. By avoiding simultaneous access to the same distributed register in the mapping;

Method 2: In the case of multiple unpredictable reconfiguration processing units accessing the same distributed register at the same time, according to the number of reconfiguration processing units in the reconfigurable array, the priority is divided according to the order of numbers from large to small , the reconfiguration processing unit with a high priority is used for the right to write.

Beneficial effects: the coarse-grained reconfigurable hierarchical array register file structure provided by the utility model enables accurate and efficient storage and transmission of array data in the reconfigurable calculation process, and improves the storage efficiency and reproducibility of data variables in the array. structural computing performance.

Description of drawings

Fig. 1 is a kind of structural representation of the utility model;

FIG. 2 is a schematic diagram of a global register file;

Fig. 3 is a schematic diagram of a local register file;

FIG. 4 is a schematic diagram of a distributed register file;

Fig. 5 is the structural representation of an example of the utility model;

Fig. 6 is a flow chart of data variable registration and transmission of the present invention.

Detailed ways

Below in conjunction with accompanying drawing, the utility model is described further.

A coarse-grained reconfigurable hierarchical array register file structure, which is used to realize the parameter transfer between the reconfigurable array arranged in an m×n rectangular array and the system control core, and at the same time complete the data registration on the reconfigurable array and transmission; as shown in Figure 1, including a global register file, a local register file and a distributed register file.

The global register file: as a shared register connecting the system control core and the reconfigurable array, it not only meets the parameter transfer requirements when the system control core calls the reconfigurable array, but also serves as a register that can be connected to each reconfigurable processing unit , has the largest fanout factor among reconfigurable arrays.

The global register file includes n global registers, and the data bit width of the global register file is consistent with the data bit width of the reconstruction processing unit; the global register file is used as a data transmission channel for transmitting input parameters and return values , and both the system control core and the reconfigurable array can access the global registers. The global register file is directly interconnected with the reconfigurable array, and the specific implementation method is: design the m global registers at the top of the global register file and 1 global register at the bottom to adopt full mesh interconnection and bus interconnection, which can be reconfigured by all The processing unit accesses, and the rest of the global registers are interconnected by bus; when the loop input parameter is greater than m and exceeds the top m global registers, the extra parameters need to be accessed through the bus; the bottom global register is used to transfer the return value of the function.

The global register file shown in Figure 2 contains 16 global registers, of which the top 3 global registers and the bottom 1 global register can be accessed by all reconstruction processing units; when the parameters passed in by the loop are greater than 3, When the top three registers are exceeded, the extra parameters need to be accessed through the bus; in particular, the global registers at the bottom are used for function return values; the global registers use the reconfigurable array clock domain and reset domain, and support software and hardware reset operations.

The local register file: each reconfiguration processing unit is correspondingly designed with a local register, and the local register is used as a private register of the corresponding reconfiguration processing unit, and the data is only used by the corresponding reconfiguration processing unit .

The local register file is mainly used to store variables with a long life cycle and a fixed spatial location, and its input and output objects are only its private reconstruction processing unit (corresponding reconstruction processing unit); the local register can The preparation of the output data to the input data is completed in one cycle; the writing of the local register is controlled by the enable bit in the configuration word. When the position is enabled, it can be completed in one cycle to reconstruct the processing unit The calculation result is written to the local register file of the local register.

As shown in Figure 3, the local register only provides 4 sub-local registers during design, and the local register can complete the preparation from output data to input data in one cycle.

The distributed register file: serves as a data storage and transmission channel between some reconfigurable processing units in the reconfigurable array.

The distributed register file is composed of distributed registers arranged in an m×n rectangular array, each row of register groups and each column of register groups share a distributed register, and the distributed registers correspond to the positions of the reconstruction processing units one by one; Each reconfiguration processing unit can operate two sets of registers, which are respectively a row of registers and a column of registers where the distributed registers are placed in corresponding positions; each reconfiguration processing unit can only operate one set of registers at the same time, and multiple reconfigurations The read and write operations between the reconfiguration processing units are selected through the multiplexer; multiple reconfiguration processing units can simultaneously perform write operations on cross-row domain register groups; multiple reconfiguration processing units can simultaneously perform read operations on the same distributed register. The cross-domain register group is interconnected in the form of row interconnection or column interconnection. When the reconstruction processing unit located in the i-th row and j-th column writes data into the cross-domain register, the i-th row or j-th column All reconstruction processing units can obtain data through cross-domain registers. The distributed register file adopts a multi-input and multi-output data access form. In order to avoid different reconstruction processing units from simultaneously accessing the same distributed register, the following two methods are used to avoid:

Method 1. By avoiding simultaneous access to the same distributed register in the mapping;

Method 2: In the case of multiple unpredictable reconfiguration processing units accessing the same distributed register at the same time, according to the number of reconfiguration processing units in the reconfigurable array, the priority is divided according to the order of numbers from large to small , the reconfiguration processing unit with a high priority is used for the right to write.

For example, when the data output by the reconstruction processing unit located at point (i, j) of the array needs to be transmitted to the reconstruction processing unit located at point (1, 1) of the array, by positioning at (i, 1) or (1, The reconstruction processing unit at position j) performs data transfer. At the moment of running T _i , the reconstruction processing unit at point (i, j) of the array writes the data into bit 0 in the cross-row register group. At time T _i +1, The reconstruction processing unit located at point (i, 1) of the array writes the data in the DCR cross-row register group 0 to the position of the cross-column register group 0 through the data exchange instruction, so that at T _i + 2 time, the data in the array (1, 1 ) can obtain the data written by the reconstruction processing unit at point (i, j) of the array in cross-column register set 0.

The minimum reconfigurable computing system shown in Figure 5 adopts the reconfigurable hierarchical array register file structure proposed in this case. The structure of the system includes: ARM7TDMI processor used as the system control core, reconfigurable array, global register file, local register file, AHB bus and distributed register file used for data transmission.

The ARM7TDMI processor with the advantages of small size, fast, low energy consumption, and good compiler support is selected as the core to control the scheduling and configuration of system operation; the global register file is connected to the reconfigurable array through the 64bitAHB bus; the local register file is connected to the reconfigurable The reconfigurable array is interconnected through a dedicated access interface with a data bit width of 128 bits; the distributed register file and the reconfigurable array are interconnected through a dedicated access interface with a data bit width of 128 bits; the reconfigurable array contains 4×4 reconfiguration processing Unit, each reconfigurable processing unit can support single-cycle 16-bit arithmetic operations and logic operations.

The registration and transmission process of the reconfigurable array data is shown in Figure 6, including: transmission request: the reconfigurable array obtains instructions from the external memory, requests the transmission of parameters or reconfigurable array data; if the data to be transmitted To exchange with the system control core, the data exchange with the system control core is realized through the global register file; otherwise, it is judged whether it is data exchange in the reconfigurable array, and if it is data exchange in the reconfigurable array, the data is realized through the distributed register file Otherwise, it is the data registration of the reconstruction processing unit, and the data registration is performed through the local register. The registration and transmission of reconfigurable data According to different situations, the most suitable register file is selected for registration and transmission, which makes full use of the resources of the register file, thereby improving the storage efficiency of data variables and reconfigurable computing performance.

The above is only a preferred embodiment of the utility model, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the utility model, some improvements and modifications can also be made. Retouching should also be regarded as the scope of protection of the present utility model.

Claims (6)

1. the array register file structure of coarseness restructural stratification, it is characterized in that: for realizing the parameter transmission between reconfigurable arrays and the system control kernel that m × n rectangular array arranges, the data that simultaneously complete on reconfigurable arrays are deposited and transmit, and comprise global register file, local register file and distributed register file:

Described global register file: as the shared register of connected system control kernel and reconfigurable arrays, the register that during as system control kernel calls reconfigurable arrays, Transfer Parameters uses, the register that can connect as each reconstruction processing unit, has the fan leaves coefficient maximum in reconfigurable arrays simultaneously;

Described local register file: the equal correspondence in each reconstruction processing unit is connected with a local register, described local register is as the privately owned register of the reconstruction processing unit of answering in contrast, and data are only for the reconstruction processing unit of answering in contrast;

Described distributed register file: be connected with reconfigurable arrays, deposit and transmission channel as the data between reconstruction processing unit in reconfigurable arrays.

2. the array register file structure of coarseness restructural according to claim 1 stratification, it is characterized in that: described global register file, comprise n global register, the data bit width of described global register file is consistent with the data bit width of reconstruction processing unit; Described global register file is as data transmission channel, and for transmitting input parameter and rreturn value, and system control kernel and reconfigurable arrays can carry out access to global register.

3. the array register file structure of coarseness restructural according to claim 2 stratification, it is characterized in that: described global register file and reconfigurable arrays are directly interconnected, concrete methods of realizing is: m global register on design global register file top and 1 global register of bottom adopt that full mesh is interconnected and bus is interconnected, can be by all reconstruction processing unit access, and all the other global registers employing buses are interconnected; 1 global register of bottom is for transition function rreturn value.

4. the array register file structure of coarseness restructural according to claim 1 stratification, it is characterized in that: described local register file, be mainly used in storage lifecycle compared with length and the fixing variable in locus, the object of its input and output is all its privately owned reconstruction processing unit; Writing by the enable bit control in configuration words of described local register.

5. the array register file structure of coarseness restructural according to claim 1 stratification, it is characterized in that: described distributed register file is made up of the distributed register of arranging by m × n rectangular array, every row register group and every column register group are shared a distributed register, and the position of distributed register and reconstruction processing unit is corresponding one by one; Each reconstruction processing unit can operate two groups of registers, is respectively a line register group and a column register group that correspondence position distributed register is placed in; Each reconstruction processing unit only can operate one group of register at one time, and the read-write operation between multiple reconstruction processing unit is selected by Port Multiplier; Multiple reconstruction processing unit can carry out write operation to inter-bank domain register group simultaneously; Multiple reconstruction processing unit can carry out read operation to same distributed register simultaneously.

6. the array register file structure of coarseness restructural according to claim 5 stratification, it is characterized in that: described cross-domain register group is interconnected or be listed as interconnected mode and realize interconnected with row, when data are write cross-domain register by the reconstruction processing unit that i is capable when being positioned at, j is listed as, being positioned at all reconstruction processing unit that i is capable or j lists can obtain data by cross-domain register.