CN104102586A - Address mapping processing method and address mapping processing device - Google Patents
Address mapping processing method and address mapping processing device Download PDFInfo
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- CN104102586A CN104102586A CN201310130486.6A CN201310130486A CN104102586A CN 104102586 A CN104102586 A CN 104102586A CN 201310130486 A CN201310130486 A CN 201310130486A CN 104102586 A CN104102586 A CN 104102586A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
Abstract
The invention discloses an address mapping processing method and an address mapping processing device. The method comprises the following steps: partitioning a logic address according to the quantity of currently-allocated DDR (Double Data Rate) synchronous RAM (Random Access Memories); respectively performing mapping processing between logic addresses and physical addresses according to the logic address in each region obtained by partitioning. A mapping unit of the device is used for respectively performing mapping processing between the logic addresses and the physical addresses according to the logic address in each region obtained by partitioning. The address mapping processing method and the address mapping processing device can be used for not only saving RAM resources, but also realizing efficient management on the physical addresses.
Description
Technical field
The present invention relates to the address mapping techniques of data communication field, relate in particular to method and device that the mapping of a kind of address is processed.
Background technology
Double Data Rate synchronous random access memory, be called for short the memory techniques standard of new generation that DDR SDRAM is EEE electronic equipment engineering joint committee (JEDEC) and issue in 2004, because of its cheap price, the data throughput of high bandwidth and advantage low in energy consumption, DDR SDRAM is widely used in the high data communication field of storage demand.Yet at data communication chip field, the Key performance index of chip is pack processing number per second (PPS), by it, determined that DDR SDRAM for data pack buffer must reach minimum read-write efficiency to meet the processing power of chip.Meanwhile, because cost factor, the method with increase DDR SDRAM physics sheet number that again can not be simple improves the data throughput of whole chip.
DDR SDRAM is widely used in data communication chip field, for message processing procedure buffer memory bag data, is generally the third generation product of DDR at present, i.e. DDR3 SDRAM, herein follow-up abbreviation DDR3.The general tupe of data communication chip is: first packet buffers into bag the outer DDR3 chip of sheet after the processing of MAC layer, generate the DDR3 physical address of data cached bag, and the part using it as packet characteristic information continues other as the processing of agreement and qos feature simultaneously.To Ethernet data message, the minimum length of bag is 64B, the burst address bit wide of main flow DDR3 is 16B at present simultaneously, can see that a packet at least needs 4 burst addresses, if directly using the DDR3 physical address of packet as its characteristic information, at least need to carry 4 physical addresss, cause resource to increase.
For reducing expense, prior art generally adopts logical address as the characteristic information of data pack buffer address, a logical address represents several DDR3 physical addresss, this kind of scheme needs to do mapping relations one to one between the logical address of DDR3 and physical address, but, the problem that adopts prior art to exist is: the processing scheme of this address mapping had both been wasted RAM resource, cannot realize again the efficient management to physical address
Summary of the invention
In view of this, the method and the device that provide the mapping of a kind of address to process are provided fundamental purpose of the present invention, have both saved RAM resource, can realize again the efficient management to physical address.
For achieving the above object, technical scheme of the present invention is achieved in that
The method that address mapping is processed, the method comprises:
According to the Double Data Rate synchronous random access memory DDR quantity of current configuration to logical address subregion;
The mapping of carrying out respectively between logical address and physical address according to the logical address of each segment after subregion is processed.
Wherein, the described DDR quantity according to current configuration specifically comprises logical address subregion:
The physical store body bank quantity comprising according to DDR quantity and each DDR obtains total physics bank number;
Total logical address is divided into a plurality of logical address sections, and segments is the maximal value that in all common divisors of described total physics bank number, numerical value is 2n, chained list quantity in described n segment.
Wherein, the described mapping processing of carrying out respectively between logical address and physical address according to the logical address of each segment after subregion specifically comprises:
Numerical value is in the situation of 2n, and the corresponding physics bank of each logical address section, is the mapping one to one of logical address and physical address;
Numerical value is in the situation of non-2n, and the corresponding a plurality of physics bank of each logical address section are the one-to-many mapping of logical address and physical address.
Wherein, the method also comprises: during described one-to-many mapping, be each physics bank configuration section bias internal base address, the quantity of described section of bias internal base address is n-1.
Wherein, the method also comprises: according to described section of bias internal base address and section bias internal address, and the section bias internal physics bank address that the section of obtaining bias internal address is corresponding.
Wherein, the method also comprises: according to described section of bias internal physics bank address, obtain corresponding physical line address and physical column address.
The device that address mapping is processed, this device comprises: subregion processing unit and mapping processing unit; Wherein,
Described subregion processing unit, for according to the DDR quantity of current configuration to logical address subregion;
Described mapping processing unit, processes for the mapping of carrying out respectively according to the logical address of each segment after subregion between logical address and physical address.
Wherein, described subregion processing unit, the physical store body bank quantity that is further used for comprising according to DDR quantity and each DDR obtains total physics bank number, total logical address is divided into a plurality of logical address sections, and segments is the maximal value that in all common divisors of described total physics bank number, numerical value is 2n, chained list quantity in described n segment.
Wherein, described mapping processing unit, is further used in situation that numerical value is 2n, makes the corresponding physics bank of each logical address section, is the mapping one to one of logical address and physical address; Numerical value is in the situation of non-2n, makes the corresponding a plurality of physics bank of each logical address section, is the one-to-many mapping of logical address and physical address.
Wherein, described mapping processing unit, while being further used for one-to-many mapping, is each physics bank configuration section bias internal base address, and the quantity of described section of bias internal base address is n-1; According to described section of bias internal base address and section bias internal address, the section bias internal physics bank address that the section of obtaining bias internal address is corresponding; According to described section of bias internal physics bank address, obtain corresponding physical line address and physical column address.
The solution of the present invention according to the DDR quantity of current configuration to logical address subregion; The mapping of carrying out respectively between logical address and physical address according to the logical address of each segment after subregion is processed.Owing to adopting the present invention directly to carry out logical address to the mapping of physical address for total logical address, but after being processed, total logical address subregion shines upon again processing, thereby reduced taking of logical address, both saved RAM resource, and logical address still less more easily location addressing realize, can realize again the efficient management to physical address.
Accompanying drawing explanation
Fig. 1 is method flow diagram of the present invention;
The segmentation table schematic diagram of logical address when Fig. 2 is the different DDR3 quantity of application example one of the present invention;
Fig. 3 is that the mapping device of application example two of the present invention forms structural representation;
Fig. 4 is that the code translator based on Mapping implementation decode procedure of application example three of the present invention forms structural representation.
Embodiment
The solution of the present invention is the mapping processing scheme of one-to-many between the logical address of DDR3 and physical address, use minimum logical address resource to meet system demand, according to the DDR3 quantity of current system configuration, logical address is divided into segment, then by segment, carries out separately the mapping between logical address and physical address.
For simplified characterization, follow-uply when linked list array form represents, logical address to be described referred to as PMAU, memory bank (bank) in full all refers to physics bank, rather than logical physical bank.Chained list quantity in n segment herein.
Below in conjunction with accompanying drawing, the enforcement of technical scheme is described in further detail.
Be illustrated in figure 1 the inventive method schematic flow sheet, this flow process comprises the following steps:
Step 101, according to the DDR quantity of current configuration to logical address subregion.
Step 102, the mapping of carrying out respectively one-to-many between logical address and physical address according to the logical address of each segment after subregion are processed.
Application example one: this example adds up to 128k with logical address, it is the concrete elaboration of example mapping processing procedure of the present invention that the changeable set number of the outer DDR3 of sheet is 1～5 group.
Step 201: total logical address is done to minute section and process, and adopt the mode of dividing equally.
Here, the detailed process of step 201 is: according to the DDR3 group number of current system configuration, total logical address idle node interval is divided into n section (every section of fragment number by logical address represents), wherein dividing sector number is the maximal value that all common divisor intermediate values of physics bank sum are 2n, like this, PMAU[16:15-n] represent sectional address.
For instance, for example, when DDR3 quantity is 5, when every DDR3 comprises 8 physics bank, the maximal value that the common divisor that total physics bank quantity is 40,40 is 2n is 8, that is to say when DDR3 quantity is 5, and 40 physics bank are divided into 8 sections.
The rule that above-mentioned segmentation adopts, in order to make the section bias internal address of every section of logical address can be with PMAU[16:15-n] carry out fast characterizing, and every section comprises minimum physics bank quantity, residue PMAU[14-n:0] be the offset address of logical address in every section, follow-up decoding meeting is fairly simple.The segmentation situation of the lower logical address of different DDR3 quantity configurations is as shown in content in the table of Fig. 2.
Step 202: for every section, according to the section bias internal base address of section bias internal address and system configuration, obtain logical address this section of corresponding section bias internal physics bank address, No. bank, section bias internal physics corresponding to logical address.
Dividing the situation of 2n and the situation of non-2n, is that logical address and physical address shine upon one to one in the situation of 2n, according to prior art, processes; In the situation of non-2n, be logical address and the mapping of physical address one-to-many.
For instance, content in the table of Fig. 2, under system configuration, if DDR3 group number is the situation of 1,2,4 2n such as grade, every section only includes 1 physics bank, and the fragment number in the table of Fig. 2 represents No. bank, the affiliated physics of logical address.
To DDR3 group number, it not the situation of 2n, if DDR3 group number is 3 and 5 situation, in the piecewise interval of each logical address, comprise a plurality of physics bank, in current example, the physics bank quantity that when DD3 quantity is 5, every section comprises is maximum, and every section comprises 5 physics bank.
In order to distinguish the section bias internal physics bank address in this section corresponding to logical address, the present invention sets a skew base address to respectively each physics bank, and in the section of supposition, chained list quantity is n, and the skew base address number of required physics bank is n-1.So under current example, when DDR3 quantity is 5, the section bias internal base address needing is maximum, number is 4, when DDR3 quantity is 3, under above-mentioned chopping rule, because every section only comprises 3 physics bank, therefore only need 2 skew base address.The DDR3 quantity of take equals 3 as example, suppose that above-mentioned 2 offset addresss are respectively a0 and a1, PMAU[13:0] be the offset address of PMAU in section, because every section comprises 3 physics bank, so as PMAU[13:0] during < a0, the skew physics bank address of this PMAU in section is 0, as a0 <=PMAU[13:0] during < a1, the skew physics bank address of this PMAU in section is 1, as PMAU[13:0] during >=a1, the skew physics bank address of this PMAU in section is 2.That is to say, the object of subregion is exactly to obtain dividing Division with the skew base address of system configuration, as with skew base address 0,1,2 subregion identifying (0-1) and (1-2), the relation of offset address and this skew base address is: in each subregion (0-1) and any one subregion (1-2), continue to divide, with skew base address, identify, such as carrying out refinement with 0.1,0.2,0.3......0.9 again in subregion (0-1).Here to it is pointed out that " 0.1 " etc. is in order conveniently explaining, to describe in digital form, is the form that adopts address to represent in practical application, similar PMAU[13:0] this description, do not repeat herein.
In a word, when DDR3 quantity is 3, if as a0 <=PMAU[13:0] < a1, and the sector address under this PMAU is 3, the physics of this PMAU in 24 physics bank is for No. bank so: 9+1=10.
Wherein, in the equation of 9+1=10, first left 9 represents the physics bank base address (every section comprises 3 physics bank) of all physics bank that sector address is 3, and 1 represents the skew physics bank address in section.Can obtain thus section bias internal physics bank address corresponding to logical address under various configurations, also can be called No. bank, the affiliated physics of logical address.
Step 203: the base address that obtains the concrete row, column in this section of bias internal physics bank address according to section bias internal physics bank address.
The form of expression of physics bank address is equivalent to two-dimensional matrix, and the section of finding bias internal physics bank address, also needs the row, column base address of finding this physics bank address concrete.After having calculated No. bank, the affiliated physics of logical address, according to skew base address and the PMAU[14-n:0 in section] comparative result be easy to just can obtain the offset address of this logical address in affiliated physics bank.The above-mentioned DDR3 quantity of still take equals 3 as example, the sector address of supposing this logical address is 3, be PMAU[16:14]=3, and a0 <=PMAU[13:0] < a1, (PMAU[13:0]-a0) is the offset address in physics bank under this logical address so.Finally according to the length of current logical address and the every row of DDR3, can obtain row, column address, for example the length of logical address and the every row of DDR3 is all the words of 2KB, because every row only has logical address, so a PMAU[13:0] be row address, the base address of row is full 0.Ranks base address computing method under other various configurations roughly the same.
It is to be noted, the present invention is only with third generation DDR, be that DDR3 is the mapping that in example explanation data chip field, logical address arrives physical address, thereby realize the management of external cache, but so long as the DDR in data chip field can adopt mapping scheme of the present invention to manage external cache, thus quickness and high efficiency realize decoding.
Contrast prior art and the present invention, take DDR3 as example, and prior art logical address and physical address shine upon one to one, have following problem:
For guaranteeing certain caching performance, the fixing logical address quantity of General Requirements while realizing, during existing techniques in realizing, generally adopts the simple mapping relations between logical address bit territory and DDR3 physical address bit territory.For example, for a 2G, the DDR3 of 16bit bit wide, corresponding physics bank address, row address and burst column address bit wide be 3bit respectively, 14bit and 7bit, if each logical address is fixed as 2KB and logical address quantity is fixed as 128K, because the every row of DDR3 is 2KB, so logical address is the base address of every row, logical address is also comparatively simple to the decoded mode of physical base address, adopts the corresponding physics bank of the highest 3bit address, middle 14bit corresponding row address, minimum bit low level is mended 0 method that is row base address can complete decoding.Yet during actual use, the quantity of needed DDR3 is not often 2 integer power, as 3 groups.If still need to adopt this kind of simple interpretation method, the logical address quantity to 128K, needs 19bit to characterize.Meanwhile, the system schema demand General Requirements of shared buffer memory adopts the mode management logic address of vessel used to hold grain at the imperial sacrifice table, and addressing pointer that need to be using logical address as RAM, will cause 4 times more than of the required RAM wastings of resources like this.According to the different application scene of chip, when may require plug-in DDR3 quantity variable, require to possess identical utilogic number of addresses.
If as prior art, total logical address is directly used in to the mapping one to one with physical address, can waste too much logical address, and employing the present invention, due to first to total logical address segmentation, according to logical address section, in section, carry out separately again the mapping processing of logical address and physical address, can use minimum logical address resource to meet system demand, as the logical address quantity of 128K, the fixing 17bit of use characterizes, thereby employing the present invention, farthest saved system RAM resource, and can realize the efficient management to physical address, mainly to shine upon to realize addressing of address function by address.
Application example two: the mapping device based on realizing mapping scheme of the present invention.
As shown in Figure 3, this mapping device is positioned at buffer memory side, comprising: subregion processing unit and mapping processing unit; Wherein, subregion processing unit is used for according to the DDR quantity of current configuration logical address subregion; Mapping processing unit is processed for the mapping of carrying out respectively according to the logical address of each segment after subregion between logical address and physical address.
Here, the physical store body bank quantity that subregion processing unit is further used for comprising according to DDR quantity and each DDR obtains total physics bank number, total logical address is divided into a plurality of logical address sections, and segments is the maximal value that in all common divisors of described total physics bank number, numerical value is 2n, chained list quantity in described n segment.
Here, mapping processing unit is further used in situation that numerical value is 2n, makes the corresponding physics bank of each logical address section, is the mapping one to one of logical address and physical address; Numerical value is in the situation of non-2n, makes the corresponding a plurality of physics bank of each logical address section, is the one-to-many mapping of logical address and physical address.
Here, the most preferred embodiment of mapping processing unit when one-to-many shines upon is: mapping processing unit is used to each physics bank configuration section bias internal base address, and the quantity of described section of bias internal base address is n-1; According to described section of bias internal base address and section bias internal address, the section bias internal physics bank address that the section of obtaining bias internal address is corresponding; According to described section of bias internal physics bank address, obtain corresponding physical line address and physical column address.
Application example three: the decode procedure of realizing based on mapping scheme of the present invention.
Be illustrated in figure 4 and realize the code translator that decode procedure adopts, in Fig. 4, the bilingual of noun is as follows:
App_pmau_vld: logical address to be decoded is effectively indicated;
App_pmau: logical address to be decoded;
DFF:D trigger;
Compare: comparer;
Pmau_fld: the fragment number of the logical address to be decoded parsing according to DDR group number;
Pmau_fld_offset: the section bias internal address of logical address to be decoded;
Pmau_fld_dly1: deposit after the segmentation after decoding;
Pmau_fld_ physics bank: No. bank, the section bias internal physics according to base address in section bias internal address and section after relatively;
Ddr_ physics bank_addr: the physics bank address parsing;
Ddr_row_addr: the physical line address parsing;
Ddr_col_addr: the physical column address parsing;
Pmau_ physics bank_offset: the physics bank internal blas address of ddr logical address to be resolved;
Cfg_ physics bank_addr[i]: user configured for base address in section relatively, total number is i;
Cfg_pmau_width: the PMAU length of configuration
Cfg_ddrc_num: the DDR group number of configuration.
Here, it is pointed out that parts trapezoidal in Fig. 4 all represent arithmetical unit.
The decode procedure (decoding from logical address to physical address) that adopts above-mentioned code translator to realize comprises following content:
1, first according to the segment number (pmau_fld) of the logical address to be decoded of user configured DDR group number (cfg_ddrc_num) decision input and the offset address (pmau_fld_offset) in this logical address place section.
2, base address in the offset address in section and user configured section (cfg_ physics bank_addr[i]) relatively specifically belonged to which physics bank in the section of drawing bias internal address in this section, i.e. No. bank, section bias internal physics (pmau_fld_ physics bank[2:0]) and the skew physical address in corresponding physics bank (pmau_ physics bank_offset).
3, according to No. bank, skew physics in the segment number of logical address and section, calculate No. bank, physics physics learning logical address.
4, according to the skew physical address decoding in physics bank, obtain line number and the row number concrete row address and the column address of this physical address (thereby obtain) of this physical address.
The above, be only preferred embodiment of the present invention, is not intended to limit protection scope of the present invention.
Claims (10)
1. the method that address mapping is processed, is characterized in that, the method comprises:
According to the Double Data Rate synchronous random access memory DDR quantity of current configuration to logical address subregion;
The mapping of carrying out respectively between logical address and physical address according to the logical address of each segment after subregion is processed.
2. method according to claim 1, is characterized in that, the described DDR quantity according to current configuration specifically comprises logical address subregion:
The physical store body bank quantity comprising according to DDR quantity and each DDR obtains total physics bank number;
Total logical address is divided into a plurality of logical address sections, and segments is the maximal value that in all common divisors of described total physics bank number, numerical value is 2n, chained list quantity in described n segment.
3. method according to claim 2, is characterized in that, the described mapping processing of carrying out respectively between logical address and physical address according to the logical address of each segment after subregion specifically comprises:
Numerical value is in the situation of 2n, and the corresponding physics bank of each logical address section, is the mapping one to one of logical address and physical address;
Numerical value is in the situation of non-2n, and the corresponding a plurality of physics bank of each logical address section are the one-to-many mapping of logical address and physical address.
4. method according to claim 3, is characterized in that, the method also comprises: during described one-to-many mapping, be each physics bank configuration section bias internal base address, the quantity of described section of bias internal base address is n-1.
5. method according to claim 4, is characterized in that, the method also comprises: according to described section of bias internal base address and section bias internal address, and the section bias internal physics bank address that the section of obtaining bias internal address is corresponding.
6. method according to claim 5, is characterized in that, the method also comprises: according to described section of bias internal physics bank address, obtain corresponding physical line address and physical column address.
7. the device that address mapping is processed, is characterized in that, this device comprises: subregion processing unit and mapping processing unit; Wherein,
Described subregion processing unit, for according to the DDR quantity of current configuration to logical address subregion;
Described mapping processing unit, processes for the mapping of carrying out respectively according to the logical address of each segment after subregion between logical address and physical address.
8. device according to claim 7, it is characterized in that, described subregion processing unit, the physical store body bank quantity that is further used for comprising according to DDR quantity and each DDR obtains total physics bank number, total logical address is divided into a plurality of logical address sections, and segments is the maximal value that in all common divisors of described total physics bank number, numerical value is 2n, chained list quantity in described n segment.
9. device according to claim 8, is characterized in that, described mapping processing unit is further used in situation that numerical value is 2n, makes the corresponding physics bank of each logical address section, is the mapping one to one of logical address and physical address; Numerical value is in the situation of non-2n, makes the corresponding a plurality of physics bank of each logical address section, is the one-to-many mapping of logical address and physical address.
10. device according to claim 9, is characterized in that, described mapping processing unit, while being further used for one-to-many mapping, is each physics bank configuration section bias internal base address, and the quantity of described section of bias internal base address is n-1; According to described section of bias internal base address and section bias internal address, the section bias internal physics bank address that the section of obtaining bias internal address is corresponding; According to described section of bias internal physics bank address, obtain corresponding physical line address and physical column address.
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| CN201310130486.6A CN104102586B (en) | 2013-04-15 | 2013-04-15 | A kind of method, apparatus of address of cache processing |
| PCT/CN2013/090967 WO2014169690A1 (en) | 2013-04-15 | 2013-12-30 | Method and device for processing address mapping |
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| CN201310130486.6A CN104102586B (en) | 2013-04-15 | 2013-04-15 | A kind of method, apparatus of address of cache processing |
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| CN110851372A (en) * | 2018-08-20 | 2020-02-28 | 慧荣科技股份有限公司 | Storage device and cache addressing method |
| CN111367461A (en) * | 2018-12-25 | 2020-07-03 | 北京兆易创新科技股份有限公司 | Storage space management method and device |
| CN111367461B (en) * | 2018-12-25 | 2024-02-20 | 兆易创新科技集团股份有限公司 | Storage space management method and device |
| CN110781101A (en) * | 2019-10-25 | 2020-02-11 | 苏州浪潮智能科技有限公司 | One-to-many mapping relation storage method and device, electronic equipment and medium |
| CN114328286A (en) * | 2022-03-14 | 2022-04-12 | 南京芯驰半导体科技有限公司 | Method for improving system access performance |
| CN114328286B (en) * | 2022-03-14 | 2022-07-15 | 南京芯驰半导体科技有限公司 | Method for improving system access performance |
| CN114707478A (en) * | 2022-06-06 | 2022-07-05 | 飞腾信息技术有限公司 | Mapping table generation method, device, equipment and storage medium |
| CN114707478B (en) * | 2022-06-06 | 2022-09-02 | 飞腾信息技术有限公司 | Mapping table generation method, device, equipment and storage medium |
Also Published As
| Publication number | Publication date |
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| WO2014169690A1 (en) | 2014-10-23 |
| CN104102586B (en) | 2019-02-22 |
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