CN114707478B - Mapping table generation method, device, equipment and storage medium - Google Patents
Mapping table generation method, device, equipment and storage medium Download PDFInfo
- Publication number
- CN114707478B CN114707478B CN202210626925.1A CN202210626925A CN114707478B CN 114707478 B CN114707478 B CN 114707478B CN 202210626925 A CN202210626925 A CN 202210626925A CN 114707478 B CN114707478 B CN 114707478B
- Authority
- CN
- China
- Prior art keywords
- block
- depth
- execution state
- mapping table
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F40/00—Handling natural language data
- G06F40/10—Text processing
- G06F40/166—Editing, e.g. inserting or deleting
- G06F40/177—Editing, e.g. inserting or deleting of tables; using ruled lines
- G06F40/18—Editing, e.g. inserting or deleting of tables; using ruled lines of spreadsheets
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
Abstract
The present disclosure provides a mapping table generating method, apparatus, device and storage medium, wherein the method comprises: establishing a mapping table, wherein the mapping table comprises four blocks, the depth of a first block and a third block is a first depth, the depth of a second block and a fourth block is a second depth, and the first depth is greater than the second depth; generating a request based on a mapping table, and acquiring mapping data; and writing the mapping data into a block corresponding to the mapping table according to the execution state of the processor. The mapping table generating method disclosed by the invention has the advantages of small mapping table area and high reading speed.
Description
Technical Field
The present disclosure relates to the field of computers, and in particular, to a mapping table generating method, apparatus, device, and storage medium.
Background
With the development of computer technology, some electronic devices are compatible with two execution states, when instructions are executed in different execution states, the required mapping tables are different in size, and it is more complicated to adopt different mapping tables in different execution states. When the same mapping table is adopted to be compatible with two execution states, the block number and the depth of the mapping table adopt the largest one required by the two execution states, so that the area of the mapping table is large, and the reading speed is influenced.
Disclosure of Invention
The present disclosure provides a mapping table generating method, apparatus, device and storage medium, so as to at least solve the above technical problems in the prior art.
According to a first aspect of the present disclosure, there is provided a mapping table generating method, the method including:
establishing a mapping table, wherein the mapping table comprises four blocks, the depth of a first block and a third block is a first depth, the depth of a second block and a fourth block is a second depth, and the first depth is greater than the second depth;
generating a request based on a mapping table, and acquiring mapping data;
and writing the mapping data into a block corresponding to the mapping table according to the execution state of the processor.
In one embodiment, the execution state of the processor includes a first execution state and a second execution state; writing the mapping data into a block corresponding to the mapping table according to the execution state of the processor, including:
writing the mapping data to an area of a second depth of the second block, the fourth block, and the first block and the third block while the processor is in a first execution state;
and when the processor is in a second execution state, writing the mapping data into the first block and the third block.
In one embodiment, the first execution state is the AArch32 execution state and the second execution state is the AArch64 execution state.
In one embodiment, the second depth is one-half of the first depth.
In one embodiment, the first depth is 32 rows and the second depth is 16 rows; or
The first depth is 16 rows and the second depth is 8 rows.
According to a second aspect of the present disclosure, there is provided an instruction execution method, the method comprising:
acquiring a source register number of an instruction;
inquiring a mapping table according to the number to obtain a physical register corresponding to the source register;
the mapping table comprises four blocks, wherein the depth of a first block and a third block is a first depth, the depth of a second block and a fourth block is a second depth, and the first depth is greater than the second depth; and when the mapping table is inquired, inquiring a block corresponding to the mapping table according to the execution state of the processor.
In one embodiment, the execution state of the processor includes a first execution state and a second execution state; according to the execution state of the processor, inquiring the block corresponding to the mapping table, wherein the inquiring comprises the following steps:
when the processor is in a first execution state, querying areas of a second depth of the second block, the fourth block and the first block and the third block;
and when the processor is in a second execution state, querying the first block and the third block.
In one embodiment, the first execution state is the AArch32 execution state and the second execution state is the AArch64 execution state.
In one embodiment, the second depth is one-half of the first depth.
In one embodiment, the first depth is 32 rows and the second depth is 16 rows; or
The first depth is 16 rows and the second depth is 8 rows.
According to a third aspect of the present disclosure, there is provided a mapping table generating apparatus, the apparatus including:
the mapping table comprises four blocks, wherein the depth of a first block and a third block is a first depth, the depth of a second block and a fourth block is a second depth, and the first depth is greater than the second depth;
the obtaining module is used for generating a request based on a mapping table and obtaining mapping data;
and the writing module is used for writing the mapping data into the block corresponding to the mapping table according to the execution state of the processor.
According to a fourth aspect of the present disclosure, there is provided an instruction execution apparatus, the apparatus comprising:
the obtaining module is used for obtaining the source register number of the instruction;
the query module is used for querying a mapping table according to the number to obtain a physical register corresponding to the source register; the mapping table comprises four blocks, wherein the depth of a first block and a third block is a first depth, the depth of a second block and a fourth block is a second depth, and the first depth is greater than the second depth; and when the mapping table is inquired, inquiring a block corresponding to the mapping table according to the execution state of the processor.
According to a fifth aspect of the present disclosure, there is provided an electronic device comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods of the present disclosure.
According to a sixth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of the present disclosure.
In the mapping table generating method, the mapping table is established to comprise four blocks, the depth of a first block and a third block is a first depth, the depth of a second block and a fourth block is a second depth, and the first depth is greater than the second depth; generating a request based on a mapping table, and acquiring mapping data; and writing the mapping data into a block corresponding to the mapping table according to the execution state of the processor. The mapping table blocks generated by the method of the embodiment of the disclosure have different depths, so that the requirements of different execution states can be met, the area of the mapping table is reduced, and the reading speed is improved.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:
in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
FIG. 1 is a flow chart illustrating an implementation of a mapping table generating method according to an embodiment of the disclosure;
FIG. 2 illustrates a structural diagram of a mapping table in an embodiment of the present disclosure;
FIG. 3 is a flow chart illustrating an implementation of an instruction execution method according to an embodiment of the disclosure;
FIG. 4 is a schematic diagram illustrating a component structure of a mapping table generating apparatus according to an embodiment of the disclosure;
FIG. 5 is a block diagram of an instruction execution apparatus according to an embodiment of the present disclosure;
fig. 6 shows a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, features and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
Referring to fig. 1, an embodiment of the present disclosure provides a mapping table generating method, where the method includes:
establishing a mapping table, wherein the mapping table comprises four blocks, the depth of a first block and a third block is a first depth, the depth of a second block and a fourth block is a second depth, and the first depth is greater than the second depth;
generating a request based on a mapping table, and acquiring mapping data;
and writing mapping data into a block corresponding to the mapping table according to the execution state of the processor.
In the mapping table generating method, the mapping table is established to comprise four blocks, the depth of a first block and a third block is a first depth, the depth of a second block and a fourth block is a second depth, and the first depth is greater than the second depth; generating a request based on a mapping table, and acquiring mapping data; and writing mapping data into a block corresponding to the mapping table according to the execution state of the processor. The mapping table blocks generated by the method of the embodiment of the disclosure have different depths, so that the requirements of different execution states can be met, the area of the mapping table is reduced, and the reading speed is improved.
The method of the embodiment of the disclosure is used for the electronic device with two execution states, and the generated mapping table is compatible with the two execution states, and meanwhile, the area of the mapping table is reduced, and the reading speed is improved.
The method of the embodiment of the disclosure can be used for an electronic device adopting an ARMv8 architecture processor, the ARMv8 architecture processor has a mapping relation between SIMD (Single Instruction Multiple Data) and floating point registers in an AArch32 execution state, and has 32-bit registers S0-S31, 32 64-bit registers D0-D31 and 15 128-bit registers Q0-Q15 in the AArch32 execution state, wherein S0-S31 and D0-D15 are respectively mapped to Q0-Q7, D16-D31 are mapped to Q8-Q15, and only 32 128-bit registers Q0-Q31 in the AArch64 execution state. The depth of blocks in the mapping table generated by the method of the embodiment of the disclosure is different, so as to meet the requirements of the AArch32 execution state and the AArch64 execution state, reduce the area of the mapping table and improve the reading speed.
In one embodiment, the execution state of the processor includes a first execution state and a second execution state. Writing mapping data into a block corresponding to the mapping table according to the execution state of the processor, including: when the processor is in a first execution state, writing mapping data into the second block, the fourth block and the area with the second depth of the first block and the third block; when the processor is in the second execution state, the mapping data is written into the first block and the third block. The second depth area of the four blocks is used by the first execution state, i.e. the second and fourth blocks are all used by the first execution state, and the second depth portions of the first and third blocks are also used by the first execution state. The second execution state uses the first block and the third block, the depth of the second block and the fourth block meets the requirement of the first execution state, the first block and the third block meet the requirement of the second execution state, and the maximum depth does not need to be uniformly adopted.
In one embodiment, the first execution state is the AArch32 execution state and the second execution state is the AArch64 execution state.
In one embodiment, the second depth is one-half of the first depth. For example, the first depth is 32 rows and the second depth is 16 rows; or 16 rows for the first depth and 8 rows for the second depth.
Fig. 2 is a structural diagram of a mapping table according to an embodiment of the disclosure. Referring to fig. 2, the first to fourth blocks among the four blocks of the mapping table are bank0-3, respectively, wherein the depths of bank0 and bank2 are 16, the depths of bank1 and bank3 are 8, the execution states of AArch64 use bank0 and bank2, and the execution states of AArch32 use bank0, bank1, bank2 and bank 3. The AArch64 execution state and AArch32 execution state share the above mapping table, wherein the depth used by the AArch32 execution state is only 16 rows, therefore, bank1 and bank3 are all used by the AArch32 execution state, the first 16 bits of bank0 and bank2 are used by the AArch64 execution state and the AArch32 execution state, and the last 16 bits of bank0 and bank2 are expanded to be used by AArch 64.
Since the AArch32 execution state uses all of bank1 and bank3 and the first 16 bits of bank0 and bank2, the AArch64 execution state uses bank0 and bank2, where the first 16 bits are used in common with AArch32 and the last 16 bits are expanded to AArch64 execution state use. When the AArch64 execution state is switched to the AArch32 execution state, only the bank2 needs to be backed up, and the bank0 and the AArch32 execution state are commonly used. The logic cost is low.
In the AArch32 execution state, at most 64 physical registers maintain the mapping relationship with the logical registers, which is as follows:
1) 32S 0-S31
2) 16D 16-D31
3) 16Q 16~ Q31 (backup of AArch 64)
The mapping table requires 16 rows or 32 rows, and if 32 rows, the backup structure may not be needed. The reading speed is faster with 16 rows. As the S0-S31 of AArch32 only maps Q0-Q7, only 8 rows are needed for bank1 and bank3, and based on the above consideration, the method of the embodiment of the disclosure selects bank0 and bank3 to be set as 16 rows and bank1 and bank3 to be set as 8 rows.
Referring to fig. 3, an embodiment of the present disclosure provides an instruction execution method, where a mapping table involved in the instruction execution method of the embodiment of the present disclosure may be obtained by the mapping table generation method of the above embodiment, and descriptions of the embodiment of the mapping table generation method may be used to understand the instruction execution method of the embodiment of the present disclosure. The instruction execution method of the embodiment of the disclosure comprises the following steps:
acquiring a source register number of an instruction;
inquiring a mapping table according to the number to obtain a physical register corresponding to the source register;
the mapping table comprises four blocks, wherein the depth of a first block and a third block is a first depth, the depth of a second block and a fourth block is a second depth, and the first depth is greater than the second depth; and when the mapping table is inquired, inquiring the block corresponding to the mapping table according to the execution state of the processor.
In the instruction execution method of the present disclosure, the read mapping table includes four blocks, the depth of the first block and the third block is a first depth, the depth of the second block and the fourth block is a second depth, and the first depth is greater than the second depth; the corresponding physical register can be queried from the mapping table according to the source register number of the instruction, wherein the block corresponding to the mapping table is read according to the execution state of the processor. The mapping table blocks read by the method of the embodiment of the disclosure have different depths, so that the requirements of different execution states can be met, the area of the mapping table is reduced, and the reading speed is improved.
In one embodiment, the execution state of the processor includes a first execution state and a second execution state. According to the execution state of the processor, inquiring a block corresponding to the mapping table, wherein the method comprises the following steps: when the processor is in a first execution state, querying areas of a second depth of the second block, the fourth block and the first block and the third block; the processor queries the first block and the third block while in the second execution state.
In one embodiment, the first execution state is AArch32 and the second execution state is AArch 64.
In one embodiment, the second depth is one-half of the first depth. In one embodiment, the first depth is 32 rows and the second depth is 16 rows; or 16 rows for the first depth and 8 rows for the second depth.
Referring to fig. 4, an embodiment of the present disclosure provides a mapping table generating apparatus, which may implement the mapping table generating method of the foregoing embodiment, and the description of the embodiment of the mapping table generating method may be used to understand the mapping table generating apparatus of the embodiment of the present disclosure. The mapping table generating device of the embodiment of the disclosure includes: the device comprises a creating module, an obtaining module and a writing module, wherein the creating module is used for creating a mapping table, the mapping table comprises four blocks, the depth of a first block and a third block is a first depth, the depth of a second block and a fourth block is a second depth, and the first depth is larger than the second depth. The obtaining module is used for generating a request based on a mapping table and obtaining mapping data; and the writing module is used for writing the mapping data into a block corresponding to the mapping table according to the execution state of the processor.
In one embodiment, the execution state of the processor includes a first execution state and a second execution state. The writing module writes the mapping data into a block corresponding to the mapping table according to the execution state of the processor, and the writing module comprises: when the processor is in a first execution state, the writing module writes the mapping data into the second block, the fourth block and the area with the second depth of the first block and the third block; and when the processor is in the second execution state, the writing module writes the mapping data into the first block and the third block.
In one embodiment, the first execution state is the AArch32 execution state and the second execution state is the AArch64 execution state.
In one embodiment, the second depth is one-half of the first depth. For example, the first depth is 32 rows and the second depth is 16 rows; or 16 rows for the first depth and 8 rows for the second depth.
Referring to fig. 5, an instruction execution apparatus according to an embodiment of the present disclosure is provided, where the instruction execution apparatus according to the embodiment of the present disclosure may implement the instruction execution method according to the embodiment of the present disclosure, and the description of the embodiment of the instruction execution method may be used for understanding the instruction execution apparatus according to the embodiment of the present disclosure. The instruction execution device of the embodiment of the disclosure comprises an acquisition module and a query module, wherein the acquisition module is used for acquiring the source register number of an instruction; the query module is used for querying the mapping table according to the number to obtain a physical register corresponding to the source register; the mapping table comprises four blocks, wherein the depth of a first block and a third block is a first depth, the depth of a second block and a fourth block is a second depth, and the first depth is greater than the second depth; and when the mapping table is inquired, inquiring the block corresponding to the mapping table according to the execution state of the processor.
In one embodiment, the execution state of the processor includes a first execution state and a second execution state. The query module queries the block corresponding to the mapping table according to the execution state of the processor, and comprises: when the processor is in the first execution state, the query module queries the second block, the fourth block and the areas with the second depth of the first block and the third block; the query module queries the first block and the third block when the processor is in the second execution state.
In one embodiment, the first execution state is AArch32 and the second execution state is AArch 64.
In one embodiment, the second depth is one-half of the first depth. In one embodiment, the first depth is 32 rows and the second depth is 16 rows; or 16 rows for the first depth and 8 rows for the second depth.
The present disclosure also provides an electronic device and a readable storage medium according to an embodiment of the present disclosure.
FIG. 6 illustrates a schematic block diagram of an example electronic device 600 that can be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the disclosure described and/or claimed herein.
As shown in fig. 6, the apparatus 600 includes a computing unit 601, which can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 602 or a computer program loaded from a storage unit 608 into a Random Access Memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the device 600 can also be stored. The calculation unit 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.
A number of components in the device 600 are connected to the I/O interface 605, including: an input unit 606 such as a keyboard, a mouse, and the like; an output unit 607 such as various types of displays, speakers, and the like; a storage unit 608, such as a magnetic disk, optical disk, or the like; and a communication unit 609 such as a network card, modem, wireless communication transceiver, etc. The communication unit 609 allows the device 600 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.
The computing unit 601 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various dedicated Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, and so forth. The calculation unit 601 performs the respective methods and processes described above, such as a mapping table generation method or an instruction execution method. For example, in some embodiments, the mapping table generation method or the instruction execution method may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 608. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 600 via the ROM 602 and/or the communication unit 609. When a computer program is loaded into RAM 603 and executed by the computing unit 601, one or more steps of the mapping table generation method or instruction execution method described above may be performed. Alternatively, in other embodiments, the calculation unit 601 may be configured by any other suitable means (e.g. by means of firmware) to perform the mapping table generation method or the instruction execution method.
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), and the Internet.
The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server with a combined blockchain.
It should be understood that various forms of the flows shown above, reordering, adding or deleting steps, may be used. For example, the steps described in the present disclosure may be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved, and the present disclosure is not limited herein.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (12)
1. A mapping table generating method, the method comprising:
establishing a mapping table, wherein the mapping table comprises four blocks, the depth of a first block and a third block is a first depth, the depth of a second block and a fourth block is a second depth, and the first depth is greater than the second depth;
generating a request based on a mapping table, and acquiring mapping data;
writing the mapping data into a block corresponding to the mapping table according to the execution state of the processor; wherein the content of the first and second substances,
the execution state of the processor comprises a first execution state and a second execution state;
writing the mapping data to an area of a second depth of the second block, the fourth block, and the first block and the third block while the processor is in a first execution state;
and when the processor is in a second execution state, writing the mapping data into the first block and the third block.
2. The method of claim 1, wherein the first execution state is an AArch32 execution state and the second execution state is an AArch64 execution state.
3. The method of claim 1, wherein the second depth is one-half of the first depth.
4. The method of claim 3, wherein the first depth is 32 rows and the second depth is 16 rows; or
The first depth is 16 rows and the second depth is 8 rows.
5. A method of instruction execution, the method comprising:
acquiring a source register number of an instruction;
inquiring a mapping table according to the number to obtain a physical register corresponding to the source register;
the mapping table comprises four blocks, wherein the depth of a first block and a third block is a first depth, the depth of a second block and a fourth block is a second depth, and the first depth is greater than the second depth; when the mapping table is inquired, inquiring a block corresponding to the mapping table according to the execution state of the processor; wherein the content of the first and second substances,
the execution state of the processor comprises a first execution state and a second execution state;
when the processor is in a first execution state, querying areas of a second depth of the second block, the fourth block and the first block and the third block;
and when the processor is in a second execution state, querying the first block and the third block.
6. The method of claim 5, wherein the first execution state is an AArch32 execution state and the second execution state is an AArch64 execution state.
7. The method of claim 5, wherein the second depth is one-half of the first depth.
8. The method of claim 7, wherein the first depth is 32 rows and the second depth is 16 rows; or
The first depth is 16 rows and the second depth is 8 rows.
9. An apparatus for generating a mapping table, the apparatus comprising:
the mapping table comprises four blocks, wherein the depth of a first block and a third block is a first depth, the depth of a second block and a fourth block is a second depth, and the first depth is greater than the second depth;
the obtaining module is used for generating a request based on a mapping table and obtaining mapping data;
a writing module, configured to write the mapping data into a block corresponding to the mapping table according to an execution state of the processor; the execution state of the processor comprises a first execution state and a second execution state; writing the mapping data to an area of a second depth of the second block, the fourth block, and the first block and the third block while the processor is in a first execution state; and when the processor is in a second execution state, writing the mapping data into the first block and the third block.
10. An instruction execution apparatus, comprising:
the obtaining module is used for obtaining the source register number of the instruction;
the query module is used for querying a mapping table according to the number to obtain a physical register corresponding to the source register; the mapping table comprises four blocks, wherein the depths of a first block and a third block are first depths, the depths of a second block and a fourth block are second depths, and the first depths are greater than the second depths; when the mapping table is inquired, inquiring a block corresponding to the mapping table according to the execution state of the processor; the execution state of the processor comprises a first execution state and a second execution state; when the processor is in a first execution state, querying areas of a second depth of the second block, the fourth block and the first block and the third block; and when the processor is in a second execution state, querying the first block and the third block.
11. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.
12. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method according to any one of claims 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210626925.1A CN114707478B (en) | 2022-06-06 | 2022-06-06 | Mapping table generation method, device, equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210626925.1A CN114707478B (en) | 2022-06-06 | 2022-06-06 | Mapping table generation method, device, equipment and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114707478A CN114707478A (en) | 2022-07-05 |
| CN114707478B true CN114707478B (en) | 2022-09-02 |
Family
ID=82177927
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210626925.1A Active CN114707478B (en) | 2022-06-06 | 2022-06-06 | Mapping table generation method, device, equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114707478B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104102586A (en) * | 2013-04-15 | 2014-10-15 | 中兴通讯股份有限公司 | Address mapping processing method and address mapping processing device |
| CN106681654A (en) * | 2016-09-29 | 2017-05-17 | 合肥兆芯电子有限公司 | Mapping table loading method and memory storage device |
| CN107526693A (en) * | 2017-08-11 | 2017-12-29 | 致象尔微电子科技（上海）有限公司 | A kind of internal memory partition method based on Linear Mapping table |
| CN107667364A (en) * | 2015-06-04 | 2018-02-06 | 微软技术许可有限责任公司 | Use the atomic update of hardware transaction memory control index |
| CN109408403A (en) * | 2018-10-12 | 2019-03-01 | 深圳市硅格半导体有限公司 | Mapping method, device, system and storage medium based on storage equipment bottom |
| CN110413228A (en) * | 2019-07-09 | 2019-11-05 | 江苏芯盛智能科技有限公司 | A kind of mapping table management method, system and electronic equipment and storage medium |
| CN111124309A (en) * | 2019-12-22 | 2020-05-08 | 浪潮电子信息产业股份有限公司 | Method, device and equipment for determining fragmentation mapping relation and storage medium |
| CN112765993A (en) * | 2021-01-20 | 2021-05-07 | 上海德拓信息技术股份有限公司 | Semantic parsing method, system, device and readable storage medium |
| CN112882663A (en) * | 2021-03-25 | 2021-06-01 | 湖南国科微电子股份有限公司 | Random writing method, electronic equipment and storage medium |
| CN113220221A (en) * | 2020-02-06 | 2021-08-06 | 瑞昱半导体股份有限公司 | Memory controller and data processing method |
| CN113555057A (en) * | 2021-07-26 | 2021-10-26 | 成都储迅科技有限责任公司 | Implementation method for expanding solid state disk mapping table unit |
| CN114450672A (en) * | 2020-11-06 | 2022-05-06 | 深圳市大疆创新科技有限公司 | Access control method and device of memory and storage medium |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11403217B2 (en) * | 2019-10-30 | 2022-08-02 | Qualcomm Incorporated | Memory bank group interleaving |
| CN113821834B (en) * | 2021-11-24 | 2022-02-15 | 飞腾信息技术有限公司 | Data processing method, security architecture system and computing device |
-
2022
- 2022-06-06 CN CN202210626925.1A patent/CN114707478B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104102586A (en) * | 2013-04-15 | 2014-10-15 | 中兴通讯股份有限公司 | Address mapping processing method and address mapping processing device |
| CN107667364A (en) * | 2015-06-04 | 2018-02-06 | 微软技术许可有限责任公司 | Use the atomic update of hardware transaction memory control index |
| CN106681654A (en) * | 2016-09-29 | 2017-05-17 | 合肥兆芯电子有限公司 | Mapping table loading method and memory storage device |
| CN107526693A (en) * | 2017-08-11 | 2017-12-29 | 致象尔微电子科技（上海）有限公司 | A kind of internal memory partition method based on Linear Mapping table |
| CN109408403A (en) * | 2018-10-12 | 2019-03-01 | 深圳市硅格半导体有限公司 | Mapping method, device, system and storage medium based on storage equipment bottom |
| CN110413228A (en) * | 2019-07-09 | 2019-11-05 | 江苏芯盛智能科技有限公司 | A kind of mapping table management method, system and electronic equipment and storage medium |
| CN111124309A (en) * | 2019-12-22 | 2020-05-08 | 浪潮电子信息产业股份有限公司 | Method, device and equipment for determining fragmentation mapping relation and storage medium |
| CN113220221A (en) * | 2020-02-06 | 2021-08-06 | 瑞昱半导体股份有限公司 | Memory controller and data processing method |
| CN114450672A (en) * | 2020-11-06 | 2022-05-06 | 深圳市大疆创新科技有限公司 | Access control method and device of memory and storage medium |
| CN112765993A (en) * | 2021-01-20 | 2021-05-07 | 上海德拓信息技术股份有限公司 | Semantic parsing method, system, device and readable storage medium |
| CN112882663A (en) * | 2021-03-25 | 2021-06-01 | 湖南国科微电子股份有限公司 | Random writing method, electronic equipment and storage medium |
| CN113555057A (en) * | 2021-07-26 | 2021-10-26 | 成都储迅科技有限责任公司 | Implementation method for expanding solid state disk mapping table unit |
Non-Patent Citations (2)
| Title |
|---|
| "Half-DRAM: a High-bandwidth and Low-power DRAM Architecture from the Rethinking of Fine-grained Activation";Tao Zhang等;《ACM SIGARCH Computer Architecture News》;20141231;第1-12页 * |
| "优化内存系统能效的DRAM架构研究综述";展旭升等;《高技术通讯》;20181231;第28卷(第9-10期);第794-812页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114707478A (en) | 2022-07-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111090628A (en) | Data processing method and device, storage medium and electronic equipment | |
| JP7096213B2 (en) | Calculation method applied to artificial intelligence chip and artificial intelligence chip | |
| EP3832493B1 (en) | Method, apparatus, electronic device and readable storage medium for data query | |
| CN113900966B (en) | Access method and device based on Cache | |
| CN114120414B (en) | Image processing method, image processing apparatus, electronic device, and medium | |
| CN111737564A (en) | Information query method, device, equipment and medium | |
| CN117236236B (en) | Chip design data management method and device, electronic equipment and storage medium | |
| CN114707478B (en) | Mapping table generation method, device, equipment and storage medium | |
| CN114743586B (en) | Mirror image storage implementation method and device of storage model and storage medium | |
| CN114816393B (en) | Information generation method, device, equipment and storage medium | |
| CN113656330B (en) | Method and device for determining access address | |
| CN115859749A (en) | Constraint building method and device of three-dimensional model, electronic equipment and storage medium | |
| CN113656331A (en) | Method and device for determining access address based on high and low bits | |
| CN107291628B (en) | Method and apparatus for accessing data storage device | |
| CN117271840B (en) | Data query method and device of graph database and electronic equipment | |
| CN115599307B (en) | Data access method, device, electronic equipment and storage medium | |
| CN113986134B (en) | Method for storing data, method and device for reading data | |
| CN113434508B (en) | Method and apparatus for storing information | |
| CN115617732B (en) | APB bus structure, system on chip, vehicle and access method | |
| CN116048816B (en) | Data request processing method, device, electronic equipment and storage medium | |
| CN113051491B (en) | Map data processing method, apparatus, storage medium, and program product | |
| CN116468711A (en) | Parameter setting method and device, electronic equipment and storage medium | |
| CN117764012A (en) | Circuit and circuit gate level netlist optimization method | |
| CN116383333A (en) | Data storage method, device, equipment and storage medium | |
| CN115033823A (en) | Method, apparatus, device, medium and product for processing data |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |