CN107526693A - A kind of internal memory partition method based on Linear Mapping table - Google Patents
A kind of internal memory partition method based on Linear Mapping table Download PDFInfo
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- CN107526693A CN107526693A CN201710686477.3A CN201710686477A CN107526693A CN 107526693 A CN107526693 A CN 107526693A CN 201710686477 A CN201710686477 A CN 201710686477A CN 107526693 A CN107526693 A CN 107526693A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
- G06F12/1483—Protection against unauthorised use of memory or access to memory by checking the subject access rights using an access-table, e.g. matrix or list
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Abstract
The present invention relates to a kind of internal memory partition method based on Linear Mapping table, including：Obtain the physical address of the status information for the access equipment for initiating memory access request and the internal memory of request access；Linear mapping table is inquired about according to physical address, the Linear Mapping table includes several list items, and several list items correspond with the internal memory in units of fixed size blocks, and includes the security attribute of corresponding memory block；Carry out whether ruling allows this internal storage access according to access equipment status information, physical address and Query Result.The present invention can set the secure memory section of arbitrary size and any number, not limited by hardware circuit, improve the flexibility of secure memory by way of software and hardware combining；Meanwhile by the extension to Linear Mapping table, the Authorization Attributes in each secure memory section can be set, user can customize Authorization Attributes, and secure memory is carried out into more fine-grained division, enriches secure memory attribute, and then improve the security of system.
Description
Technical field
The present invention relates to internal memory safety method, more particularly, to a kind of secure memory method based on internal memory isolation.
Background technology
With being widely popularized for the safety services such as mobile payment, Mobile banking, digital publishing rights, safety plays in end equipment
Highly important effect.End equipment based on ARM frameworks is each in mobile phone, flat board, wearable device, smart machine, sensor etc.
Individual field has a wide range of applications.In secure context, what most of chip factory commercial cities were provided based on ARMTechnology
Realize the security solution of oneself.However,Primarily directed to CPU hardware isolated technology, can not protect interior
The safety of data such as deposit, store.Current chip factory commercial city major on the market extends the hardware of secure memory in the SoC of oneself
Scheme, while ARM also provides the security IP of TZASC, TZMA two and realizes safety in data storage.In most of safety
The scheme of depositing is realized by hardware logic electric circuit, wherein the number in the secure memory section that can be supported, and each security interval
Granule size limited extremely, very big limits use of the software to these secure memory sections；Also, hardware logic electricity
The secure memory attribute that road is realized only supports secure and non-secure two kinds, and security interval inside more specifically can not be drawn
Point；
The content of the invention
Present invention is generally directed to a kind of internal memory partition method based on Linear Mapping table, suitable for solution foregoing problems and
Know other problemses, shortcoming and the limitation of technology.This hair is using in a kind of safety based on hardware logic electric circuit and Linear Mapping table
Scheme is deposited, the secure memory section of arbitrary size and any number can be set, do not limited by hardware circuit；Meanwhile according to
Linear Mapping tableau format, the authority and attribute in each secure memory section can be set, secure memory is subjected to more particulate
The division of degree.
To achieve the above object, the invention provides a kind of internal memory partition method based on Linear Mapping table, including：Obtain
Initiate the physical address of the status information of the access equipment of memory access request and the internal memory of request access.According to physical address
Inquire about linear mapping table LMAT, Linear Mapping table LMAT includes several list items, several list items with using fixed size blocks as
The internal memory of unit corresponds, and includes the security attribute of corresponding memory block.According to access equipment status information, physical address
Carry out whether ruling allows to access with Query Result.
Preferably, access equipment is CPU, and access state information includes：Whether CPU is in a safe condition.Security attribute bag
Include：It can be accessed by the CPU of non-secure states.
Preferably, ruling includes, in the case where CPU is in a safe condition, it is allowed to accesses；Or CPU is in non-security
State, and the security attribute in Query Result then allows to access for that can be accessed by the CPU of non-secure states.
Preferably, security attribute also includes：It can be read or write by the CPU of non-secure states.
Preferably, access equipment status information also includes：CPU thread tag (Thread ID).Security attribute also wraps
Include：Allow the thread tag (Thread ID) for accessing corresponding memory block.
Preferably, access equipment also includes：Direct memory access DMA and graphics processor GPU.
Preferably, access equipment status information also includes：The device label of access equipment and the direct internal memory of access equipment
Access path DMA Channel.Security attribute also includes：Allow to access the device label of corresponding memory block and allow access pair
Answer the direct memory access passage DMA Channel of memory block.
Preferably, Linear Mapping table LMAT data renewal, is completed by the CPU under safe condition.
Preferably, Linear Mapping table LMAT is stored in Installed System Memory, and Linear Mapping table LMAT is by the memory headroom of occupancy
The security attribute of list item corresponding to block is arranged to safety.
Preferably, the above method is performed by hardware rights management logic circuit MPMU, and method also includes, by Linear Mapping table
List item in LMAT is buffered in rights management logic circuit MPMU.
The present invention is by way of software and hardware combining, it is possible to achieve the secure memory section of arbitrary size and any number,
Improve the flexibility of secure memory；Pass through the extension to Linear Mapping attribute list, it is possible to achieve abundant secure memory attribute,
Such as the delineation of power based on CPU different threads can be realized, and then improve the security of system.
Brief description of the drawings
Fig. 1 is a kind of internal memory partition method flow chart based on Linear Mapping table provided in an embodiment of the present invention；
Fig. 2 is the schematic diagram for the system that internal memory partition method is realized according to one embodiment of the invention；
Fig. 3 is the schematic diagram for the system that internal memory partition method is realized according to another embodiment of the present invention；
Fig. 4 is the list item schematic diagram according to the Linear Mapping table of one embodiment；
Fig. 5 is the list item schematic diagram according to the Linear Mapping table of another embodiment；
Fig. 6 is the schematic diagram according to the Linear Mapping table of one embodiment；
Fig. 7 is the schematic diagram for the system that internal memory partition method is realized according to one embodiment.
Embodiment
Below by drawings and examples, technical scheme is described in further detail.
As shown in figure 1, it is a kind of internal memory partition method flow chart based on Linear Mapping table provided in an embodiment of the present invention.
This method includes：Step S1, the status information and request for obtaining the access equipment for initiating memory access request are visited
The physical address for the internal memory asked；Step S2, linear mapping table LMAT, Linear Mapping table LMAT bags are inquired about according to the physical address
Containing several list items, several list items correspond with the internal memory in units of fixed size blocks, and include corresponding memory field
The security attribute of block；Step S3, ruling is carried out according to the status information of the access equipment, the physical address and Query Result
Whether allow to access.
A kind of internal memory partition method based on Linear Mapping table provided by the invention is illustrated with reference to Fig. 2.
As shown in Fig. 2 to realize the schematic diagram of the system of internal memory partition method according to one embodiment of the invention.
In the embodiment of fig. 2, access equipment is CPU 101.When CPU 101 initiates memory access request, virtually
Location is converted to physical address by virtual address map unit MMU 102.The process of the conversion may relate to TLB inquiry,
Inquiry of page table etc..Then, in step S1, rights management logic circuit (Memory Permission Management
Unit, abbreviation MPMU) 103 get the physical address after the conversion.Also, MPMU 103 also obtains CPU 101 safe shape
State secure state (safe S or non-security NS).Then, looked into step S2, MPMU 103 according to accessed physical address
Ask a Linear Mapping table (Linear Map Attribute Table, abbreviation LMAT) 104.In step S3, the power of conducting interviews
The ruling of limit, and according to the result of ruling, it is allowed to or refuse this internal storage access.List item mapping internal memory in LMAT 104
In a block, and contain the security attribute of the block.In one embodiment, the i.e. corresponding memory field of the security attribute
Block is secure memory or non-security internal memory.The CPU 101 of 104 permission safe conditions of LMAT carries out data renewal.
In the fig. 3 embodiment, forms of the MPMU 103 in whole on-chip system SoC is unrestricted, or with independent
Module is present, or is present in the form of submodule, subfunction in existing module.Fig. 2 is a kind of MPMU 103 with standalone module
Existing schematic diagram, Fig. 3 are the schematic diagrames that a kind of MPMU 103 is present in Memory Controller Hub unit (MCU) 105 with submodule.
In step S3, MPMU 103 has three class input signals, and the first kind is to send the status informations of CPU 101 of internal storage access, such as：
CPU 101 prerogative grade, safe condition, ASID etc.；This kind of input is directly obtained by SoC internal signals to MPMU 103, or
Obtained by MPMU 103 by reading register；Second class is the physical address information of accessed internal memory, and this kind of input can be straight
Connect and obtained from memory access signals；3rd class is Linear Mapping table LMAT 104.Internal storage access power is contained in MPMU 103
The ruling logic of limit, allowed according to this three classes input signal or refuse the access to internal memory.Because MPMU 103 is sent out CPU 101
Any memory access request gone out can all inquire about LMAT 104 and carry out authority ruling, to accelerate visits of the MPMU 103 to LMAT 104
Speed is asked, in one embodiment, a set of caching mechanism is realized inside MPMU 103, the list items of LMAT 104 that will frequently use
Cache to MPMU 103, to accelerate MPMU 103 ruling speed.
Fig. 4 is the list item schematic diagram for the Linear Mapping table that one embodiment of the invention provides.
LMAT 104 is mapped the internal memory in units of a block.Block is a continuous physical memory piece
Section, its size can be different according to design, for example, can be using a Physical Page as a block in canonical system.LMAT
104 and internal memory 106 mapping relations it is as follows：
1st, internal memory, according to physical address according to ascending order or backward order, can be divided into 1 in units of block --- and n
Block；
2nd, the list item in LMAT 104 can be expressed as list item 1 from Section 1 to last --- list item N；
3rd, LMAT 104 list item 1 --- list item N maps memory block 1 respectively --- n；
4th, the security attribute of corresponding memory block is contained in each list item in LMAT 104, i.e. access rights are believed
Breath.
LMAT 104 size is by a list item index in Installed System Memory size, memory block size and LMAT 104
Size together decide on, circular is：
Given any physical address physical_address, can calculate the physical address in LMAT104
List item index sizes, circular are：
Divided it should be noted that this calculation formula is only applicable to physical address according to ascending order.
The security attribute information needed for MPMU 103 is contained in list item in LMAT 104.One simple security attribute
Information format is, with 1bit represent corresponding to memory block whether can be accessed by the CPU 101 of non-security NS states：0 represents
The internal memory can be accessed by the CPU 101 of non-security NS states；1, which represents this, to be visited by the CPU 101 of non-security NS states
Ask, the CPU 101 of only safe condition could access the internal memory.
Fig. 4 is the schematic diagram that a contents in table in LMAT 104 is represented with 2bits.Bit0 (R) indicates whether to forbid NS
The CPU of state is read, and bit1 (W) represents the CPU write for whether forbidding NS states.Table 1 is the internal memory security attribute piece based on the example
Lift.
| Authority describes | bit0(R) | bit1(W) |
| NS is readable, writeable | 0 | 0 |
| NS is read-only, not writeable | 0 | 1 |
| NS only writes, unreadable | 1 | 0 |
| NS is unreadable, not writeable | 1 | 1 |
Table 1：Authority description based on R, W bit
Fig. 5 is the list item schematic diagram according to the Linear Mapping table of another embodiment.
The form of the list items of LMAT 104 can be extended according to demand.Fig. 5 is the increase thread tags of CPU 101
Thread id informations.MPMU 103 can be according to the current CPU 101 for initiating internal storage access Thread ID and LMAT 104
In Thread ID contrasted, matching then illustrate that the internal memory belongs to current thread Thread, it is allowed to access；Mismatch then
Illustrate that current Thread is attempting to access that another Thread physical memory, denied access.Increasing Thread ID can be from
Ensure that different Thread have different physical memory spaces on hardware, increase the security of system.
Fig. 6 is the schematic diagram according to the Linear Mapping table of one embodiment.
In the present invention, it is necessary to preserve LMAT 104 using the continuous internal memory of one piece of physics.Position residing for the contiguous memory
Put unrestricted, be present in on-chip system SoC piece in static RAM SRAM, or directly from Installed System Memory
Reserved in 106.Meanwhile in order to increase LMAT 104 security, prevent malicious code distorting to LMAT 104, LMAT
Physical memory shared by 104 only allows the CPU 101 of safe condition to modify.If the physical memory that LMAT 104 takes
For SoC on-chip SRAM, then hardware circuit is needed to ensure that the SRAM only allows the CPU 101 of safe condition to change；If LMAT
104 take in save as what is reserved from Installed System Memory, then need when system starts in configuration LMAT 104 shared by itself
Physical memory is secure memory.Fig. 6 is a kind of schematic diagram that LMAT 104 uses internal memory to be reserved from Installed System Memory.Figure
In as an example, from the end of Installed System Memory reserve 9 blocks as the spaces of LMAT 104, then initialized to LMAT 104
When, it is necessary to by the security attribute of 9 list items at end be arranged to safety, to show 9 blocks at end as secure memory.
In a specific example, it is assumed that Installed System Memory is 2G (2147483648bytes), the initial address of Installed System Memory
For 0x10000000.It is 4K (4096bytes) that memory block size is set in the present embodiment, it is assumed that LMAT is stored in Installed System Memory
In, shared memory headroom maps memory block since the initial address of Installed System Memory in the way of ascending order, and uses
R, W 2bit entry format are included shown in Fig. 4, then：
LMAT list item number is：2147483648bytes/4096bytes=524288
LMAT size is：524288 × 2bits=131072bytes=128K
LMAT itself take list item number be：131072bytes/4096bytes=32
Therefore, it is necessary to which LMAT preceding 32 index are arranged into binary one 1 during system initialization, you can to pass through
Initialized (0xff includes 4 binary ones 1, therefore only needs 32/4=8 0xff) with minor function：memset
(0x10000000,0xff,8)。
It is to LMAT list item sizes corresponding to the address of any physical address：(address-0x10000000)/
4096bytes。
Fig. 7 is the system schematic that internal memory partition method is realized according to one embodiment.
The access equipment that memory access request is sent due to step S1 is not only limited to CPU 101, in step s3, in order to
Preventing direct memory access DMA, graphics processor GPU and Digital Signal Processing DSP etc., other can directly carry out internal storage access
Destruction of the access equipment to the internal memory rules of competence of MPMU 103, MPMU 103 is also required to receive in addition to CPU 101 simultaneously
The status information of these access equipments, and according to the status information of these access equipments, memory address and LMAT 104 come ruling
Access to internal memory.Different device labels, the status information obtained in step sl are configured for different access equipments first
Middle storage.In step s3, whether comparative apparatus label is correct, and the access equipment only to match could allow to access.For
DMA also relates to direct memory access passage (DMA channel), when access equipment is DMA, also need to judge DMA channel whether
Match somebody with somebody, the DMA channel only matched could allow to access.So MPMU 103 can be carried out to access of any access equipment to internal memory
Ruling, add the security of whole system.
Above-described embodiment, the purpose of the present invention, technical scheme and beneficial effect are carried out further
Describe in detail, should be understood that the embodiment that the foregoing is only the present invention, be not intended to limit the present invention
Protection domain, within the spirit and principles of the invention, any modification, equivalent substitution and improvements done etc., all should include
Within protection scope of the present invention.
Claims (10)
1. a kind of internal memory partition method based on Linear Mapping table, it is characterised in that method includes：
Obtain the physical address of the status information for the access equipment for initiating memory access request and the internal memory of request access；
Linear mapping table (LMAT) (104) is inquired about according to the physical address, the Linear Mapping table (LMAT) (104) is if include
Dry list item, several described list items correspond with the internal memory in units of fixed size blocks, and include corresponding memory field
The security attribute of block；
The memory block is the cell block for being divided Installed System Memory in units of fixed size；
List item in the Linear Mapping table (LMAT) (104) maps one by one in a linear fashion with memory block；
Carry out whether ruling allows to access according to the status information of the access equipment, the physical address and Query Result.
2. according to the method for claim 1, it is characterised in that the access equipment is CPU (101), the shape of access equipment
State information includes：Whether CPU (101) is in a safe condition；The security attribute includes：Can be by the CPU of non-secure states
(101) access.
3. according to the method for claim 2, it is characterised in that the ruling includes, in a safe condition in CPU (101)
In the case of, it is allowed to access；Or it is in non-secure states in CPU (101), and the security attribute in Query Result is can be with
In the case of being accessed by the CPU (101) of non-secure states, it is allowed to access.
4. according to the method for claim 2, it is characterised in that the security attribute also includes：Can be by non-secure states
CPU (101) read or write.
5. according to the method for claim 4, it is characterised in that the status information of the access equipment also includes：CPU
(101) thread tag (Thread ID)；
The security attribute also includes：Allow the thread tag (Thread ID) for accessing corresponding memory block.
6. according to the method for claim 1, it is characterised in that the access equipment also includes：Direct memory access (DMA)
And graphics processor (GPU) (602) (601).
7. according to the method for claim 6, it is characterised in that the status information of the access equipment also includes：The visit
Ask the main equipment label of equipment and the direct memory access passage (DMA Channel) of access equipment；
The security attribute also includes：Allow to access the device label of corresponding memory block and allow to access corresponding memory block
Direct memory access passage (DMA Channel).
8. according to the method for claim 1, it is characterised in that the data renewal of the Linear Mapping table (LMAT) (104),
Completed by the CPU (101) under safe condition.
9. according to the method for claim 1, it is characterised in that the Linear Mapping table (LMAT) (104) is stored in system
In internal memory, the Linear Mapping table (LMAT) (104) sets the security attribute of list item corresponding to the memory headroom block of occupancy
For safety.
10. according to the method for claim 1, it is characterised in that methods described is by hardware rights management logic circuit
(MPMU) (103) perform, and methods described also includes, and the list item in Linear Mapping table (LMAT) (104) is buffered in into the authority
Manage in logic circuit (MPMU) (103).
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| CN108491716A (en) * | 2018-01-29 | 2018-09-04 | 中国电子科技网络信息安全有限公司 | A kind of virutal machine memory isolation detection method based on physical page address analysis |
| CN109815737A (en) * | 2019-01-30 | 2019-05-28 | 山东华芯半导体有限公司 | A kind of single-deck multi-user's physical isolation method based on address of cache |
| WO2019183831A1 (en) * | 2018-03-28 | 2019-10-03 | Intel Corporation | Address space identifier management in complex input/output virtualization environments |
| CN110825492A (en) * | 2019-10-31 | 2020-02-21 | 海光信息技术有限公司 | Method, device, equipment and storage medium for isolating secure data memory |
| CN111258935A (en) * | 2018-11-30 | 2020-06-09 | 上海寒武纪信息科技有限公司 | Data transmission device and method |
| CN111857947A (en) * | 2020-06-11 | 2020-10-30 | 海光信息技术有限公司 | Memory isolation method, isolation check circuit and CPU chip |
| CN114707478A (en) * | 2022-06-06 | 2022-07-05 | 飞腾信息技术有限公司 | Mapping table generation method, device, equipment and storage medium |
| CN116150740A (en) * | 2023-04-17 | 2023-05-23 | 杭州鸿钧微电子科技有限公司 | Resource isolation method and device, chip system and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108491716A (en) * | 2018-01-29 | 2018-09-04 | 中国电子科技网络信息安全有限公司 | A kind of virutal machine memory isolation detection method based on physical page address analysis |
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| CN114707478A (en) * | 2022-06-06 | 2022-07-05 | 飞腾信息技术有限公司 | Mapping table generation method, device, equipment and storage medium |
| CN114707478B (en) * | 2022-06-06 | 2022-09-02 | 飞腾信息技术有限公司 | Mapping table generation method, device, equipment and storage medium |
| CN116150740A (en) * | 2023-04-17 | 2023-05-23 | 杭州鸿钧微电子科技有限公司 | Resource isolation method and device, chip system and electronic equipment |
| CN116150740B (en) * | 2023-04-17 | 2023-12-12 | 杭州鸿钧微电子科技有限公司 | Resource isolation method and device, chip system and electronic equipment |
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