WO2014169690A1

WO2014169690A1 - Method and device for processing address mapping

Info

Publication number: WO2014169690A1
Application number: PCT/CN2013/090967
Authority: WO
Inventors: 黄苏
Original assignee: 中兴通讯股份有限公司
Priority date: 2013-04-15
Filing date: 2013-12-30
Publication date: 2014-10-23
Also published as: CN104102586B; CN104102586A

Abstract

Disclosed are a method and device for processing address mapping. The method comprises: according to the number of double data rate synchronous dynamic random access memories (DDRs) which are configured currently, partitioning a logical address; and according to the logical address of each partitioned range segment, performing mapping processing between the logical address and a physical address respectively. A mapping processing unit of the device is configured to perform mapping processing between a logical address and a physical address respectively according to the logical address of each partitioned range segment. By means of the present invention, RAM resources are saved, and a physical address can also be managed efficiently.

Description

Method and device for address mapping processing

The present invention relates to address mapping technology in the field of data communication, and in particular, to a method and apparatus for address mapping processing. Background technique

Double Data Rate Synchronous Random Access Memory (DDRSDRAM) is a new generation of memory technology standards issued by the Joint Commission on Electronic Equipment (JEDEC) and 2004. Due to its low price, high bandwidth data throughput and low power consumption, DDR SDRAM is widely used in the field of data communication where storage is demanding. However, in the field of data communication chips, the chip's key performance index is the number of packets per second (PPS), which determines that the DDR SDRAM used for packet buffering must achieve the lowest read and write efficiency to meet the processing power of the chip. At the same time, because of cost factors, it is not possible to increase the data throughput of the entire chip simply by increasing the number of physical slices of DDR SDRAM.

DDR SDRAM is widely used in the field of data communication chips. It is used to buffer packet data during message processing. It is currently the third generation of DDR, namely DDR3 SDRAM. This article is referred to as DDR3. The general processing mode of the data communication chip is as follows: After the data packet is processed by the MAC layer, the packet is first buffered into the off-chip DDR3 chip, and the DDR3 physical address of the buffered data packet is generated, and is continued as part of the packet characteristic information. Protocol and handling of QoS functions. For Ethernet data packets, the minimum length of the packet is 64B. At the same time, the current DDR3 burst address width is 16B. You can see that at least 4 burst addresses are required for a data packet. If the DDR3 physical address of the data packet is directly used as its The feature information needs to carry at least 4 physical addresses, resulting in an increase in resources.

In order to reduce overhead, the prior art generally adopts a logical address as a feature of a packet cache address. Information, a logical address represents a number of DDR3 physical addresses. This scheme requires a mapping relationship between the logical address and the physical address of DDR3. However, the problem with the prior art is: The solution wastes RAM resources and does not enable efficient management of physical addresses. Summary of the invention

In view of this, the main purpose of the embodiments of the present invention is to provide a method and an apparatus for address mapping processing, which not only saves RAM resources, but also implements efficient management of physical addresses.

To achieve the above objective, the technical solution of the embodiment of the present invention is implemented as follows:

A method for address mapping processing, the method comprising:

Synchronous random access memory DDR number to logical address partition according to the currently configured double data rate;

The mapping between the logical address and the physical address is performed according to the logical addresses of the interval segments after the partition.

The partitioning the logical address according to the currently configured number of DDRs specifically includes: obtaining a total physical bank number according to the number of DDRs and the number of physical bank banks included in each DDR;

The total logical address is divided into a plurality of logical address segments, and the number of segments is a maximum value of 2n among all the common divisors of the total physical bank number, and the n refers to the number of linked lists in the segment.

The mapping between the logical address and the physical address according to the logical addresses of the interval segments after the partitioning includes:

In the case of a value of 2n, each logical address segment corresponds to a physical bank, and is a one-to-one mapping between a logical address and a physical address;

When the value is not 2n, each logical address segment corresponds to multiple physical banks, which is a one-to-many mapping between logical addresses and physical addresses.

The method further includes: configuring, in the one-to-many mapping, each segment of the physical bank Offset base address, the number of offset base addresses in the segment is nl.

The method further includes: obtaining, according to the offset base address and the intra-segment offset address in the segment, an intra-segment offset physical bank address corresponding to the intra-segment offset address.

The method further includes: obtaining a corresponding physical row address and a physical column address according to the offset physical bank address in the segment.

An apparatus for address mapping processing, the apparatus comprising: a partition processing unit and a mapping processing unit; wherein

The partition processing unit is configured to partition the logical address according to the currently configured DDR number; the mapping processing unit is configured to perform mapping processing between the logical address and the physical address according to the logical addresses of the interval segments after the partition.

The partition processing unit and the mapping processing unit use a central processing unit (CPU) and a digital signal processor (DSP, Digital Singnal) when performing processing.

Processor ) or Programmable Array ¹ J (FPGA, Field - Programmable Gate Array) implementation.

The partition processing unit is further configured to obtain a total physical bank number according to the number of DDRs and the number of physical bank banks included in each DDR, and divide the total logical address into multiple logical address segments, and segment the segments. The number is the maximum value of 2n among all the common divisors of the total physical bank number, and the n refers to the number of linked lists in the segment.

Wherein, the mapping processing unit is further configured to have a value of 2n, and if each logical address segment corresponds to one physical bank, the one-to-one mapping between the logical address and the physical address; when the value is not 2n, Making each logical address segment correspond to multiple physical banks is a one-to-many mapping between logical addresses and physical addresses.

Wherein, the mapping processing unit is further configured to configure an intra-segment offset base address for each physical bank when the one-to-many mapping is performed, and the number of the offset base addresses in the segment is n-1; Offset base address and intra-segment offset address, get the intra-segment offset physical bank location corresponding to the offset address within the segment Address: obtaining a corresponding physical row address and a physical column address according to the offset physical bank address in the segment. The solution of the embodiment of the present invention partitions the logical address according to the currently configured DDR number; and performs mapping processing between the logical address and the physical address according to the logical address of each interval segment after the partition. The embodiment of the present invention does not directly map the logical address to the physical address for the total logical address, but performs the mapping processing after the total logical address is partitioned, thereby reducing the occupation of the logical address, thereby saving RAM resources. Fewer logical addresses make address addressing easier, and efficient management of physical addresses. DRAWINGS

1 is a flowchart of a method according to an embodiment of the present invention;

2 is a fragmented representation of a logical address when the number of DDR3s is different according to the first application example of the present invention;

3 is a schematic structural diagram of a mapping device of an application example 2 of the present invention;

4 is a schematic diagram showing the structure of a decoding apparatus based on a mapping implementation decoding process according to the third application example of the present invention. detailed description

The solution of the embodiment of the present invention is a one-to-many mapping processing scheme between the logical address and the physical address of the DDR3, and uses the least logical address resource to meet the system design requirement, and divides the logical address into interval segments according to the number of DDR3s configured by the current system. Then, the mapping between the logical address and the physical address is performed separately by the interval segment.

To simplify the description, the logical address is simply referred to as PMAU description when it is represented in the form of a linked list, and the bank of the full text refers to the physical bank instead of the logical physical bank. In this paper, n refers to the number of linked lists in the segment.

The implementation of the technical solution will be further described in detail below with reference to the accompanying drawings.

FIG. 1 is a schematic flowchart of a method according to an embodiment of the present invention, where the process includes the following steps: Step 101: Partition the logical address according to the currently configured number of DDRs.

Step 102: Perform one-to-many mapping processing between the logical address and the physical address according to the logical addresses of the interval segments after the partitioning.

Application Example 1: In this example, the mapping process of the embodiment of the present invention is specifically described by taking the total number of logical addresses as 128k and the number of variable groups of off-chip DDR3 being 1~5.

Step 201: Perform the segmentation processing on the total logical address, and adopt the equalization mode.

Here, the specific process of step 201 is as follows: According to the current system configuration DDR3 group number, the total logical address idle node interval is equally divided into n segments (each segment is represented by a segment number of a logical address), wherein the number of segments is the total number of physical banks The median value of all the common divisors is 2n, so that PMAU[16:15-n] represents the segmentation address.

For example, when the number of DDR3s is 5 and each DDR3 contains 8 physical banks, the total number of physical banks is 40, and the common divisor of 4 is 2n, which is 8, which means that when the number of DDR3 is At 5 o'clock, 40 physical banks are divided into 8 segments.

The above-mentioned segmentation rules are adopted so that the intra-segment offset address of each segment of the logical address can be quickly characterized by PMAU[16:15-n], and each segment contains the minimum number of physical banks, and the remaining PMAU [14-n] :0] is the offset address of the logical address in each segment, and subsequent decoding will be simpler. The segmentation of logical addresses under different DDR3 number configurations is shown in the table in Figure 2.

Step 202: For each segment, according to the intra-segment offset address and the intra-segment offset base address configured by the system, the logical address is offset from the physical bank address in the segment corresponding to the segment, that is, the intra-segment offset corresponding to the logical address. Move the physical bank number.

In the case of 2n and 2n, in the case of 2n, the logical address and the physical address are mapped one-to-one, according to the prior art; in the case of non- 2n, the logical address and the physical address are one-to-many mapping.

For example, it can be seen from the table in FIG. 2 that, in the system configuration, if the number of DDR3 groups is 1, 2, 4, etc., 2n, each segment includes only one physical bank, and the segment in the table of FIG. No. Represents the physical bank number to which the logical address belongs.

In the case where the number of DDR3 groups is not 2n, such as the case where the number of DDR3 groups is 3 and 5, the segmentation interval of each logical address includes a plurality of physical banks. In the current example, the number of DD3s is 5 when each segment contains physics. The largest number of banks, each segment includes 5 physical banks.

In order to distinguish the physical bank address in the segment within the segment corresponding to the logical address, the embodiment of the present invention sets an offset base address for each physical bank, and assumes that the number of linked lists in the segment is n, then the required physical bank The number of offset base addresses is nl. Therefore, in the current example, when the number of DDR3s is 5, the required intra-segment offset base address is the most, and the number is 4. When the number of DDR3s is 3, under the above-mentioned segmentation rule, because each segment contains only 3 physics. Bank, so only 2 offset base addresses are needed. Taking the number of DDR3 equal to 3 as an example, assume that the above two offset addresses are a0 and a1 respectively, and PMAU[13:0] is the offset address of the PMAU in the segment, because each segment contains 3 physical banks, so when PMAU[ 13:0]<a0, the offset physical bank address of the PMAU in the segment is 0. When a0 <= PMAU[13:0] <al, the offset physical bank address of the PMAU in the segment is 1. When PMAU[13:0] >=al, the offset physical bank address of the PMAU in the segment is 2. That is to say, the purpose of the partition is to obtain partition partitioning with the system-configured offset base address, such as partitions (0-1) and (1-2) identified by offset base addresses 0, 1, and 2, offset. The relationship between the address and the offset base address is: continue to divide in any partition of each partition (0-1) and (1-2), and identify with an offset base address, such as partition (0-1) It is further refined by 0.1, 0.2, 0.3 0.9. It should be pointed out here that "0.1" and so on are for convenience of explanation and are described in digital form. In practical applications, the form of address representation is used, similar to the description of PMAU[13:0], which is not mentioned here.

In summary, when the number of DDR3 is 3, if a0 <= PMAU[13:0] <al and the segment address to which the PMAU belongs is 3, then the physical bank number of the PMAU in 24 physical banks is: 9 +1=10.

Where, in the equation of 9+1=10, the first 9 on the left represents all physical banks with a segment address of 3. The physical bank base address (each segment contains 3 physical banks), and 1 indicates the offset physical bank address within the segment. Thus, the intra-segment offset physical bank address corresponding to the logical address in various configurations can be obtained, which can also be referred to as the physical bank number of the logical address.

Step 203: Obtain the base address of the specific row and column of the offset physical bank address in the segment according to the offset physical bank address in the segment.

The representation of the physical bank address is equivalent to a two-dimensional matrix. To find the offset physical bank address within the segment, you need to find the specific row and column base address of the physical bank address. After calculating the physical bank number of the logical address, it is easy to obtain the offset address of the logical address in the physical bank according to the comparison between the offset base address in the segment and PMAU[14-n: 0]. Still taking the above DDR3 number equal to 3 as an example, assuming that the segment address of the logical address is 3, that is, PMAU[16:14]=3, and a0<= PMAU[13:0]<al , then (PMAU[13:0 ]-a0 ) is the offset address in the physical bank to which the logical address belongs. Finally, the row and column addresses can be obtained according to the current logical address and the length of each row of DDR3. For example, if the logical address and the length of each row of DDR3 are 2 KB, since each row has only one logical address, then PMAU[13:0] is Row address, the base address of the column is all 0s. The calculation method of the row and column base address under various other configurations is similar.

It should be noted that the third embodiment DDR, that is, DDR3, is used as an example to describe the mapping of logical addresses to physical addresses in the data chip domain, thereby implementing external cache management, but the partial cache is managed, thereby quickly and efficiently managing Implement decoding.

Comparing the prior art and the embodiment of the present invention, taking the DDR3 as an example, the prior art logical address and the physical address are mapped one-to-one, and the following problems exist:

To ensure a certain cache performance, a fixed number of logical addresses is generally required for implementation. In the prior art, a simple mapping relationship between a logical address bit field and a DDR3 physical address bit field is generally adopted. For example, for a 2G, 16-bit wide DDR3, the corresponding physical bank address, row address, and burst column address width are 3bit, 14bit, and 7bit, respectively, if each logical address Fixed to 2KB and the number of logical addresses is fixed at 128K, because DDR3 is 2KB per line, so the logical address is the base address of each row, and the decoding method of logical address to physical base address is simpler. The highest 3bit corresponds to the physical bank. The address, the middle 14bit corresponds to the row address, and the lowest bit low bit is 0, which is the column base address method to complete the decoding. However, the number of DDR3s required for actual use is often not an integer power of two, such as three groups. If such a simple decoding method is still required, a 19-bit representation is required for the number of 128K logical addresses. At the same time, the system solution requirements of the shared cache generally require the use of a table to manage the logical address, and the logical address needs to be the addressing pointer of the RAM, which will result in a waste of four times the required RAM resources. Depending on the application scenario of the chip, it may be required to have a variable number of external DDR3s while requiring the same number of available logical addresses.

If the total logical address is directly used for one-to-one mapping with the physical address as in the prior art, excessive logical addresses are wasted, and in the embodiment of the present invention, since the total logical address is segmented first, According to the logical address segment, the mapping between the logical address and the physical address is performed separately in the segment, and the system design requirement can be satisfied by using the minimum logical address resource, for example, the number of logical addresses of 128K, and the 17-bit representation is fixedly used, thereby adopting the embodiment of the present invention. The system RAM resources are saved to the greatest extent, and the efficient management of physical addresses can be realized, mainly by address mapping to implement address addressing.

Application Example 2: A mapping device based on a mapping scheme that implements an embodiment of the present invention.

As shown in FIG. 3, the mapping device is located on the cache side, and includes: a partition processing unit and a mapping processing unit; wherein, the partition processing unit is configured to partition the logical address according to the currently configured DDR number; and the mapping processing unit is configured to The logical address of the interval segment performs mapping processing between the logical address and the physical address.

Here, the partition processing unit is further configured to obtain the total physical bank number according to the number of DDRs and the number of physical bank banks included in each DDR, and divide the total logical address into a plurality of logical address segments, and the number of segments is The value of all the common divisors of the total physical bank number is 2n A large value, the n refers to the number of linked lists in the segment.

Here, when the mapping processing unit is further configured to have a value of 2n, each logical address segment corresponds to one physical bank, and is a one-to-one mapping between the logical address and the physical address; if the value is not 2n, each is made A logical address segment corresponding to multiple physical banks is a one-to-many mapping between a logical address and a physical address.

Here, a preferred embodiment of the mapping processing unit in the one-to-many mapping is: the mapping processing unit is configured to configure an intra-segment offset base address for each physical bank, and the number of offset base addresses in the segment is n- 1; according to the offset base address and the intra-segment offset address in the segment, obtain an intra-segment offset physical bank address corresponding to the intra-segment offset address; and obtain a corresponding physical row address according to the offset physical bank address in the segment And the physical column address.

Application Example 3: A decoding process implemented by a mapping scheme according to an embodiment of the present invention.

As shown in Figure 4, the decoding device used to implement the decoding process, the Chinese and English comparisons of the nouns in Figure 4 are as follows:

App_pmau_vld: a valid indication of the logical address to be decoded;

App_pmau: the logical address to be decoded;

DFF: D trigger;

Compare: comparator

Pmau fld: the segment number of the logical address to be decoded parsed according to the number of DDR groups; pmau-fld_offset: the intra-segment offset address of the logical address to be decoded;

Pmau fld dlyl : post-decoding post-segment registration;

Pmau—fld—physical bank: offset the physical bank number according to the intra-segment offset address and the intra-segment base address comparison;

Ddr—physical bank— addr: the resolved physical bank address;

Ddr row addr: the resolved physical row address;

Ddr col addr: the resolved physical column address; Pmau—physical bank—offset: the physical bank internal offset address of the ddr logical address to be parsed;

Cfg—physical bank—addr[i]: the user-configured intra-segment base address for comparison, the total number is i;

Cfg_pmau— width: configured PMAU length

Cfg ddrc num: Number of configured DDR groups.

Here, it should be noted that the components of the trapezoid in Fig. 4 all represent the arithmetic unit.

The decoding process (decoding from logical address to physical address) implemented by the above decoding apparatus includes the following contents:

1. First, according to the number of DDR groups configured by the user ( cfg — ddrc — num ), the segment number of the logical address to be decoded ( pmau — fld ) and the offset address in the segment where the logical address is located ( pmau — fld — offset ).

2. Comparing the offset address in the segment with the user-configured intra-segment base address ( cfg - physical bank - addr[i] ), the intra-segment offset address belongs to the first physical bank in the segment, that is, the segment Internal offset physical bank number ( pmau - fld - physical bank [2:0] ) and offset physical address ( pmau - physical bank - offset ) in the corresponding physical bank.

3. Calculate the physical physical bank number of the logical address based on the segment number of the logical address and the offset physical bank number in the segment.

4. The row number and the column number of the physical address are obtained according to the offset physical address in the physical bank (the specific row address and column address of the physical address are obtained);

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Industrial applicability

The solution of the embodiment of the present invention partitions the logical address according to the currently configured DDR number; and performs mapping processing between the logical address and the physical address according to the logical address of each interval segment after the partition. The embodiment of the present invention does not directly map the logical address to the physical address for the total logical address, but performs the mapping processing after the total logical address is partitioned, thereby reducing the occupation of the logical address, thereby saving RAM resources. Fewer logical addresses make address addressing easier, and efficient management of physical addresses.

Claims

claims

1. A method of address mapping processing, which method includes:

Partition the logical address according to the currently configured Double Data Rate synchronous random access memory DDR number;

Mapping between logical addresses and physical addresses is performed based on the logical addresses of each interval segment after partitioning.

2. The method according to claim 1, wherein the partitioning of logical addresses according to the currently configured number of DDRs specifically includes:

The total number of physical banks is obtained based on the number of DDRs and the number of physical memory banks included in each DDR;

The total logical address is divided into multiple logical address segments, and the number of segments is the maximum value of 2n among all common denominators of the total number of physical banks, where n refers to the number of linked lists in the segment.

3. The method according to claim 2, wherein the mapping between logical addresses and physical addresses according to the logical addresses of each interval segment after partitioning specifically includes:

When the value is 2n, each logical address segment corresponds to a physical bank, which is a one-to-one mapping between logical addresses and physical addresses;

When the value is other than 2n, each logical address segment corresponds to multiple physical banks, which is a one-to-many mapping of logical addresses and physical addresses.

4. The method according to claim 3, wherein the method further includes: during the one-to-many mapping, configuring an intra-segment offset base address for each physical bank, and the number of intra-segment offset base addresses is n-l.

5. The method according to claim 4, wherein the method further includes: obtaining an intra-segment offset physical bank address corresponding to the intra-segment offset address according to the intra-segment offset base address and the intra-segment offset address.

6. The method according to claim 5, wherein the method further comprises: according to the Offset the physical bank address to obtain the corresponding physical row address and physical column address.

7. An address mapping processing device, which includes: a partition processing unit and a mapping processing unit; wherein,

The partition processing unit is configured to partition the logical address according to the currently configured number of DDRs; the mapping processing unit is configured to perform mapping processing between logical addresses and physical addresses according to the logical addresses of each interval segment after partitioning.

8. The device according to claim 7, wherein the partition processing unit is further configured to obtain the total number of physical banks based on the number of DDRs and the number of physical memory banks included in each DDR, and average the total logical addresses. It is divided into multiple logical address segments, and the number of segments is the maximum value of 2n among all common denominators of the total number of physical banks, where n refers to the number of linked lists in the segment.

9. The device according to claim 8, wherein the mapping processing unit is further configured to make each logical address segment correspond to a physical bank when the value is 2n, which is a pair of logical addresses and physical addresses. One mapping; when the value is non-2n, each logical address segment corresponds to multiple physical banks, which is a one-to-many mapping of logical addresses and physical addresses.

10. The device according to claim 9, wherein the mapping processing unit is also configured for one-to-many mapping, configuring an intra-segment offset base address for each physical bank, and the intra-segment offset base address is The number is n-1; According to the intra-segment offset base address and the intra-segment offset address, the intra-segment offset physical bank address corresponding to the intra-segment offset address is obtained; The corresponding intra-segment offset physical bank address is obtained physical row address and physical column address.