CN102508807A - Scalable processor architecture (SPARC)-V8-processor-based bus structure - Google Patents
Scalable processor architecture (SPARC)-V8-processor-based bus structure Download PDFInfo
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- CN102508807A CN102508807A CN2011103500439A CN201110350043A CN102508807A CN 102508807 A CN102508807 A CN 102508807A CN 2011103500439 A CN2011103500439 A CN 2011103500439A CN 201110350043 A CN201110350043 A CN 201110350043A CN 102508807 A CN102508807 A CN 102508807A
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Abstract
The invention discloses a scalable processor architecture (SPARC)-V8-processor-based bus structure, which is used for connecting an SPARC V8 processor with a plurality of pieces of slave equipment. The slave equipment is a logic module in a field programmable gate array (FPGA). The bus structure comprises a bus bridge, wherein the bus bridge is used for connecting the SPARC V8 processor with the plurality of pieces of slave equipment, and comprises a control logic module, an address decoding module, a data selection module and a data path. The bus structure further comprises a plurality of interface modules, wherein one end of each interface module is connected with the bus bridge, and the other end of each interface module is connected with corresponding slave equipment; and the structure of each interface module is configured according to the needs of different slave equipment. By the SPARC-V8-processor-based bus structure, problems about the system construction of users can be solved to a great extent, development speed can be increased, the development cycle of a system can be shortened, different requirements of different users can be met, and the diversity of the system can be greatly improved.
Description
Technical field
The present invention relates to a kind of bus structure.
Background technology
Along with the develop rapidly of semiconductor technology, on-site programmable device FPGA is because dirigibility greatly and good restructural ability are being applied to growing field.For the better dirigibility of performance programming device, processor with the combination of programming device just by everybody institute's extensive concern and acceptance, Here it is reconfigurable SoC.Reconfigurable SoC generally is made up of FPGA and general processor nuclear, and such structure allows under the prerequisite that does not change hardware configuration, to carry out the renewal of some parameters, function and instruction.The programmable system on chip of called optical imaging (SoPC) is exactly a kind of of restructural SoC.Homemade SoPC system is integrated together modules such as processor, storer and FPGA through encapsulation, be built into a SOC(system on a chip).It is a programmable system, has the design flexible mode, can reduce, extendible, scalable, and possess the function of the system programmable of software and hardware.
Because the singularity of homemade SoPC hardware; Be that FPGA directly is connected on the input/output space of SPARC V8 (Scalable Proces sor Architecture V8) processor through connecting line; Connecting line is a limited number of address data signals and control signal; This has just determined can't be the same with conventional use FPGA, uses between different interface signals and the processor according to Different Logic to communicate.When we need realize the module of a plurality of functions in FPGA, an external bus was very necessary with regard to what show.
Existing bus structure are not suitable for the requirement of SPARC v8 processor; And complex structure comparatively speaking, big to hardware requirement, be not suitable for the platform of our homemade SoPC hardware; We require bus in FPGA, to realize; So the read-write sequence on the bus all must satisfy the requirement of SPARC V8 processor input/output space, the look-at-me of generation can not directly pass to processor through bus, and all factors have determined to apply mechanically the formation that ready-made sheet external bus is accomplished total system fully.
Summary of the invention
The purpose of this invention is to provide a kind of simple in structure, realize easily bus structure based on SPARC V8 processor.
The present invention includes following technical scheme:
A kind of bus structure based on SPARC V8 processor are used to connect SPARC V8 processor and a plurality of slave unit; Said slave unit is the logic module among the FPGA; Said bus structure comprise a bus bridge that is used to connect SPARC V8 processor and a plurality of slave units; Bus bridge comprises control logic module, the address decoding module, and data are selected module and data path;
The address decoding module is used for selecting the slave unit that communicates with said processor; Control logic module is passed to the address decoding module with the address signal of processor output; The address decoding module is deciphered to produce to said address signal and is selected signal, and passes to control logic module;
The selection signal that control logic module produces according to the address decoding module produces slave unit and selects signal and MUX control signal;
Data path comprises read data register, write data register and MUX, and read data register is used to store the data of the slave unit of selecting through MUX, and write data register is used for the data that storage of processor is write slave unit; MUX is controlled the control of the MUX control signal of logic module generation, has only the data of selected slave unit output just can be chosen by MUX, is transferred in the read data register;
Data select module to be used for the data on the temporary said processor data line, and the control logic module control data selects module to carry out the transmission of data; When carrying out read operation, the control read data register is selected the register in the module with data transmission to data, thereby is transferred to processor; When carrying out write operation, control data selects module that processor data is transferred in the write data register, thereby is transferred in the slave unit; When not having read-write operation, the control logic module control data is selected module output high-impedance state.
Bus structure also comprise a plurality of interface modules, and each interface module one end links to each other with bus bridge, and the other end links to each other with corresponding slave unit; The structure of each interface module is configured according to the needs of different slave units.
The present invention with respect to the advantage that prior art had is:
(1) bus structure of the present invention have simple in structure, characteristics such as it is convenient to realize, hardware spending is little; Bus specification is succinctly effective; Can be used for soft nuclear, solid nuclear and stone, need not use special developing instrument and target hardware, in addition its almost compatible existing any logic synthesis tool; Can make processor under situation about not increasing with the connecting line of outside FPGA, realize control and management multiple external unit.
(2) bus structure that have an interface module can become unified signal with the conversion of signals of different slave units output, and the concrete structure of interface module can dispose according to the needs of slave unit neatly.Reduce the problem in the system integration, improved reusability, portability and the reliability of slave unit.
(3) the present invention can solve custom system to a great extent and build the problem that runs into, and improves tempo of development, shortens the construction cycle of system, can satisfy the requirement of different user aspect different, enriches the diversity of system greatly.
Description of drawings
Fig. 1 is the SoPC system construction drawing;
Fig. 2 is a bus bridge structural drawing of the present invention;
Fig. 3 is an interface module structural drawing of the present invention;
Fig. 4 is a bus structure read cycle sequential chart of the present invention;
Fig. 5 is a bus structure write cycle time sequential chart of the present invention.
Embodiment
Bus structure of the present invention are responsible for connecting the logic module among SPARC V8 processor and the FPGA.This bus is articulated on the input/output space of SPARC V8 processor, and the main contents of this invention are following:
As shown in Figure 1, be the SoPC system construction drawing, comprise SPARC V8 processor, FPGA, external memory storage and bus structure of the present invention.Bus structure of the present invention are used to connect SPARC V8 processor and the inner a plurality of logic modules of FPGA.Bus structure are finally in the inner realization of FPGA.
Bus structure of the present invention comprise a bus bridge that is used to connect SPARC V8 processor and a plurality of slave units; Slave unit is the logic module among the FPGA.Bus bridge is responsible for carrying out between SPARC V8 processor and the slave unit conversion of data and control signal, and bus bridge provides address, data and the control signal of slave unit read-write.Bus bridge is as unique main equipment of bus, and the transmission on the whole bus is all sent by main equipment, is responsible for response by slave unit.Bus is supported 32 slave units at most.
Preferably, bus structure of the present invention also comprise a plurality of interface modules.Interface module is used for connecting bus bridge and slave unit.Interface module can become different slave unit conversion of signals unified bus bridge signal, satisfies the conversion requirement of various different slave unit signals.
Bus bridge: bus bridge is as main equipment unique on the bus, and processor is controlled slave unit through bus bridge.Bus bridge provides address, data and the control signal of slave unit read-write.As shown in Figure 2, bus bridge is mainly by control logic module, the address decoding module, and data are selected module, data path several most of compositions.
1, address decoding module: when two or above slave unit are arranged in the system, just need an address decoding module select needed slave unit.Control logic module is passed to the address decoding module with the address signal ADD [27:23] of processor output, and the address decoding module is deciphered to produce to address signal and selected signal Slave_select [x], and passes to control logic module.
2, control logic module: control logic module is the major part of bus bridge logic control.Slave_select [x] signal that control logic module produces according to the address decoding module produces slave unit and selects signal PSEL0-PSEL31 and MUX control signal.The control logic module control data selects module to carry out the transmission of data, and when not having read-write operation, the control logic module control data is selected module output high-impedance state.When carrying out read operation, the control read data register is selected the register in the module with data transmission to data, thereby is transferred to processor; During write operation, control data selects module that processor data is transferred in the write data register, thereby is transferred in the slave unit.
3, data are selected module: it is the data on the temporary processor data line that data are selected the effect of module.When carrying out the read cycle, read data register passes to data with data and selects in the module, and data select module when read signal OEN is effective, data to be passed on the data line of processor.When carrying out write cycle time, the data on the processor data line DATA [15:0] at first can be transferred to data and select in the module, and under the effective situation of write signal WRITEN, data select module that data are passed in the write data register.
4, data path: data path comprises read data register, write data register and MUX.Read data register is used to store the data of the slave unit of selecting through MUX.Write data register is used for the data that storage of processor is write slave unit.The effect of MUX is to carry out that data read or slave unit is passed to main equipment with correct signal during to the master transmissions back-signalling at main equipment.MUX is controlled the control of the control signal of logic module generation, has only the data of selected slave unit output just can be chosen by MUX, is transferred in the read data register.
The left side of Fig. 2 is the signal of bus and processor, and the right side is the interface signal of bus and slave unit, and main signal comprises:
CLK: system clock
RESETN: systematic reset signal, low level is effective
The choosing of IOSN:IO sheet, low level is effective;
WRITEN: write and enable, low level is effective
OEN: data bus is read to enable, and low level is effective
BRDYN: external data is ready to signal, and low level is effective
ADD: processor address bus
DATA: processor data bus
PSELx: the chip selection signal of slave unit x
PENABLE: high level is represented the transmission cycle of the process of reading or writing
PWRITE: read-write control signal, high level represent that with effect low level is represented to read effectively
PADD: slave unit address wire
PWDATA: slave unit write data line
PRDATA: slave unit read data line
Interface module: interface module is the module of being responsible between link bus bridge and the slave unit.The structure of interface module is as shown in Figure 3, mainly comprises the interrupt control module, the byte adjusting module, read/write FIFO and reseting logic etc., all structures can be carried out cutting according to the needs of different slave units, when needs which the part function the time can select.The concrete structure of each interface module can be configured.The user only need carry out the exploitation of slave unit.The interrupt control module can respond the look-at-me that slave unit produces, thereby look-at-me is passed in the processor, produces look-at-me.The byte adjusting module can be configured according to condition of different.Bus of the present invention has 16 fixing data buss, supports 8,16 data transmission.For example, if the data that slave unit only supports 8 bit data read-writes, byte adjusting module can 16 bit data of bus transfer be divided into two 8 slave unit is exported, and with synthetic 16 bit data of 8 bit data of slave unit output.Reset logic module is used for the reset signal of bus bridge output is converted into the reset signal of slave unit.For example, the reset signal that bus bridge produces is the low level signal of a 100ns, and the reset request signal of slave unit is the high level signal of 200ns, and reset logic module can be converted into the low level signal of 100ns the high level signal of 200ns.Read-write FIFO is used for buffer memory and is input to the data that slave unit or slave unit output to bus bridge, to satisfy the rate requirement of different slave units transmission data.
The interface module design of bus can be satisfied the requirement of the unlike signal of various Different Logic modules, and for the completion conversion that perhaps user-defined logic module can both be very succinct of new module.
Fig. 4, Fig. 5 have provided the read and write access sequential chart of bus structure of the present invention to slave unit respectively.
In first clock period, address bus ADD goes up and produces correct address signal among Fig. 4, and IOSN and OEN signal are dragged down, and the read cycle begins.Through a clock period, address signal has been transferred on the bus, and correct slave unit is selected, and the address PADD that address information is driven to bus goes up to read the data in the logic module.BRDYN is an answer signal, and the BRDYN signal was dragged down in the 3rd clock period, showed that the data among the PRDATA are ready to, and in the 4th clock period, data PRDATA was passed on the DATA data bus, and data transmission finishes.
Among Fig. 5, in first clock period, processor produces correct address signal on address bus, while IOSN, and WRITEN is driven to low level, writes the transmission beginning.After a clock period, the address signal ADD of processor is transferred on the slave unit address bus PADD, and corresponding PSEL signal is selected, selects corresponding slave unit to conduct interviews.In the ensuing clock period; The PENABLE signal is put height; The DATA data-signal of processor is transferred on the PWDATA in the bus, and logic module is carried out data writing operation. then logic module is according to the situation driving interrupt module of transmission if error of transmission occurs, and generation is interrupted.
Slave unit is selected through the PSEL signal, takes place and the communicating by letter of bus.Only when PSEL was effective, bus was just effective to the operation of bus to the operation or the slave unit of slave unit.Slave unit requires data not surpass 16, and the address is maximum supports 23, and each slave unit has the addressing space of 8M.
Bus structure of the present invention have simple in structure and characteristics such as can dispose neatly, and the interconnected characteristic between its operation clock, bus bit wide, each interface bit wide and each peripheral hardware etc. can dispose neatly.Bus specification can be used for soft nuclear, solid nuclear and stone, need not use special developing instrument and target hardware, in addition its almost compatible existing any logic synthesis tool.The user can carry out writing and deleting of code according to the needs of oneself, to reach the advantages of simplicity and high efficiency purpose.
The present invention has defined a kind of configurable interconnected strategy; Allow the deviser to select different data-transmission modes and carry out different module to load; Form complete system design; Can make processor under situation about not increasing with the connecting line of FPGA, realize control and management multiple external unit.
Bus structure of the present invention have reduced the problem in the system integration through public logic interfacing and data exchange standard between the definition slave unit, have improved reusability, portability and the reliability of slave unit, have accelerated the speed of product marketization.
The content of not doing to describe in detail in the instructions of the present invention belongs to this area professional and technical personnel's known technology.Though described embodiment of the present invention in conjunction with accompanying drawing, those of ordinary skills can make various distortion or modification within the scope of the appended claims.
Claims (2)
1. the bus structure based on SPARC V8 processor are used to connect SPARC V8 processor and a plurality of slave unit; Said slave unit is the logic module among the FPGA; It is characterized in that: said bus structure comprise a bus bridge that is used to connect SPARC V8 processor and a plurality of slave units; Bus bridge comprises control logic module, the address decoding module, and data are selected module and data path;
The address decoding module is used for selecting the slave unit that communicates with said processor; Control logic module is passed to the address decoding module with the address signal of processor output; The address decoding module is deciphered to produce to said address signal and is selected signal, and passes to control logic module;
The selection signal that control logic module produces according to the address decoding module produces slave unit and selects signal and MUX control signal;
Data path comprises read data register, write data register and MUX, and read data register is used to store the data of the slave unit of selecting through MUX, and write data register is used for the data that storage of processor is write slave unit; MUX is controlled the control of the MUX control signal of logic module generation, has only the data of selected slave unit output just can be chosen by MUX, is transferred in the read data register;
Data select module to be used for the data on the temporary said processor data line, and the control logic module control data selects module to carry out the transmission of data; When carrying out read operation, the control read data register is selected the register in the module with data transmission to data, thereby is transferred to processor; When carrying out write operation, control data selects module that processor data is transferred in the write data register, thereby is transferred in the slave unit; When not having read-write operation, the control logic module control data is selected module output high-impedance state.
2. a kind of bus structure based on SPARC V8 processor as claimed in claim 1 is characterized in that: also comprise a plurality of interface modules, each interface module one end links to each other with bus bridge, and the other end links to each other with corresponding slave unit; The structure of each interface module is configured according to the needs of different slave units.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104461620A (en) * | 2014-11-27 | 2015-03-25 | 北京时代民芯科技有限公司 | Autonomous reconstruction soft configuration method for SoPC chip |
| CN104572326A (en) * | 2014-12-18 | 2015-04-29 | 北京时代民芯科技有限公司 | Read-back self-reconfiguration-based fault-tolerant method for SoPC (Programming System on Chip) chip |
| CN105429835A (en) * | 2015-11-11 | 2016-03-23 | 南车株洲电力机车研究所有限公司 | Local bus circuit based on FPGA |
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| US6754760B1 (en) * | 2000-08-21 | 2004-06-22 | Xilinx, Inc. | Programmable interface for a configurable system bus |
| CN1760848A (en) * | 2005-11-01 | 2006-04-19 | 苏州国芯科技有限公司 | Method for designing AMBA bus applied by C*Core-microprocessor |
| CN101876960A (en) * | 2009-12-21 | 2010-11-03 | 北京中星微电子有限公司 | APB bus system and chip |
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2011
- 2011-11-08 CN CN201110350043.9A patent/CN102508807B/en not_active Expired - Fee Related
Patent Citations (3)
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| US6754760B1 (en) * | 2000-08-21 | 2004-06-22 | Xilinx, Inc. | Programmable interface for a configurable system bus |
| CN1760848A (en) * | 2005-11-01 | 2006-04-19 | 苏州国芯科技有限公司 | Method for designing AMBA bus applied by C*Core-microprocessor |
| CN101876960A (en) * | 2009-12-21 | 2010-11-03 | 北京中星微电子有限公司 | APB bus system and chip |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104461620A (en) * | 2014-11-27 | 2015-03-25 | 北京时代民芯科技有限公司 | Autonomous reconstruction soft configuration method for SoPC chip |
| CN104572326A (en) * | 2014-12-18 | 2015-04-29 | 北京时代民芯科技有限公司 | Read-back self-reconfiguration-based fault-tolerant method for SoPC (Programming System on Chip) chip |
| CN104572326B (en) * | 2014-12-18 | 2017-12-01 | 北京时代民芯科技有限公司 | A kind of SoPC chip fault-tolerance approaches based on retaking of a year or grade via Self-reconfiguration |
| CN105429835A (en) * | 2015-11-11 | 2016-03-23 | 南车株洲电力机车研究所有限公司 | Local bus circuit based on FPGA |
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