CN1760848A - Method for designing AMBA bus applied by C*Core-microprocessor - Google Patents
Method for designing AMBA bus applied by C*Core-microprocessor Download PDFInfo
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Abstract
Characters of the method are that based on AMBA bus structure, using single/double C<SUP>*</SUP>Core microprocessor as bus control unit; setting bridge unit from CLB bus to AMBA bus, and applying C<SUP>*</SUP>Core microprocessor to AMBA bus; when being corresponding to single C<SUP>*</SUP>Core microprocessor, bridge unit is constituted from any one bridge of following two bridges; and when being corresponding to single C<SUP>*</SUP>Core microprocessor, bridge unit is constituted from two beings. First bridge including a set of state machine is in use for deterring states of AHB bus from CLB bus to AMBA, and the microprocessor is connected to AHB bus. Second bridge including APB state machine transfers control logic and module selection logic, and the microprocessor is connected to APB bus system of AMBA. The invention makes C<SUP>*</SUP>Core microprocessor possessing CLB bus interface get the more extensive application.
Description
Technical field
The present invention relates to a kind of bus design method of microprocessor, be specifically related to a kind of C
*The method for designing of Core microprocessor applications AMBA bus.
Background technology
Along with the development of integrated circuit processing technique and the rapid raising of EDA design level, the ability and the technology of carrying out System on Chip/SoC SoC design based on intellecture property IP (Intellectual Property) nuclear have obtained improving greatly at present.Based on the integrated reusable designing technique of IP is that various IP modules (microprocessor, DSP, storer or the like) are integrated, its key is to set up correctly, efficiently, on-chip bus structure flexibly, structure is assembled into the chip development model on basis with function.In this field, on-chip bus (on-chipbus) is as the interconnection structure of SoC integrated system, can solve the mutual communication issue between each IP functional module, comprise aspects such as data layout, liaison, sequential, agreement, thereby, the designer goes to consider how self-designed functional module and other functional modules are coupled together, it is convenient to make that the IP module integrates for removing sizable energy from.
SoC on-chip bus technology comprises two aspects, the one, and select for use and disclose general bus structure in the world, the 2nd, according to the needs independent development on-chip bus of specific area exploitation.Because the widespread use of versabus, the most conventional way are exactly to use to disclose general bus structure in the world.The bus structure of comparative maturity have the AMBA bus of ARM company, the CoreConnect that IBM Corporation proposes etc. in the world.And specific or use different not too widely buses and will be applied to these general bus structure, just must realize by the interconnected conversion of bus.
The C of the applicant C Core Technology (Suzhou) Co., Ltd.
*The Core series microprocessor has adopted C
*Bus on-chip bus standard, C
*Bus is the open bus of having carried out improving on the semiconductor of Motorola is reused the basis of standard and having optimized and come, wherein, and CLB (C
*Core Local Bus) be C
*High-performance system bus in the Bus architecture.In order to realize C
*The Core microprocessor is used widely, the present invention proposes a kind of C
*The method for designing of Core microprocessor applications AMBA bus.
Summary of the invention
The present invention proposes a kind of C
*The method for designing of Core microprocessor applications AMBA bus, its objective is will be with a kind of C of the CLB of having bus interface
*The Core microprocessor applications makes C in the system with AMBA bus architecture
*The Core microprocessor is more widely used.
For achieving the above object, the technical solution used in the present invention is: a kind of C
*The method for designing of Core microprocessor applications AMBA bus is based on the AMBA bus structure, with the list/couple C with CLB bus interface
*The Core microprocessor arrives the bridge unit of AMBA bus with C as bus control unit by the CLB bus is set
*The Core microprocessor applications is in the AMBA bus; The corresponding single C of described bridge unit
*Constitute corresponding two C during the Core microprocessor by in following two bridges any one
*During the Core microprocessor, be made of following two bridges, wherein, first bridge is the bridge of CLB bus to the ahb bus of AMBA, and second bridge is the bridge of CLB bus to the APB bus of AMBA, and first bridge is with C
*The Core microprocessor is articulated in the ahb bus system of AMBA, and second bridge is with C
*The Core microprocessor is articulated in the APB bus system of AMBA;
Comprise a group state machine in described first bridge, be used for determining the CLB bus to the corresponding state between the ahb bus of AMBA, the redirect between the completion status, the one group state machine comprises:
(1), bus abnormality machine, be used for handling the undesired transmission mode of CLB bus system;
(2), the bus idle state machine, be used for determining the transport-type of bus;
(3), bus busy condition machine, be used for judging the busy situation of bus;
(4), the bus arbitration state machine, be used for judging and the control of the ahb bus of AMBA decide the operation of bus according to the control of bus;
(5), bus separated transmission state machine, be used for handling the SPLIT transport-type that ahb bus had of AMBA;
(6), bus abort state machine, be used for handling the CLB bus system and run into unusual situation;
Comprise in described second bridge:
(1), transmission control logic, be used for storing the address of relevant CLB bus and other bus signals, and according to the transmission translation data of different in width;
(2), module selects logic, be used for providing corresponding selection signal according to the address;
(3), the APB state machine, comprise the free time (IDLE), set up (SETUP), enable (ENABLE) three states, address and other control signals of changing are transferred to the APB bus of AMBA under the control of APB logic state machine.
Related content in the technique scheme is explained as follows:
1, in the such scheme, " AMBA " is advanced microcontroller bus architecture; " AHB " is Advanced High-performance Bus; " APB " is Advanced Peripheral Bus; CLB (C
*Core Local Bus) be C
*High-performance system bus in the Bus architecture.
2, in the such scheme, described C
*The Core microprocessor adopts the CLB bus structure and designs, and has CLB bus interface form, in order to make C
*The Core microprocessor can the compatible AMBA bus of comparative maturity in the world, realizes using widely, and the bridge unit of CLB bus to the AMBA bus is set in the AMBA bus structure.About C
*The relation of the Core microprocessor and first bridge and second bridge has following three kinds of situations:
(1), adopts single C
*The Core microprocessor is as bus control unit, with first bridge with C
*The Core microprocessor is articulated in the ahb bus system of AMBA.
(2), adopt single C
*The Core microprocessor is as bus control unit, with second bridge with C
*The Core microprocessor is articulated in the APB bus system of AMBA.
(3), adopt two C
*The Core microprocessor is as bus control unit, wherein, with first bridge with a C
*The Core microprocessor is articulated in the ahb bus system of AMBA, with second bridge with another C
*The Core microprocessor is articulated in the APB bus system of AMBA.
3, in the such scheme, for the ease of representing different states, CLB comprises one group of token in first bridge of the ahb bus of AMBA.
4, in the such scheme, CLB comprises one group of conversion of signals form in first bridge of the ahb bus of AMBA, is used for according to the conversion of signals between different tokens and the signal realization bus interface.
Ultimate principle of the present invention is:
If will have the C of CLB bus interface
*The Core microprocessor is applied in the system based on the AMBA bus architecture, needs the interface of design CLB bus and AMBA system, promptly designs bridge, realizes the interconnected of two kinds of bus systems, the C of CLB bus interface like this by bridge
*The Core microprocessor just can be grafted directly to easily in the AMBA bus system system is controlled and operates.And for the AHB among the AMBA and two kinds of buses of APB, the designer can select first bridge and second bridge flexibly according to the performance requirement of chip system, with C
*The Core microprocessor is articulated in the different bus systems easily, realizes the different performance requirement of chip.
The CLB bus is with C to the effect of first bridge of the ahb bus of AMBA
*The transmission that the Core microprocessor sends is converted to the transmission to AHB system slave unit, so this bridge needs CLB and two interfaces of AHB.Bridge needs to receive earlier bus address and the control signal of CLB, sends the corresponding signal of corresponding ahb bus then, and according to the handshake of returning of AHB, converts the handshake of CLB bus to.The design of bridge will be based upon the analysis of docking port signal, and on the basis of the requirement of conversion between the two, designs the function that corresponding converting form and state machine are realized bridge.
The CLB bus is with C to the effect of second bridge of the APB bus of AMBA
*The transmission that the Core microprocessor sends is converted to the transmission to APB system slave unit, so this bridge needs CLB and two interfaces of APB.Bridge needs to receive earlier bus address and the control signal of CLB, sends the corresponding signal of corresponding APB bus then.The design of bridge will be based upon the analysis of docking port signal, and on the basis of the requirement of conversion between the two, designs the function that corresponding converting form and state machine are realized bridge.
Because the technique scheme utilization, the present invention compared with prior art has following advantage and effect:
1, the present invention adopts the method for bridge, two bridges have been designed, promptly the ahb bus and the APB bus of first bridge (the following CLB2AHB bridge that also is called) and second bridge (the following CLB2APB bridge that also is called) difference corresponding A MBA bus provide a kind of with C
*The Core series microprocessor is applied to the method for AMBA.
2, two bridges of the present invention have made things convenient for the designer to select C as required
*The Core microprocessor applications is in the ahb bus system of AMBA bus or the APB bus system of AMBA bus.
3, CLB2AHB bridge of the present invention has adopted six simple state machines to clearly illustrate that the situation that the bus system conversion may be run into, and has simplified design and change over condition.
4, CLB2APB bridge of the present invention, the method that has adopted form is described the signal of needs conversion, and make things convenient for the conversion of logic, make and to follow two double-periodic data transmission of bus when changing between two bus signals, and do not need extra latent period.
Description of drawings
Accompanying drawing 1 is system chart of the present invention.
Accompanying drawing 2 is realized block diagram for CLB bus of the present invention to the bridge of the ahb bus of AMBA.
Accompanying drawing 3 is the bridge state machine diagram of CLB bus of the present invention to the ahb bus of AMBA, wherein, and the unusual and bus idle state machine of Fig. 3 (a) expression bus; Fig. 3 (b) expression bus arbitration and bus busy condition machine; Fig. 3 (c) expression bus is separated and bus abort state machine.
Accompanying drawing 4 is the bridge implementation figure of CLB bus of the present invention to the ahb bus of AMBA.
Accompanying drawing 5 is realized block diagram for CLB bus of the present invention to the bridge of the APB bus of AMBA.
Accompanying drawing 6 is 8/16 bit data path of CLB2APB bridge transmission control logic of the present invention.
Accompanying drawing 7 is selected the realization block diagram of logic for CLB2APB bridge module of the present invention.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described:
Embodiment:
Shown in accompanying drawing 1, a kind of C310 microprocessor applications is in the bus-structured system chart of AMBA, based on the AMBA bus structure, by CLB2AHB bridge and CLB2APB bridge with C
*The Core microprocessor is applied to AMBA as a bus control unit, and first CLB2AHB bridge is applied to C
*The Core microprocessor is articulated to the ahb bus system, and second CLB2APB bridge is applied to C
*The Core microprocessor is articulated to the APB bus system, and two bridges can select one to use according to the performance need of chip.Also can adopt two C
*The Core microprocessor is as bus control unit, wherein, with first CLB2AHB bridge with a C
*The Core microprocessor is articulated in the ahb bus system of AMBA, with second CLB2APB bridge with another C
*The Core microprocessor is articulated in the APB bus system of AMBA.
One, the realization of CLB2AHB bridge
Design example: shown in accompanying drawing 2, the design of CLB2AHB bridge realizes figure, it is the analysis that is based upon the docking port signal, and on the basis of the requirement of conversion between the two, by corresponding converting form, MUX, state machine and token are formed, token is used for representing the state of corresponding state of state machine and expansion, is finished the conversion of signal by converting form by the situation of change of token and signal.
1, state machine is used for according to circumstances determining corresponding state, and the redirect between the completion status, has designed following six state machines as required:
(1), bus abnormality machine (ab_normal state_machine), be used for handling the undesired transmission mode of CLB bus system.State machine ab_normal state_machine is the information design returned of the HRESP signal at AHB equipment, when AHB equipment causes the response of RETRY or ERROR owing to cause specific, the CLB bus system should enter abnormal transmission mode accordingly, and state machine comprises normal and abnormal two states.Intactly be described below: original state is normal, as the satisfied ((RETRY﹠amp of the interface signal of AHB;～HREADY) | (ERROR﹠amp;～HREADY)) when being genuine condition, the state of state machine changes, and enters the abnormal state, and satisfy (OKAY﹠amp when the AHB interface signal; HREADY﹠amp; When being genuine HGRANT), state machine reenters the normal state.
(2), bus idle state machine (idle state_machine), be used for determining the transport-type of bus.The effect of state machine idle state_machine is a value of determining transport-type HTRANS according to the HRESP signal of AHB, guarantees that ensuing CLB bus transfer can correctly carry out.State machine has two states, original state idle_normal, i.e. normal transmission state and the state idle_idle state that carries out the IDLE transmission.Complete description: after the system RESET, state is idle_normal, when interface signal satisfies ((RETRY﹠amp;～HREADY) | (ERROR﹠amp;～HREADY) | (SPLIT﹠amp;～HREADY)) when being genuine condition, state takes place to shift and enters the idle_idle state, then state shifts the idle_normal state that enters again.
(3), bus busy condition machine (busy state_machine), be used for judging the busy situation of bus.The effect of this state machine is the return signal HREADY according to transport-type and ahb bus, and whether the transmission of judging bus BUSY, thereby the CLB bus is made corresponding response, and just the p_ta_b signal of CLB bus carries out certain variation.The Busy state machine comprises two states, normal_transfer and busy_transfer.Complete description is: the input signal of state machine is HTRANS and HREADY, the original state of state machine is busy_transfer, carry out the transfer of state by the value of judging HTRANS and HREADY, when HTRANS==BUSY and HREADY are that high condition is not when satisfying simultaneously, the state of state machine changes, go into the normal_transfer state from the original state machine, if the condition of front is still set up, then state is remained stationary, and when HTRANS==BUSY and HREADY be the words that high condition is set up simultaneously, the state of state machine shifts, and is converted to the busy_tramsfer state.When state machine at busy_transfer the time, the signal p_ta_b signal of CLB bus is changed to " 1 ".
(4), bus arbitration state machine (arbitration state_machine), be used for judging and the control of the ahb bus of AMBA decide the operation of bus according to the control of bus.State machine arbitrationstate_machine is used for judging the control of ahb bus, thereby decides the operation of bus according to the control of bus.This state machine has three states: have bus control right, do not have the control and the arbitrate state of bus.Describe its state transitions situation: under HGRANT signal during the RESET was low situation, state machine entered the state of not_own_bus; Work as HGRANT﹠amp; When the HREADY condition is genuine, enter bus arbitration arbitration state.In the arbitration state, when the HREADY position was high, state shifted, and entered the own_bus state, and transmission at this moment will normally be carried out; Under this state, if as (～HGRANT) ﹠amp; HREADY is under the genuine situation, and state transitions enters the state of not_own_bus.Original state be own_bus situation similarly.
(5), bus separated transmission state machine (split state_machine), be used for handling the SPLIT transport-type that ahb bus had of AMBA.This state machine has no_split, split_split, three states of split_transition, and wherein, the no_split state is used for representing the state that data transmission is normally carried out; The split_split state is used for representing that the main equipment that transmits by other interrupts, and the transmission of bridge enters the SPLIT transmission; The split_transition state then is to be used for representing that other main equipment finished transmission, and bus transfer will be converted to normal transmission from the SPLIT transmission.Complete state transitions situation is as follows: after finishing the RESET of system, state machine enters original state no_split state, as (HGRANT﹠amp; The ﹠amp of (～HREADY); SPLIT) be genuine condition when setting up, indicate that the SPLIT transmission has taken place in the AHB system, bridge will lose bus control right, enter the wait process, and at this moment state will be converted to the split_split state from no_split; As (HGRANT﹠amp; HREADY) be genuine condition when setting up, illustrate that SPLIT transmits finishes, and state machine state transitions will take place enters the split_transition state; In the split_transition state, if being height, HREADY shows that bridge can proceed transmission, so state exchange is no_split.
(6), bus abort state machine (abort state_machine), be used for handling the CLB bus system and run into unusual situation.State machine abort state_machine is used for handling when the CLB bus system runs into abnormal conditions, and CLB will abandon ongoing transmission, carries out new transmission again.It has not_abort and abort two states, and wherein the not_abort state is used for representing to transmit the situation generation that does not normally have abort, and the abort state represents that then transmission is abandoned no longer carrying out.Specifically describe as follows: after system finishes RESET, state machine enters the not_abort state, when p_abort_b signal and HREADY signal are low condition when setting up simultaneously, prove that bus will abandon this time transmitting, state will change and handle this situation; In the abort state, when HREADY state transitions when being high, reenter the not_abort state, normally carry out following transmission.
2, token is used to identify different states, according to top state machine, has designed following token:
(1), Abnormal_state_token: this token is used for representing that the state of bus abnormality machine is in the abnormal state, and the formula of embodying is: abnormal_state_token=(normal_state==`ABNORMAL).
(2), Idle_state_token: this token is used for representing that the state of bus idle state machine is in the idle_idle state, and expression formula is: idle_state_token=(idie_state==`IDLE_IDLE).
(3), Before_arbitration_state_token: this token is used for representing that the next state of bus arbitration state machine will be the arbitration state, and expression formula is: before_arbitration_state_token=(next_arbitration_state==`ARBITRATION).
(4), Before_arbitration_state_token1: this token is the logical and of before_arbitration_state_token token and CLB bus signals～m_tscd_b, and expression formula is: before_arbitration_state_token1=(before_arbitration_state_token﹠amp;～m_tscd_b).
(5), Split_state_token: this token is used for representing that the state of bus separated transmission state machine is in the split_split state, and expression formula is: splita_state_token=(split_state==`SPLIT_SPLIT).
(6), Split_transition_state_token: this token is used for representing that the state of bus separated transmission state machine is in the split_transition state, and expression formula is: split_transition_state_token=(split_state==`SPLIT_TRANSITION).
(7), Abort_state_token: this token is used for representing that the state of bus abort state machine is in the abort state, and expression formula is: abort_state_token=(abort_state==`ABORT).
(8), Arbitration_state_token: this token is used for representing that the state of bus arbitration state machine is in the arbitration state, and expression formula is: arbitration_state_token=(arbitration_state==`ARBITRATION).
(9), Arbitration_state_token1: this token is the logical and of arbitration_state_token token and CLB bus signals～m_tscd_b, and expression formula is: arbitration_state_token1=(arbitration_state_token﹠amp;～m_tscd_b).
(10), Busy_state_token: this token is used for representing that the state of bus busy condition machine is in the busytransfer state, and expression formula is: busy_transfer_state_token=(busy_transfer_state=`BUSY_TRANSFER).
3, bridge conversion of signals form is used for according to the conversion of signals between different tokens and the signal realization bus interface.The conversion form of signal of interest is described below:
(1), the converting form of HREQx signal
The HREQx signal is the bus request signal in the ahb bus system, and this signal demand is changed according to the p_lpmd signal in the CLB bus, and the signal assignment sees the following form 1:
Table 1HREQx logical relation table
| p_lpmd | HREQx |
| 00(stop) | 0 |
| 01(wait) | 0 |
| 10(doze) | 0 |
| 11(normal) | 1 |
(2), the converting form of HSIZE signal
The HSIZE signal is a signal of describing data length signal in the transmission course in the ahb bus system, in CLB and AHB transmission course, all can support the data transmission of different in width, word, half-word, byte, this signal demand is according to the signal p_tsiz conversion of signals of CLB bus system, and the signal assignment sees the following form 2:
Table 2HSIZE logical relation table
| p_tsiz[1：0] | HSIZE[2：0] |
| 00(word 32bit) | 010(32bit word) |
| 01(byte 8bit) | 000(8bit byte) |
| 10(halfword 16bit) | 001(16bit halfword) |
| 11(reserve) |
(3), the converting form of HPROT signal
The HPROT signal is the level features that is used for describing transmission, and each transmission can be a data transmission, can be the operational code transmission, and its character has determined that it must be changed by p_tc among the CLB and p_ifetch signal, and the signal assignment sees the following form 3:
Table 3HPROT logical relation table
| {p_tc[2]，p_ifetch} | HPROT[3：0](not bufferable and not cacheable) |
| 00 | 0001(user data fetch) |
| 01 | 0000(user opcode access) |
| 10 | 0011(privileged data fetch) |
| 11 | 0010(privileged opcode access) |
(4), the converting form of HBURST signal
HBURST signal description burst transfer type, by the inc_token conversion, the signal assignment sees the following form 4:
Table 4HBURST logical relation table
| inc_token | HBURST |
| 1 | 001(INC) |
| 0 | 000(single) |
(5), the converting form of HTRANS signal
The HTRANS signal is used for identifying the type of the each transmission of AHB system, changes according to value and several token of CLB signal.This signal is a signal important in the AHB system, and it indicates the type of each transmission.Determine the transport-type of AHB system, not only more judge, and will decide according to the different conditions of the state machine of front according to the value of CLB signal.When p_early_abort_b was effective, the type of HTRANS should be composed and be BUSY; And when the idle_state_token in the idle state machine was effective, HTRANS should be IDLE; As p_treq_b when being high, HTRANS is BUSY; When the seq_token in the state machine when being high the value of HTRANS be SEQ; When seq_token is invalid, when p_treq_b was effective, HTRANS was NONSEQ.The signal assignment sees the following form 5:
Table 5HTRANS logical relation table
| p_early_abort_b | idle_state_token | p_treq_b | seq_token | HTRANS |
| 0 | x | x | x | 01(BUSY) |
| 1 | 1 | x | x | 00(IDLE) |
| 1 | 0 | 1 | x | 01(BUSY) |
| 1 | 0 | 0 | 1 | 11(SEQ) |
| 1 | 0 | 0 | 0 | 10(NONSEQ) |
X represents that 0 or 1 all can in the table
(6), the converting form of p_ta_b and p_tea_b signal
These two handshake that signal is the CLB bus system of p_ta_b and p_tea_b, each transmission could finish and begin when all will wait their states normal normally.Analysis is learnt, the p_abort_b signal of CLB bus end, and the different conditions of the state machine of introducing previously, the return signal HREADY of ahb bus end, HRESP will determine the value of these two signals.These two signals of p_ta_b and p_tea_b are to change according to return signal HREADY, HRESP and the various token of CLB bus signals, ahb bus end, and the signal assignment sees the following form 6:
Table 6p_ta_b and p_tea_b logical relation table
| p _ a b o r t _ b | b r s y _ t r a n s f e r _ s t a t e _ t o k e n | a b o r t _ s t a t e _ t o k e n | a b n o r m a l _ s t a t e _ t o k e n | s p l i t _ s t a t e _ t o k e n | s p l i t _ t r a n s i t i o n _ s t a t e _ t o k e n | b e f o r e _ A r b i t r a t i o n _ s t a t e _ t o k enl | A r b i t r a t i o n _ s t a t e _ t o k e n l | H R E A D Y | H R E S P [ 1 ∶ 0 ] | p _ t a _ b | p _ t e a _ b |
| 0 | x | x | x | x | x | x | x | x | xx | 1 | 0 |
| 1 | 1 | x | x | x | x | x | x | x | xx | 1 | 1 |
| 1 | 0 | 1 | x | x | x | x | x | x | xx | 1 | 1 |
| 1 | 0 | 0 | 1 | x | x | x | x | x | xx | 1 | 1 |
| 1 | 0 | 0 | 0 | 1 | x | x | x | x | xx | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 | 1 | x | x | x | xx | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | x | x | xx | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | x | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 00(ok) | 0 | 1 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 00(ok) | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 01(error) | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 01(error) | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10(retry) | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 10(retry) | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11(split) | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 11(split) | 1 | 1 |
X represents that 0 or 1 all can in the table
The simple converting form of describing the present invention's design: as long as the p_abort_b signal is effective, no matter what other state status is, always that p_ta_b be " 1 " is promptly invalid, p_tea_b always be " 0 " effectively, promptly transmit and do not finish, and make a mistake; When if state machine busy_transfer_state_token is effective, bus state is for busy, and this moment, p_ta_b was invalid, and p_tea_b is invalid, i.e. transmission is not finished, and does not make a mistake; When abort_state_token, abnormal_state_token, split_state_token, split_transition_state_token, before_arbitration_state_token, arbitration_state_token token are effective respectively, p_ta_b is invalid, and p_tea_b is invalid; When above state machine token is all invalid, under the just modal transmission situation, be the value of determining p_ta_b and p_tea_b according to HREADY and HRESP, HREADY represents completion status, and HRESP represents error situation.Form has at length provided the situation that signal changes, and wherein p_ta_b is effective, and the invalid situation of p_tea_b, is the state of normal data transmission.
(7), the converting form of address_load_en signal
The address_load_en signal is used for latching of control address signal and transmission of control signals, when address_load_en is effective, just carrying out address and other control signals such as p_tsiz, p_rw_b latchs, p_addr does not carry out any processing under other situations, compose after the selection of address of latching then and undressed address process selector switch mux and give HADDR, finish the conversion of address signal.The situation more complicated that the address need be latched, need determine jointly that by the state and the signal of a lot of state machines treq_neg_token, split_state_token, split_transition_state_token, abort_state_token, abnormal_state_token, arbitration_state_token1, ptea_b, p_early_abort_b, p_ta_b signal and token determine the value of address_load_en jointly.Table 7 has clearly provided the situation of change of address_load_en: token is from left to right arranged according to the height of priority, under the effective situation of the token on the left side, the not only whether effective situation of the token of back, according to form assignment address_load_en, from form as can be seen when all tokens are all invalid, to determine the variation of address_load_en according to the combined situation of p_tea_b, p_early_abort_b, three signals of p_ta_b, when p_tea_b is low, when being wrong generation, address_load_en is effective; When p_tea_b is high, i.e. transmission does not have wrong the time, if p_early_abort_b is for low effective the time, only abnormal conditions take place to abandon transmission, and this moment, address_load_en did not carry out address latch for hanging down; As p_tea_b, when p_early_abort_b is invalid, promptly transmit the assignment that situation about finishing decides address_load_en according to p_ta_b, when p_ta_b effective for the low address latch address_load_en that need carry out effective the time; When p_ta_b does not then need to carry out address latch invalid the time for high, this moment address_load_en invalid be " 0 ".Change over condition sees the following form 7:
Table 7address_load_en logical relation table
| t r e q _ n e g _ t o k e n | s p l i t _ s t a t e _ t o k e n | s p l i t _ t r a n s i t i o n _ s t ate_token | a b o r t _ s t a t e _ t o k e n | A b n o r m a l _ s t a t e _ t o k e n | A r b i t r a t i o n _ s t a t e _ t okenl | p _ t e a _ b | P _ e a r l y _ a b o r t _ b | p _ t a _ b | a d d r e s s _ l o a d _ e n |
| 1 | x | x | x | x | x | x | x | x | 1 |
| 0 | 1 | x | x | x | x | x | x | x | 0 |
| 0 | 0 | 1 | x | x | x | x | x | x | 0 |
| 0 | 0 | 0 | 1 | x | x | x | x | x | 0 |
| 0 | 0 | 0 | 0 | 1 | x | x | x | x | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | x | x | x | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | x | x | 1 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | x | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 |
X represents that 0 or 1 all can in the table
(8), the converting form of select_enable signal
The select_enable signal is the selection signal (being the selection signal of HADDR) of the first bridge inside, when this signal when being low, the address of selecting not latch be p_addr as HADDR, and when signal when being high, the address signal that selection was latched is as HADDR.This signal is controlled jointly by state idle_state_token, ab_normal_state_token, abort_state_token, split_transition_state_token, the arbitration_state_token of some state machines.When idle_state_token was effective, no matter effective situation of other token, signal select_enable was low, and promptly the address does not need to latch; According to the situation of priority from left to right, when abnormal_state_token was effective, the signal that need latch was delivered to the AHB end; Same abort_state_token, split_transition_state_token, arbitration_state_token1 are effective, get under the invalid situation of token and be higher than their priority, select_enbale then is high, and the signal that promptly needs to latch is delivered to the AHB end as address signal.The select_enable signal is changed by several tokens, and the signal assignment sees the following form 8:
Table 8select_enable logical relation table
| i d l e _ s t a t e _ t o k e n | a b n o r m a l _ s t a t e _ t oken | a b o r t _ s t a t e _ t o k e n | s p l i t _ t r a n s i t i o n _sate_token | A r b i t r a t i o n _ s t a t e_token1 | s e l c t _ e n a b l e |
| 1 | x | x | x | x | 0 |
| 0 | 1 | x | x | x | 1 |
| 0 | 0 | 1 | x | x | 1 |
| 0 | 0 | 0 | 1 | x | 1 |
| 0 | 0 | 0 | 0 | 1 | 1 |
X represents that 0 or 1 all can in the table
(9), the converting form of Inc_token token
The Inc_token token is changed according to the p_aseq_b signal, that is to say that the address according to the transport-type that last time transmission increases continuously, decides an inc_token.The token delay_inc_token of this token and a clock period of its delay comes together to determine the seq_token that mentions later, thereby determines the SEQ transport-type of signal HTRANS above-mentioned.When p_aseq_b effectively just " 0 " time, the inc_token token is " 1 "; And when p_aseq_b is invalid when being " 1 ", the inc_token token is " 0 ".The signal assignment sees the following form 9:
Table 9inc_token logical relation table
| p_aseq_b | inc_token |
| 0 | 1 |
| 1 | 0 |
(10), the converting form of Seq_token token
The Seq_token token is used to refer to above the ahb bus will carry out the transmission of continuation address, as inc_token and delay_inc_token when all being high, show and will transmit continuously that this moment, seq_token just was effectively for " 1 ".And other situations, seq_token will can be ineffective.Its conversion sees the following form 10:
Table 10seq_token logical relation table
| inc_token | delay_inc_token | Seq_token |
| 1 | 1 | 1 |
| 1 | 0 | 0 |
| 0 | 1 | 0 |
| 0 | 0 | 0 |
Provide the basic read-write implementation of CLB2AHB bridge below.
Read transmission:
Data are sent to CLB main equipment (C from the AHB slave unit through bridge in this transmission
*The Core processor) in.When the CLB main equipment will be read to transmit, send the transmission signals of CLB, each state machine provides the signal that AHB holds according to token and internal control signal then according to the state of condition conversion oneself.A wherein very important internal signal is address_load_en, know above, this signal is determined by the signal of interest that CLB such as many tokens such as arbitration_state_token1, abort_state_normal, abnormal_state_token etc. and p_ta_b, p_tea_b hold, when having only this signal effective, transmission of control signals just can be delivered to the AHB end.
When this bridge at C
*After starting working under the control of Core, the p_treq_b signal drags down, and just starts its inner state machine, and jumps along sampling address and control signal on clock.When internal control signal address_load_en is effective, offer the AHB end sampling with by transport address, transmission of control signals that top form is changed, the transmission of beginning AHB end.And then when next transmission began, the data of last transmission were returned from CLB.The transmission of back is according to the return signal HREADY and the HRESP of AHB end, and the operation of participant status machine is changed and the control signal assignment thereby carry out corresponding form.Reading transmission can finish in two clock period.Fig. 4 has provided implementation.
Write transmission:
Data are from CLB main equipment (C in this transmission
*Core) be sent in the AHB slave unit through bridge.When the CLB main equipment will be write transmission, send the transmission signals of CLB, each state machine provides the signal that AHB holds according to token and internal control signal then according to the state of condition conversion oneself.When same internal signal address_load_en was effective, transmission of control signals, transport address and write data just can be delivered to the AHB end.
When this bridge at C
*After starting working under the control of Core, the p_treq_b signal drags down, and just starts its inner state machine, and jumps along sampling address date and control signal on clock.When internal control signal address_load_en is effective, offer the AHB end sampling with by transport address, transmission of control signals and data that top form is changed, the transmission of beginning AHB end.The transmission of back is according to the return signal HREADY and the HRESP of AHB end, and the operation of participant status machine is changed and the control signal assignment thereby carry out corresponding form.
Two, the realization of CLB2APB bridge
Design example: shown in accompanying drawing 5, the design of CLB2APB bridge realizes figure, by an APB state machine, adds address decoding selection module and control transmission module composition simultaneously.
1, APB state machine: address and other control signals of changing will be transferred to the APB bus under the control of APB state machine.The APB state machine comprises the free time (IDLE), sets up (SETUP), enables (ENABLE) three states, when bus be reset or bus on not transmission the time, state machine is in the IDLE state, valid function at some APB slave units has taken place above bus once, bridge will enter this state of SETUP, the PSELx signal has been put in this state, and this state is only kept one-period, then according to circumstances enters ENBALE state or IDLE state.Table 11 is the variation forms according to the coherent signal of APB state machine variation.
Table 11APB state machine signal change list
| State | PSEL | PENABLE | Addr_latch_en | | p_ta_b |
| IDLE | |||||
| 0 | 0 | 1 | | 1 | |
| | 1 | 0 | 0 | ～ | 1 |
| | 1 | 1 | 0 | ～ | 0 |
2, transmission control logic: store as required and the bus signals of the address that produces relevant CLB bus and other, and according to the transmission translation data of different in width.Realize of the transmission of the bus data of CLB bus by a data selector switch in this logic, for different bytes different mapping relations are arranged, as shown in Figure 6 to the APB bus data.
3, module is selected logic: provide corresponding selection signal according to the address.Module selection logic is used for producing the selection signal of concrete slave unit, referring to shown in Figure 7.The base address of each slave unit is arranged in module selection logic, work as C
*When the Core microprocessor was initiated once visit, module was selected the relatively base address of the LSB position of p_addr (concrete LSB position be come in by the system integration time define) and each slave unit of logic.As long as they are complementary, there is the visit of an APB to initiate with regard to explanation.Apb_select and apb_module_select signal are that module selects logic to export to the APB state machine.The Apb_select signal will be effective at first in the APB visit, and the apb_module_select signal will point out that slave unit is selected.
The foregoing description only is explanation technical conceive of the present invention and characteristics, and its purpose is to allow the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences that spirit is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (4)
1, a kind of method for designing of C*Core microprocessor applications AMBA bus, it is characterized in that: based on the AMBA bus structure, with list with CLB bus interface/pair C*Core microprocessor as bus control unit, by be provided with the CLB bus to the bridge unit of AMBA bus with the C*Core microprocessor applications in the AMBA bus; Constitute by in following two bridges any one during the corresponding single C*Core microprocessor of described bridge unit, during corresponding pair C*Core microprocessors, constitute by following two bridges, wherein, first bridge is the bridge of CLB bus to the ahb bus of AMBA, second bridge is the bridge of CLB bus to the APB bus of AMBA, first bridge is articulated to the C*Core microprocessor in the ahb bus system of AMBA, and second bridge is articulated to the C*Core microprocessor in the APB bus system of AMBA;
Comprise a group state machine in described first bridge, be used for determining the CLB bus to the corresponding state between the ahb bus of AMBA, the redirect between the completion status, the one group state machine comprises:
(1), bus abnormality machine, be used for handling the undesired transmission mode of CLB bus system;
(2), the bus idle state machine, be used for determining the transport-type of bus;
(3), bus busy condition machine, be used for judging the busy situation of bus;
(4), the bus arbitration state machine, be used for judging and the control of the ahb bus of AMBA decide the operation of bus according to the control of bus;
(5), bus separated transmission state machine, be used for handling the SPLIT transport-type that ahb bus had of AMBA;
(6), bus abort state machine, be used for handling the CLB bus system and run into unusual situation;
Comprise in described second bridge:
(1), transmission control logic, be used for storing the address of relevant CLB bus and other bus signals, and according to the transmission translation data of different in width;
(2), module selects logic, be used for providing corresponding selection signal according to the address;
(3), the APB state machine, comprise the free time, set up, enable three states, address and other control signals of changing are transferred to the APB bus of AMBA under the control of APB logic state machine.
2, the method for designing of C*Core microprocessor applications AMBA bus according to claim 1 is characterized in that: comprise one group of token in described first bridge, be used to represent different states, one group token comprises:
(1), the Abnormal_state_token token is used for representing that the state of bus abnormality machine is in the abnormal state;
(2), the Idle_state_token token is used for representing that the state of bus idle state machine is in the idle_idle state;
(3), the Before_arbitration_state_token token is used for representing that the next state of bus arbitration state machine will be the arbitration state;
(4), the Before_arbitration_state_token1 token is the logical and of before_arbitration_state_token token and CLB bus signals～m_tscd_b;
(5), the Split_state_token token is used for representing that the state of bus separated transmission state machine is in the split_split state;
(6), the Split_transition_state_token token is used for representing that the state of bus separated transmission state machine is in the split_transition state;
(7), the Abort_state_token token is used for representing that the state of bus abort state machine is in the abort state;
(8), the Arbitration_state_token token is used for representing that the state of bus arbitration state machine is in the arbitration state;
(9), the Arbitration_state_token1 token is the logical and of arbitration_state_token token and CLB bus signals～m_tscd_b;
(10), the Busy_state_token token is used for representing that the state of bus busy condition machine is in the busytransfer state.
3, the method for designing of C*Core microprocessor applications AMBA bus according to claim 2, it is characterized in that: comprise one group of conversion of signals form in first bridge, be used for according to the conversion of signals between different tokens and the signal realization bus interface, one group conversion of signals form comprises:
(1), the converting form of HREQx signal
The HREQx signal is the bus request signal in the ahb bus system, and this signal demand is changed according to the p_lpmd signal in the CLB bus, and the signal assignment sees the following form 1:
Table 1 HREQx logical relation table
p_lpmd HREQx
00(stop) 0
01(wait) 0
10(doze) 0
11(normal) 1
(2), the converting form of HSIZE signal
The HSIZE signal is a signal of describing data length signal in the transmission course in the ahb bus system, and this signal demand is according to the signal p_tsiz conversion of signals of CLB bus system, and the signal assignment sees the following form 2:
Table 2 HSIZE logical relation table
p_tsiz[1:0] HSIZE[2:0]
00(word 32bit) 010(32bit word)
01(byte 8bit) 000(8bit byte)
10(halfword 16bit) 001(16bit halfword)
11(reserve)
(3), the converting form of HPROT signal
The HPROT signal is the level features that is used for describing transmission, is changed by p_tc among the CLB and p_ifetch signal, and the signal assignment sees the following form 3:
Table 3 HPROT logical relation table
{p_tc[2]，p_ifetch} HPROT[3:0](not bufferable and not cacheable)
00 0001(user data fetch)
01 0000(user opcode access)
10 0011(privileged data fetch)
11 0010(privileged opcode access)
(4), the converting form of HBURST signal
HBURST signal description burst transfer type, by the inc_token conversion, the signal assignment sees the following form 4:
Table 4 HBURST logical relation table
inc_token HBURST
1 001(INC)
0 000(single)
(5), the converting form of HTRANS signal
The HTRANS signal is used for identifying the type of the each transmission of AHB system, changes according to value and several token of CLB signal, and the signal assignment sees the following form 5:
Table 5 HTRANS logical relation table
p_early_abort_b idle_state_token p_treq_b seq_token HTRANS
0 x x x 01(BUSY)
1 1 x x 00(IDLE)
1 0 1 x 01(BUSY)
1 0 0 1 11(SEQ)
1 0 0 0 10(NONSEQ)
X represents that 0 or 1 all can in the table
(6), the converting form of p_ta_b and p_tea_b signal
These two handshake that signal is the CLB bus system of p_ta_b and p_tea_b are changed according to return signal HREADY, HRESP and the various token of CLB bus signals, ahb bus end, and the signal assignment sees the following form 6:
Table 6 p_ta_b and p_tea_b logical relation table
p_ab_ort_b busy_transfer_state_token abort_state_token abnormal_state_token split_state_roken split_transition_state_token before_Arbitration_state_token1 Arbitration_state_token1 HREADY HRESP[1:0] p_ta_b p_tea_b
0 x x x x x x x x xx 1 0
1 1 x x x x x x x xx 1 1
1 0 1 x x x x x x xx 1 1
1 0 0 1 x x x x x xx 1 1
1 0 0 0 1 x x x x xx 1 1
1 0 0 0 0 1 x x x xx 1 1
1 0 0 0 0 0 1 x x xx 1 1
1 0 0 0 0 0 0 1 x x 1 1
1 0 0 0 0 0 0 0 1 00(ok) 0 1
1 0 0 0 0 0 0 0 0 00(ok) 1 1
1 0 0 0 0 0 0 0 0 01(error) 0 0
1 0 0 0 0 0 0 0 1 01(error) 1 0
1 0 0 0 0 0 0 0 0 10(retry) 1 1
1 0 0 0 0 0 0 0 1 10(retry) 1 1
1 0 0 0 0 0 0 0 0 11(split) 1 1
1 0 0 0 0 0 0 0 1 11(split) 1 1
X represents that 0 or 1 all can in the table
(7), the converting form of address_load_en signal
The address_load_en signal is used for latching of control address signal and transmission of control signals, and change over condition sees the following form 7:
Table 7 address_load_en logical relation table
trcq_neg_token split_state_token split_transition_state_token abort_state_toke Abnormal_state_token Arbitrarion_stat_token1 p_tea_b p_early_abort_b p_ta_b address_loab_cn
1 x x x x x x x x 1
0 1 x x x x x x x 0
0 0 1 x x x x x x 0
0 0 0 1 x x x x x 0
0 0 0 0 1 x x x x 0
0 0 0 0 0 1 x x x 0
0 0 0 0 0 0 0 x x 1
0 0 0 0 0 0 1 0 x 0
0 0 0 0 0 0 1 1 0 1
0 0 0 0 0 0 1 1 1 0
X represents that 0 or 1 all can in the table
(8), the converting form of select_enable signal
The select_enable signal is the selection signal of the first bridge inside, is changed by several tokens, and the signal assignment sees the following form 8:
Table 8 select_enable logical relation table
idle_state_token abnormal_state_token abort_state_token split_transition_state_token Arbitration_state_token1 select_enable
1 x x x x 0
0 1 x x x 1
0 0 1 x x 1
0 0 0 1 x 1
0 0 0 0 1 1
X represents that 0 or 1 all can in the table
(9), the converting form of Inc_token token
The Inc_token token is changed according to the p_aseq_b signal, and the signal assignment sees the following form 9:
Table 9 inc_token logical relation table
p_aseq_b inc_token
0 1
1 0
(10), the converting form of Seq_token token
The Seq_token token is used to refer to above the ahb bus will carry out the transmission of continuation address, and its conversion sees the following form 10:
Table 10 seq_token logical relation table
inc_token delay_inc_token Seq_token
1 1 1
1 0 0
0 1 0
0 0 0
4, the method for designing of C*Core microprocessor applications AMBA bus according to claim 1 is characterized in that: the variation of APB state machine signal sees the following form 11 in described second bridge:
Table 11 APB state machine signal change list
State PSEL PENABLE Addr_latch_en PWRITE p_ta_b
IDLE 0 0 1 X 1
SETUP 1 0 0 ～p_rw_b 1
ENABLE 1 1 0 ～p_rw_b 0
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| CN102184290A (en) * | 2011-05-06 | 2011-09-14 | 天津大学 | Cycle accurate and bit accurate system level model for embedded micro-processor |
| CN101556571B (en) * | 2009-04-08 | 2011-11-23 | 苏州国芯科技有限公司 | Bridge capable of realizing the high/low speed switch between CLB and slave modules |
| CN102508807A (en) * | 2011-11-08 | 2012-06-20 | 北京时代民芯科技有限公司 | Scalable processor architecture (SPARC)-V8-processor-based bus structure |
| CN103198043A (en) * | 2013-01-24 | 2013-07-10 | 杭州中科微电子有限公司 | Improved AHB-to-APB bus bridge and control method thereof |
| CN103488602A (en) * | 2013-09-14 | 2014-01-01 | 西安电子科技大学 | Method of designing multi-bit data correlator based on bus |
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| CN102508807B (en) * | 2011-11-08 | 2014-11-05 | 北京时代民芯科技有限公司 | Scalable processor architecture (SPARC)-V8-processor-based bus structure |
| CN103198043A (en) * | 2013-01-24 | 2013-07-10 | 杭州中科微电子有限公司 | Improved AHB-to-APB bus bridge and control method thereof |
| CN103198043B (en) * | 2013-01-24 | 2016-05-11 | 杭州中科微电子有限公司 | A kind of improved AHB to APB bus bridge and control method thereof |
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