CN1707403A - Input and output interface controller - Google Patents
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- CN1707403A CN1707403A CN 200410025008 CN200410025008A CN1707403A CN 1707403 A CN1707403 A CN 1707403A CN 200410025008 CN200410025008 CN 200410025008 CN 200410025008 A CN200410025008 A CN 200410025008A CN 1707403 A CN1707403 A CN 1707403A
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Abstract
The I/O interface controller includes one processor with main WISHBONE interface; one kernel interface controller part with auxiliary WISHBONE interface connected to the main WISHBONE interface; registers including data register and control/state register for maintaining the operation commands of the interface controller; one I/O control part; and logic control part including kernel logic control part, DMA transmission logic control part, interruption mode transmission logic control part and inquiry mode transmission logic control part. In the said technological scheme, the I/O interface of the present invention may perform data transmission in high speed DMA mode except backing up IRQ, FIQ or inquiry transmission mode. The I/O ports have their type controlled and configured flexibly with the I/O control part. The present invention adopts WISHBONE bus in simple structure and low hardware cost.
Description
Technical field
The present invention relates to the IO interface controller in the chip, more particularly, relate to a kind of universal input/output interface controller of high speed.
Background technology
(System-on-a-Chip, SOC) field are to realize the key of high-quality, SOC easy of integration for newly-designed SOC product provides excellent interface at system integrated chip.The consideration of the design of bus IO interface on function, be also noted that the problem such as standardization, sequential closure of interface.At present, existing many manufacturers and organization development interconnect interface, WISHBONE SoC InterconnectionArchitecture of the VSIA On-Chip Bus of CoreFrame, the VSIA of the CoreConnect of the AMBA of ARM company, IBM Corporation, Palmchip company, Silicore company etc. for example, but they are incompatible, and great majority need permission agreement.But WISHBONE is wide-open bus standard, does not need permission agreement, and its complexity is low, realizes simple relatively.Therefore from opening, design cycle, realization cost, performance, WISHBONE is one of competitive SoC on-chip bus standard.
Universal input/output interface (General Purpose IO Interface, GPIO) be very important a kind of IO interface in the SoC system, its better flexibility, stronger configurability, hardware costs is little, application is abundant etc., and advantage makes that it has obtained using widely in various SoC system.Two soft nuclears of the disclosed GPIO of source code are arranged on the famous open OpenCores of hardware organization, but the two is all just supported inquiry or interrupts the low speed data transmission mode, and the IO port type of the two is fixed, and can't provide configuration and operational version flexibly for the user.And all there are following shortcoming more or less in universal I interface in the various SoC system on the market and special GPIO expansion card: only support IRQ, FIQ or inquiry low speed data transmission mode; The IO port type is single, and is dumb, and configurability is relatively poor; The bus interface complexity, reusability is relatively poor; Hardware realizes that cost is higher.
Summary of the invention
, port arrangement type inflexible shortcoming low at prior art universal input/output interface transmission speed the invention provides a kind of simple in structurely, support the IO interface of high-speed data transmission.
According to technical scheme of the present invention, a kind of IO interface controller is provided, comprise following structures:
One processor, it has the WISHBONE main interface;
One IO interface controller core parts, it has WISHBONE from interface, and described WISHBONE is connected to described WISHBONE main interface from interface;
Register links to each other with described processor and described IO interface controller core parts, comprises data register and control/status register, the operational order of the described interface controller of described register holds;
Input/output control unit links to each other with described register;
Logic control unit, link to each other with described processor, described IO interface controller core parts, described register and described input/output control unit, it comprises core logic control assembly, dma mode transmission logic control assembly, interrupt mode transmission logic control assembly and inquiry mode transmission logic control assembly, wherein, described dma mode transmission logic control assembly, interrupt mode transmission logic control assembly and inquiry mode transmission logic control assembly are subjected to the control of described core logic control assembly.
According to preferred embodiment of the present invention, the request signal of the data transmission that the dma mode transmission logic control assembly use in the described logic control unit is outside or the clock signal of external data transmission are as the handshake request signal of inside, with the clock signal that internal frequency is higher it is sampled, when sampling rising edge, outside data are transfused to and send DMA and ask, the data of input are transmitted in the mode of DMA by the WISHBONE bus through after the shifting processing, after finishing data transfer operation, return the affirmation signal of expression valid data transmission, finish dma operation one time.
According to preferred embodiment of the present invention, described input/output control unit has 32 port, described register is 48 a register, when operating, adopt the mode of " seal in and go out ", when sampling the rising edge of external request signal, described 4 eight bit registers carry out data transfer operation in regular turn one time, outside simultaneously data are input in first eight bit register, after repeating 4 above-mentioned steps, send dma request signal and carry out the DMA transmission, the value of described 4 registers is from a high position to the low level and become 32 data to be transmitted by the WISHBONE bus.
According to preferred embodiment of the present invention, described WISHBONE uses 11 groups from control and data-signal from the connection between interface and the WISHBONE main interface.
According to the present invention, a specific embodiments of this IO interface comprises following structure:
One has the bus master of WISHBONE main interface;
One has the IO interface controller core parts of WISHBONE from interface, and described WISHBONE is connected to described WISHBONE main interface from interface; Core logic control assembly in described register and the described logic control unit, interrupt mode transmission logic control assembly and inquiry mode transmission logic control assembly are integrated on the described IO interface controller core parts;
One dma mode transmission logic control assembly is connected to described IO interface controller core parts;
One input/output control unit is connected to described IO interface controller core parts, and described input/output control unit also connects outside data source module;
One clock generation module is connected to described IO interface controller core parts, and clock signal is provided.
According to the present invention, another specific embodiments of this IO interface can comprise following structure:
One has the processor of WISHBONE main interface;
One has the IO interface controller core parts of WISHBONE from interface, and described WISHBONE is connected to described WISHBONE main interface from interface; Core logic control assembly in described register and the described logic control unit, interrupt mode transmission logic control assembly and inquiry mode transmission logic control assembly are integrated on the described IO interface controller core parts;
One dma mode transmission logic control assembly is connected to described IO interface controller core parts;
One storer is connected to described dma mode transmission logic control assembly;
One serial ports is connected to described storer and described microprocessor, also is connected to outside display;
One clock frequency divider is connected to described microprocessor, and the receive clock signal offers described microprocessor behind the frequency division;
One number generator is connected to described Clock dividers and described IO interface controller core parts, receives the clock signal that described Clock dividers provides.And carry out exchanges data with described IO interface controller core parts.
After having adopted technical scheme as above, IO interface of the present invention can also use dma mode at a high speed to carry out data transmission except supporting IRQ, FIQ or query transmission mode.And IO port type of the present invention is controlled by input/output control unit, can carry out flexible configuration.Bus structure have adopted the WISHBONE bus, and are simple in structure, and simultaneously, the realization cost of hardware has also reduced widely.
Description of drawings
Feature of the present invention, essence and advantage will be below become more obvious after in conjunction with the accompanying drawings and embodiments the explanation, wherein:
Fig. 1 is the structured flowchart according to IO interface controller of the present invention;
Fig. 2 is according to Handshake Protocol figure between the interface in the IO interface controller of the present invention;
Fig. 3 is a DMA transmission time sequence graph of a relation;
Fig. 4 seals in and goes out the technical logic structural drawing;
Fig. 5 is the logic diagram according to a bit manipulation in the IO interface controller of the present invention;
Fig. 6 is a process flow diagram of inquiring about input operation;
Fig. 7 is the process flow diagram that interrupts input operation;
Fig. 8 is the process flow diagram that carries out the data output function;
Fig. 9 is the process flow diagram that carries out the DMA data transfer operation;
Figure 10 is the building-block of logic of simulating the IO interface controller of realizing with the RTL level according to of the present invention;
Figure 11 is the building-block of logic according to the IO interface controller of realizing with the FPGA realistic model of the present invention.
Embodiment
Further specify technical scheme of the present invention below in conjunction with accompanying drawing.
Fig. 1 is the structured flowchart according to IO interface controller 100 of the present invention, as shown, comprises following structure:
One processor 102, it has WISHBONE main interface 104; One IO interface controller core parts 106, it has WISHBONE from interface 108, and WISHBONE is connected to WISHBONE main interface 104 from interface 108.Follow WISHBONE SoCInterconnection specification Rev.B agreement between the above-mentioned interface, it has realized 32 data-bus width, low 5 address signals as the internal register group of address bus, control signal is the defined standard signal of agreement.
Register 110 links to each other with processor 102 and IO interface controller core parts 106, comprises data register and control/status register, the operational order of register 110 saving interface controllers.In one embodiment, the register 110 of IO interface controller 100 all is 32 bit registers of software-accessible.Comprise data register and control/status register.The user can write the I/O operation that these registers are controlled general purpose I/O signal by programming.
Input/output control unit 112 links to each other with register 110.Be specifically responsible for the interface of realizing input and output.It is to connect the internal core of data output interface and the interface of the I/O Pads of outside.It comprises 32 outside bidirectional port, can be controlled as FPDP or control port by user program, and can carry out the data input-output operation in 4 kinds of IO port modes.
Because in the superiority of each side such as opening, design cycle, realization cost, performance, output Output Interface Control device of the present invention has adopted WISHBONE IP kernel interconnection agreement.The interface of IO interface controller core parts 106 is that WISHBONE is from interface, (this is not shown with processor 102 or bus interconnection structure, below an embodiment in can be described) the WISHBONE main interface link to each other, the standard signal of use agreement definition is finished Handshake Protocol and the data transmission between the principal and subordinate interface.Advocate peace and all import from the outside after passing through synchronously from the clock signal clk _ I and the reset signal of interface.Address signal is connected with the address output signal of main interface, and low level wherein is as the address of internal register.The FPDP cross-connect of data input and output port and main interface, the expression data bus on effective byte signal and write under the control of enable signal, and swap data between the main interface module, read in control signal or valid data that main interface sends, and return the data of confirmation, status information or outside input.When illegal address signal or effective byte selection mistake occurring, be changed to significant level from interface by the signal ERR_O that will report an error and send error message to main interface.Only effective at the signal STB_O of expression normal bus cycles CYC_I and data transfer cycle, and when not having reporting errors information, just return confirmation signal ACK_O, as shown in Figure 2.Fig. 2 is according to Handshake Protocol figure between the interface in the IO interface controller of the present invention, and wherein CLK_I is that clock signal, STB_O are that data transfer cycle signal, CYC_I are that normal bus cycles, ACK_O are that confirmation signal, ERR_O are the signal that reports an error.More than be the basic mentality of designing of the WISHBONE interface of IO interface controller of the present invention, She Ji WISHBONE interface controller can make and carry out to fast and reliable data I/O operation between internal microprocessor and the external chip in this way.
If the universal input/output interface controller can only then can not satisfy the needs of high speed data transfer to interrupt or the work of inquiry low speed mode.And in many real application systems, all have the application demand of high speed data transfer, for example the A/D data transmission of 20MB/s in some GPS uses inevitably.Interrupt and inquiry mode why data transmission rate is lower, mainly be to handle or wait for that dma mode is direct and memory transactions data of interrupts of CPU not in data transmission procedure then owing to they all need the operate as normal of interrupts of CPU.Therefore, IO interface design of Controller of the present invention has realized the DMA data transfer mode, and it is mainly realized by dma mode transmission logic control assembly 118.In the IO interface of the present invention, adopt the request signal of the clock signal EXT_CLK of outside lower frequency, thereby avoided requiring the outside special data transmission request signal that produces, simplified user's design as the DMA transmission, convenient for users to use.Adopt the higher clock signal WB_CLK of internal frequency that outside low-frequency clock is sampled, when sampling rising edge, dma request signal is changed to significant level, thereby send dma request signal DMA_REQ.After finishing data transfer operation, the DMA answer signal is changed to effectively, return the affirmation signal DMA_ACK of expression valid data transmission.When sampling the DMA answer signal when effective, just dma request signal is removed, finish dma operation one time, the sequential relationship between each control signal is as shown in Figure 3.Fig. 3 is a DMA transmission time sequence graph of a relation, and wherein WB_CLK is that the higher clock signal of internal frequency, EXT_CLK are that clock signal, the DMA_REQ of outside lower frequency is that dma request signal, DMA_ACK are confirmation signals.
If outside is that unit carries out input operation with the byte, and the data width of inner WISHBONE bus is 32, in order to improve the utilization factor of message transmission rate and bus effectively, so adopted the realization technology of " seal in and go out ".The building-block of logic such as a mistake of " seal in and go out " technology! Do not find Reference source.Shown in, using 48 register, and realize a counter simultaneously, counter is not shown in the drawings, but those of ordinary skill in the art should be appreciated that counter can be realized with software or example, in hardware.When sampling the rising edge of external timing signal, counter is from 1 counting, between 4 eight bit registers, carry out data transfer operation one time according to the order from the low address to the high address, outside simultaneously data are input in the minimum eight bit register in address, when counter is accumulated to 4, promptly all read in data in 4 registers, added up to 32 bit data.At this moment, the value of 4 registers is from the high address to the low address and become 32 data to send into storer by the WISHBONE bus, and unison counter is clear 0, correctly to carry out next operation.In this case, dma request signal becomes when four rising edges appear in external clock just to data transmission request signal of dma controller transmission.
According to the present invention, the register 110 of IO interface controller comprises data register and control/status register.The user can be by being provided with control register and the register that reads and writes data is finished the input and output operation of data.Data register comprises that input data register, output data register, DMA import data register, and control/status register comprises control register, output enable register, OIER, interrupt status register.
The data transfer operation process of IO interface controller of the present invention is as follows.Fig. 5 is the logic diagram according to 1 bit manipulation in the IO interface controller of the present invention, more particularly, is wherein 1 the building-block of logic of outside 32 bit ports, below with the 0th operation that inputs or outputs of at length introducing module as example.Hardware reset signal makes 32 all general input/output signals be set to inquire about the input operation pattern, that is to say, it all is invalid, all conductively-closeds of interruption that all output triple gates drive, and therefore input can not produce any interrupt request singal.When the user need carry out input operation with inquiry mode, at first the corresponding position by user program setting output enable register is " 0 ", make it be output as high-impedance state, to forbid output function, and the corresponding position that OIER is set is " 0 ", to forbid producing interrupt request, the user inquires about input operation with regard to readable corresponding port position, the concrete operations flow process as shown in Figure 6:
Step S600 when the user is provided with when carrying out input operation with interrupt mode, be " 0 " by the corresponding position of user by programmed settings output enable register at first, makes to be output as high resistant, with the selection reading mode.
Step S602, the corresponding position that OIER is set is " 1 ", to allow interrupt request.
Step S604, the interrupt enable bit that control register is set is " 1 ", and, then when the input data of corresponding outside port satisfy trigger mode, just can produce interrupt request singal by the trigger mode that interrupt request triggers control bit selection exterior interrupt is set.Shield the interrupt request of all, the interrupt enable bit reset of control register is got final product.
Step S606, the corresponding position of inquiry input data register.
In general, generally will do following a few step work in interrupt handling routine, concrete stream dirt figure should be appreciated that as shown in Figure 7 flow process shown in Figure 7 is to follow after the request interrupt step of step S604:
Step S700 preserves on-the-spot.
Step S702 reads in the data of port, such as data input register.
Step S704 puts 0 with the interrupt enable bit and the interrupt status register of control register, promptly removes interrupt request singal.
Step S706 recovers on-the-spot.
When customer requirements carried out output function, concrete operating process comprised as shown in Figure 8:
Step S800 at first is " 1 " by the user by the corresponding position that programming is provided with the output enable register, to select WriteMode.
Step S802 is provided with OIER and puts 0 for " 0 " or with the interrupt enable bit of control register, produces with the disabled interrupt request signal.
Step S804, user just can carry out the data output function, such as data are write data output register.
IO interface controller of the present invention is also supported the DMA data transfer mode.When carrying out DMA when operation transmission, concrete process flow diagram as shown in Figure 9:
Step S900 at first will be set to 0 by the dma operation enable bit of user's control register.
Step S902, the lower clock signal of foreign frequency is as 31st input of dma request signal by outside port.
Step S904, outside byte data is from the least-significant byte input of outside port simultaneously.
Step S906, inner byte data with outside 4 inputs is merged into 32 data and is sent into storer by the WISHBONE bus, carries out the DMA data transfer operation.
IO interface of the present invention is not only supported the interruption of using always and is inquired about the low speed data transmission mode, and supports DMA high speed data transfer mode.It supports 4 kinds of IO port types, can satisfy multiple application demand, and 32 bidirectional ports can be disposed by user flexibility, have reduced taking of hardware resource.Can use 5 kinds of interrupt request trigger modes, enrich application.Adopt the WISHBONE bus as interconnect interface, reduced design complexities and realized cost.
Introduce two building-block of logic below according to the specific implementation of IO interface controller of the present invention:
Figure 10 is the building-block of logic of simulating the IO interface controller of realizing 1000 with the RTL level according to of the present invention.Specifically comprise following structure:
One has the bus master 1002 of WISHBONE main interface 1004,, has just used bus master 1002 rather than processor herein.
One has the IO interface controller core parts 1006 of WISHBONE from interface 1008, and WISHBONE is connected to WISHBONE main interface 1004 from interface 1008.Core logic control assembly in register and the logic control unit, interrupt mode transmission logic control assembly and inquiry mode transmission logic control assembly are integrated on the described IO interface controller core parts, so do not illustrate in the figure.
One dma mode transmission logic control assembly 1010 is connected to IO interface controller core parts 1006.
One input/output control unit 1012 is connected to IO interface controller core parts 1006, and input/output control unit 1006 also connects outside data source module 1014.
One clock generation module 1016 is connected to IO interface controller core parts 1006, and it provides clock signal.
When the RTL simulation realizes, can carry out testing authentication ad hoc to the input of the inquiry in the IO interface structure of the present invention, interruption input (5 kinds of trigger modes), data output, DMA data transmission 4 part major functions.The test vector of RTL level simulation mainly is made of following 5 modules: clock generating module 1016, dma mode transmission logic control assembly 1010, external data source 1014, WISHBONE main interface 1004 and test vector module (promptly own with the IO interface controller 1000 of RTL level simulation realization).In the process of test, the test vector program can produce 200,000 32 random data, and the input and output 4 part major functions of port are carried out analog detection.
Figure 11 is the building-block of logic according to the IO interface controller of realizing with the FPGA realistic model 1100 of the present invention.Specifically comprise:
One has the processor 1102 of WISHBONE main interface 1104.
One has the IO interface controller core parts 1106 of WISHBONE from interface 1108, and WISHBONE is connected to WISHBONE main interface 1104 from interface 1108.Core logic control assembly in register and the logic control unit, interrupt mode transmission logic control assembly and inquiry mode transmission logic control assembly are integrated on the IO interface controller core parts, thereby do not illustrate among this figure.
One dma mode transmission logic control assembly 1110 is connected to IO interface controller core parts 1106.
One storer 1112 is connected to dma mode transmission logic control assembly 1110.
One serial ports 1114 is connected to storer 1112 and microprocessor 1102, also is connected to outside display 1120.Serial ports 1114 is interfaces of a kind of input and output of being realized by input/output control unit.
One clock frequency divider 1116 is connected to microprocessor 1102, and the receive clock signal offers microprocessor 1102 behind the frequency division;
One number generator 1118 is connected to Clock dividers 1116 and IO interface controller core parts 1106, the clock signal that receive clock frequency divider 1116 provides.And carry out exchanges data with IO interface controller core parts 1106.
The FPGA simulation realizes avoiding the inherent shortcoming of RTL level simulation existence.When carrying out FPGA emulation, IO interface controller core parts 1106 are connected with processor 1102, download on the SOPC development board that comprises an APEX EP20K400E device that is about 400,000 equivalent gates of altera corp and carry out emulation.Process of simulation comprises by number generator 1118 generation data and sends to IO interface controller core parts 1106, IO interface controller core parts 1106 are operated in the DMA transmission mode, after it samples data, by dma mode transmission logic control assembly 1110 with writing data into memory 1112, behind to be transmitted the finishing, through serial ports 1114 data in the storer 1112 are outputed to display 1116 and show.
Below in the hardware complexity of analyzing according to technical scheme of the present invention.When examining admittedly, only used comprehensive IO interface controller core parts 733 standard blocks, use 755 standard blocks (having increased clock Buffer) altogether and generate stone, be distributed in 40 cell row, the utilization factor of unit is 76.8%, and area is about 38942.2um
2, the border ratio is 1: 1, has 108 IO ports.Its hardware complexity of above data declaration is lower, realizes that cost is less, and area is also smaller, and chief reason is owing to adopted WISHBONE interconnection structure and multiplex technique in design, thereby has reduced design complexity and hardware is realized cost.
IO interface controller of the present invention all is provided with register at input and output port, and controls with the single edge of single clock, thereby makes timing closure own.Its critical path is below 2ns, and the dominant frequency that can satisfy based on the design of 0.18 μ m standard block is the integrated application need of 500MHz or the SoC chip below the 500MHz.
Comprehensive, the present invention has following technique effect:
1. owing to realized direct memory visit high speed data transfer mode, and adopted the technology of " seal in and go out ", improved data transmission rate greatly, can strengthen the IO performance of whole SoC chip, through experiment, data transmission rate can reach more than the 30MBps;
2. because at the architecture of High Speed General IO interface controller IP kernel with logical design has been carried out specially and optimize meticulously, make its critical path very short, be integrated into the bottleneck that can not become chip performance in the SoC system, thereby improved the efficient of system integration work;
3. owing to adopted open bus protocol (WISHBONE), significantly improve the reusability of IO interface controller, be convenient to the integrated application of user, can not be subjected to the restriction of bus admission agreement;
4. owing to adopted the realization bus protocol that cost is little, hardware complexity is low, and adopted multiplex technique widely, therefore the realization of High Speed General IO interface controller IP kernel only needs logic gate seldom, thereby has significantly reduced the burden aspect scale and power consumption when the SoC chip is integrated.
The foregoing description provides to being familiar with the person in the art and realizes or use of the present invention; those skilled in the art can be under the situation that does not break away from invention thought of the present invention; the foregoing description is made various modifications or variation; thereby protection scope of the present invention do not limit by the foregoing description, and should be the maximum magnitude that meets the inventive features that claims mention.
Claims (6)
1. an IO interface controller is characterized in that, comprises following structures:
One processor, it has the WISHBONE main interface;
One IO interface controller core parts, it has WISHBONE from interface, and described WISHBONE is connected to described WISHBONE main interface from interface;
Register links to each other with described processor and described IO interface controller core parts, comprises data register and control/status register, the operational order of the described interface controller of described register holds;
Input/output control unit links to each other with described register;
Logic control unit, link to each other with described processor, described IO interface controller core parts, described register and described input/output control unit, it comprises core logic control assembly, dma mode transmission logic control assembly, interrupt mode transmission logic control assembly and inquiry mode transmission logic control assembly, wherein, described dma mode transmission logic control assembly, interrupt mode transmission logic control assembly and inquiry mode transmission logic control assembly are subjected to the control of described core logic control assembly.
2. IO interface controller as claimed in claim 1, it is characterized in that, the request signal of the data transmission that the dma mode transmission logic control assembly use in the described logic control unit is outside or the clock signal of external data transmission are as the handshake request signal of inside, with the clock signal that internal frequency is higher it is sampled, when sampling rising edge, outside data are transfused to and send DMA and ask, the data of input are transmitted in the mode of DMA by the WISHBONE bus through after the shifting processing, after finishing data transfer operation, return the affirmation signal of expression valid data transmission, finish dma operation one time.
3. IO interface controller as claimed in claim 1, it is characterized in that, described input/output control unit has 32 port, described register is 48 a register, when operating, adopt the mode of " seal in and go out ", when sampling the rising edge of external request signal, described 4 eight bit registers carry out data transfer operation in regular turn one time, outside simultaneously data are input in first eight bit register, after repeating 4 above-mentioned steps, send dma request signal and carry out the DMA transmission, the value of described 4 registers is from a high position to the low level and become 32 data to be transmitted by the WISHBONE bus.
4. IO interface controller as claimed in claim 1 is characterized in that, described WISHBONE uses 11 groups from control and data-signal from the connection between interface and the WISHBONE main interface.
5. as each described IO interface controller in the claim 1 to 4, it is characterized in that, can comprise following structure:
One has the bus master of WISHBONE main interface;
One has the IO interface controller core parts of WISHBONE from interface, and described WISHBONE is connected to described WISHBONE main interface from interface; Core logic control assembly in described register and the described logic control unit, interrupt mode transmission logic control assembly and inquiry mode transmission logic control assembly are integrated on the described IO interface controller core parts;
One dma mode transmission logic control assembly is connected to described IO interface controller core parts;
One input/output control unit is connected to described IO interface controller core parts, and described input/output control unit also connects outside data source module;
One clock generation module is connected to described IO interface controller core parts, and clock signal is provided.
6. as each described IO interface controller in the claim 1 to 4, it is characterized in that, can comprise following structure:
One has the processor of WISHBONE main interface;
One has the IO interface controller core parts of WISHBONE from interface, and described WISHBONE is connected to described WISHBONE main interface from interface; Core logic control assembly in described register and the described logic control unit, interrupt mode transmission logic control assembly and inquiry mode transmission logic control assembly are integrated on the described IO interface controller core parts;
One dma mode transmission logic control assembly is connected to described IO interface controller core parts;
One storer is connected to described dma mode transmission logic control assembly;
One serial ports is connected to described storer and described microprocessor, also is connected to outside display;
One clock frequency divider is connected to described microprocessor, and the receive clock signal offers described microprocessor behind the frequency division;
One number generator is connected to described Clock dividers and described IO interface controller core parts, receives the clock signal that described Clock dividers provides.And carry out exchanges data with described IO interface controller core parts.
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| CN101237415B (en) * | 2008-02-22 | 2010-10-13 | 浙江大学 | A method for realizing IP core of ARP protocol |
| CN1975635B (en) * | 2006-12-28 | 2011-01-05 | 陈曦 | Enhanced wishbone on-chip bus for leading-in bus code |
| CN102036038A (en) * | 2011-01-07 | 2011-04-27 | 天津天地伟业数码科技有限公司 | Multi-channel OSD video superposition controller |
| CN102306135A (en) * | 2011-06-02 | 2012-01-04 | 中国兵器工业集团第二一四研究所苏州研发中心 | Communication method of IP module of SOC (System-On-Chip) and OCB (On-Chip Bus) |
| CN102662894A (en) * | 2012-03-23 | 2012-09-12 | 中国航天科技集团公司第九研究院第七七一研究所 | General bus slave unit interface |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1975635B (en) * | 2006-12-28 | 2011-01-05 | 陈曦 | Enhanced wishbone on-chip bus for leading-in bus code |
| CN101237415B (en) * | 2008-02-22 | 2010-10-13 | 浙江大学 | A method for realizing IP core of ARP protocol |
| CN102036038A (en) * | 2011-01-07 | 2011-04-27 | 天津天地伟业数码科技有限公司 | Multi-channel OSD video superposition controller |
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