CN202632269U

CN202632269U - Storage system with chip enabling signal expansion

Info

Publication number: CN202632269U
Application number: CN 201220182725
Authority: CN
Inventors: 倪勇
Original assignee: Beijing Memblaze Technology Co Ltd
Current assignee: Beijing Memblaze Technology Co Ltd
Priority date: 2012-04-26
Filing date: 2012-04-26
Publication date: 2012-12-26
Anticipated expiration: 2022-04-26

Abstract

The utility model discloses a storage system with chip enabling signal expansion. The storage system comprises a memory controller, a first memory chip, and a signal expander; the memory controller is coupled with the signal expander; the first memory chip comprises a first pipe core and a second pipe core; the first pipe core is provided with a first enabling port; the second pipe core is provided with a second enabling port; and the signal expander is connected to the first enabling port and the second enabling port, so as to send independent enabling signals to the first pipe core and the second pipe core.

Description

Storage system with chip enable signal expansion

Technical field

The utility model relates to storer, storage system field.Particularly, the utility model relates to the number of pin that reduces Memory Controller, and improves the quantity of the exercisable memory chip of Memory Controller.

Background technology

Along with SSD (Solid-State Drive; Solid state hard disc) development of technology; Need hold increasing Flash chip in the storage system of forming by controller and Flash chip, but and in single Flash chip, also comprise a plurality of tube cores (DIE) through the stacked package technology.In a system, use a plurality of NAND FLASH chips to improve product capacity and performance based on the SSD technology of NAND FLASH with many enable signals.Because each tube core on the NAND Flash chip all has chip enable (Chip Enable; CE) port; And when each tube core of operation; To apply independent CE signal to it, distinguishing mutually with the operation of other chip/die in the storage system, thereby a large amount of IO port resource of numerous CE signal demand consume memory controllers.

Fig. 1 is the synoptic diagram of the SSD storage system that nand flash memory controller and NAND flash memory (FLASH) are formed in the prior art.It wraps wealthy one or more Memory Controller 101 and a plurality of flash memory path 10s 2,103 in the storage system of Fig. 1, comprises one or more pieces flash chip (not shown) on each flash memory passage.In the storage system of Fig. 1; Also comprise a plurality of flash chips or chip enable (CE) signal wire of flash memory die on connected storage controller 101 and the flash memory path 10 2; In Fig. 1, point out with " flash memory passage 1-CE1 " and " flash memory passage 1-CEn "; And a plurality of flash chips on connected storage controller 101 and the flash memory path 10 3 or chip enable (CE) signal wire of flash memory die, in Fig. 1, point out with " flash memory passage m-CE1 " and " flash memory passage m-CEn ".The storage system of Fig. 1 also comprises the data and the control signal wire except that chip enable signal line of connected storage controller 101 and flash memory path 10 2,103, in Fig. 1, points out with " data and control ".In the scheme of Fig. 1, flash memory path 10 2 and 103 shared identical " data and control " signal wires.

In the example of Fig. 1; A Memory Controller is connected with m flash memory passage; 1 flash chip is arranged on each flash memory passage; And each Flash chip comprises n tube core, and 1 chip of each tube core with oneself be when selecting (CE) port, and then the quantity of the Memory Controller CE signal that need provide is n*m.This will consume the IO pin resource that Memory Controller quantity is n*m at least, and increase the area of storage system circuit.

The utility model content

A kind of storage system is provided, has comprised Memory Controller, first memory chip, signal spreaders;

Said Memory Controller is coupled to said signal spreaders;

Said first memory chip comprises first tube core and second tube core, and said first tube core has first enable port, and said second tube core has second enable port;

Said signal spreaders is connected to said first enable port and said second enable port, to send independently enable signal to said first tube core and said second tube core.

A kind of storage system also is provided, has comprised Memory Controller, first memory chip, second memory chip, signal spreaders;

Said Memory Controller is connected to said signal spreaders;

Said first memory chip has first enable port, and said second memory chip has second enable port;

Said signal spreaders is connected to said first enable port and said second enable port, to send independently enable signal to said first memory chip and said second memory chip.

A kind of storage system also is provided, has comprised Memory Controller, first memory chip, second memory chip and signal spreaders;

Said Memory Controller is connected in series to said signal spreaders;

Said first memory chip comprises first tube core and second tube core; Said second memory chip comprises the 3rd tube core and the 4th tube core;

Said first tube core has first enable port, and said second tube core has second enable port, said the 3rd tube core the 3rd enable port, and said the 4th tube core has the 4th enable port;

[007] said signal spreaders is connected to said first enable port, said second enable port, said the 3rd enable port, said the 4th enable port, to send independently enable signal to said first tube core, said second tube core, said the 3rd tube core and said the 4th tube core.

Description of drawings

When together with advantages, through with reference to the detailed description of back, will understand the utility model best and preferably use pattern and its further purpose and advantage the embodiment of illustrating property, wherein accompanying drawing comprises:

Fig. 1 is the synoptic diagram for the SSD storage system of nand flash memory controller in the prior art and NAND flash memory composition;

Fig. 2 provides the storage system of first embodiment of the utility model;

Fig. 3 adopts shift register to come extended chip to enable the schematic diagram of the embodiment of (CE) signal;

Fig. 4 adopts PLD to come extended chip to enable the schematic diagram of the embodiment of (CE) signal.

Embodiment

Fig. 2 provides first embodiment of the utility model.It comprises Memory Controller 201 and flash memory passage 1 (202) to flash memory passage m (203) in the storage system of Fig. 2, comprises one or more pieces flash chip (not shown) on each flash memory passage.In the storage system of Fig. 2, also comprise CE extender 204.CE extender 204 is connected to storer control 201.CE extender 204 is connected with Memory Controller 201, can be through for example CE data signal line and CE control signal wire.Also can between CE extender 204 and Memory Controller 201, transmit data through communication protocols such as IIC, UART, LIN.In the embodiment in figure 1,

flash memory passage

202 and 203 data shared and the control signal wire except that chip enables.

CE extender 204 is through many chip enables (CE) signal wire; Be connected with a plurality of flash chips or chip enable (CE) port of flash memory die of flash memory passage 1 (202) to the flash memory passage m (203), these chip enables (CE) signal wire is pointed out with " flash memory passage 1-CE1 ", " flash memory passage 1-CEn ", " flash memory passage m-CE1 " and " flash memory passage m-CEn " in Fig. 2.

In the embodiment of Fig. 2; M flash memory passage arranged in the storage system; 1 flash chip is arranged on each flash memory passage, each flash chip comprise n tube core and with this n tube core corresponding n chip enable (CE) port, thereby need use n*m CE signal wire altogether.These n*m CE signal ports all are connected to CE extender 204, and communicate (for example, CE data signal line in the present embodiment and CE control signal wire) through less signal wire between CE extender 204 and the Memory Controller 201.For example; Memory Controller 201 will enable first tube core of first flash chip on the flash memory passage 203 to 204 indications of CE extender; Then CE extender 204 produces effective enable signal on corresponding " flash memory passage m-CE1 " chip enable signal line, and on other chip enable signal lines, does not produce effective enable signal.

Below, with introducing the mode of transmitting the CE signal between Memory Controller control CE extender and a plurality of flash memory passage in further detail.

Fig. 3 adopts shift register to come extended chip to enable the schematic diagram of the embodiment of (CE) signal.

The storage system of Fig. 3 comprises Memory Controller 301, shift register 302,303, and flash memory 304,305,306,307.The data of flash memory 304-307 and the control signal except that chip enables (CE) are connected to together, and are connected to Memory Controller 301.Memory Controller 301 is also connected to shift register 302 and shift register 303.The output port Q0-Q7 of shift register 302 is connected respectively to four chip enables (CE) port CE1-CE4 of flash memory 304 and four chip enables (CE) port CE1-CE4 of flash memory 305, to control 4 tube cores and 4 tube cores in the flash memory 305 in the flash memory 304 respectively.The output port Q0-Q7 of shift register 303 is connected respectively to four chip enables (CE) port CE1-CE4 of flash memory 306 and four chip enables (CE) port CE1-CE4 of flash memory 307, to control 4 tube cores and 4 tube cores in the flash memory 307 in the flash memory 306 respectively.Shift register 302 and shift register 303 are connected with cascade system, make shift register 303 can receive the displacement output signal of shift register 302.

Shift register

302 and 303 specifically can be the 74HC595 chip.

For example, when first flash memory die that will select flash memory 304 (corresponding to chip enable port CE1) when operating, through the SHCP clock; The data " 1,000 0000 " of 8bit are loaded into shift register 302 through DS, again through the STCP clock, with the data that are loaded into shift register 302; Output to the Q0-Q7 port of shift register 302; Thereby apply effective enable signal at the CE1 of flash memory 304 port, then, can carry out read-write operation first tube core of flash memory 304.Similarly, flash controller can apply effective enable signal at the CE4 of flash memory 305 port through 8 Bit datas " 0,000 0001 " are loaded into shift register 302 and export to flash memory 304,305.

Because

shift register

302 and 303 cascades, Memory Controller also can impose on

shift register

302 and 303 with 16 Bit datas " 0,000 0,000 0,001 0000 ", makes on the CE4 of flash memory 306 port, to apply effective enable signal.

In this way, through using 3 IO ports of Memory Controller 301,16 chip enables (CE) port of may command flash memory 304-307.

In the above example, have only a port to be applied in effective enable signal in the chip enable port of flash memory 304-307 at every turn.Alternatively; Can the data of

flash memory

304 and 305 and other control ports except that chip enables be linked together; And be connected to Memory Controller 301; And the data of flash memory 306,307 and other control ports except that chip enables are linked together, and be connected to Memory Controller 301, make Memory Controller 301 to send different data and control signal to flash memory set 304,305 and flash memory set 306,307 simultaneously.In the case; Memory Controller 301 can be through providing 16 Bit datas " 0,001 0,000 0,100 0000 " to shift register 302,303;, simultaneously the 4th tube core of flash memory 304 and the 2nd tube core of flash memory 306 are operated then to the CE2 port transmission enable signal of the CE4 of flash memory 304 port and flash memory 306 with simultaneously.

The storage system of Fig. 4 comprises Memory Controller 401, PLD 402, and flash memory 404,405,406,407.The data of flash memory 404-407 and the control port except that chip enables (CE) are connected to together, and are connected to Memory Controller 401.Memory Controller 401 is also connected to PLD 402.The output port Q0-Q15 of PLD 402 is connected respectively to chip enable (CE) the port CE1-CE4 of flash memory 404-407, to control 4 tube cores in each of flash memory 404-407 respectively.PLD 402 specifically can be for example FPGA (field programmable gate array; Field Programmable Gate Array), CPLD (CPLD; Complex Programmable Logic Device), EPLD (Erasable Programmable Logic Device, Erasable Programmable Logic Device) etc.

Memory Controller 401 can be set to effectively through the particular port in the output port Q0-Q15 of the FPDP (D0-D4) of PLD 402 and/or command port (CMD) PLD.For example, the Q1 port is set to effectively, can send data simultaneously and enable the control signal (CE) except that chip to flash memory 404-407 then.Because the CE1 port of the flash memory 404 that only is connected with the Q1 port of PLD 402 receives effective chip enable signal; Thereby; Only first tube core of flash memory 404 is operated, and can not disturb other tube cores of flash memory 404, also can not disturb flash memory 405-407.

Though provided the embodiment of PLD 402 connection 16 chip enables (CE) signals among Fig. 4; One of ordinary skill in the art will recognize the chip enable signal that can export other any amount through PLD, and the flash memory and/or the flash memory die of control respective numbers.And; Through the data of

flash memory

404 and 406 and the control port except that chip enables are connected respectively to Memory Controller 401; And flash memory 404 and flash memory 405 shared datas and the control port except that chip enables; Flash

memory

406 and 407 shared datas and the control port except that chip enables, Q1 and Q9 port that storer control 401 can be provided with PLD are exported useful signal simultaneously, can visit the tube core 1 of flash memory 404 and the tube core 2 of flash memory 406 then simultaneously.

One of ordinary skill in the art will recognize, the utility model comprises but do not limit to based on following mode from Memory Controller to IO extender transmission data: based on serial protocol (IIC, SPI, UART, LVDS etc.), based on PLD (CPLD, FPGA etc.), based on General Logic device (shift register etc.).

Obviously, one of ordinary skill in the art will recognize that also scheme that the utility model provides also can be applied to the storage medium of other types such as NOR flash memory or polymer memory.

Represented description, and be not intended to disclosed form limit or restriction the utility model to the utility model in order to illustrate with purpose of description.To one of ordinary skill in the art, many adjustment and variation are conspicuous.

Claims

1. a storage system comprises Memory Controller, first memory chip, signal spreaders;

Said Memory Controller is coupled to said signal spreaders;

2. storage system according to claim 1,

The FPDP of the FPDP of said first tube core and said second tube core links together, and is connected to said Memory Controller.

3. storage system according to claim 1 and 2,

Said signal spreaders is shift register or PLD.

4. a storage system comprises Memory Controller, first memory chip, second memory chip, signal spreaders;

Said Memory Controller is connected to said signal spreaders;

5. storage system according to claim 4,

The FPDP of the FPDP of said first memory chip and said second memory chip links together, and is connected to said Memory Controller.

6. according to claim 4 or 5 described storage systems,

Said signal spreaders is shift register or PLD.

7. a storage system comprises Memory Controller, first memory chip, second memory chip and signal spreaders;

Said Memory Controller is connected in series to said signal spreaders;

Said signal spreaders is connected to said first enable port, said second enable port, said the 3rd enable port, said the 4th enable port, to send independently enable signal to said first tube core, said second tube core, said the 3rd tube core and said the 4th tube core.

8. storage system according to claim 7,

The FPDP of said first tube core, said second tube core is connected to the FPDP of said first flash chip; The FPDP of said the 3rd tube core, said the 4th tube core is connected to the FPDP of said second flash chip;

The FPDP of the FPDP of said first flash chip and said second flash chip links together, and is connected to said Memory Controller.

9. according to claim 7 or 8 described storage systems,

Said signal spreaders is shift register or PLD.

10. according to claim 1,4 or 7 described storage systems, wherein said memory chip is a flash chip.