CN107301136A - It is a kind of that the method that data break selection is continuously exported is realized based on FPGA - Google Patents
It is a kind of that the method that data break selection is continuously exported is realized based on FPGA Download PDFInfo
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- CN107301136A CN107301136A CN201710476305.3A CN201710476305A CN107301136A CN 107301136 A CN107301136 A CN 107301136A CN 201710476305 A CN201710476305 A CN 201710476305A CN 107301136 A CN107301136 A CN 107301136A
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- data
- fpga
- fifo
- chip microcomputer
- control signal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
Abstract
The method that continuously exports of data break selection realized based on FPGA the invention provides a kind of, is comprised the following steps：S1, in FPGA use fifo memory buffer data；S2, the interface to FPGA interface module connection fifo memories are defined, and coordinate corresponding control signal, realize the data transfer that selection needs, and realize continuation address output.It is of the present invention to realize that data break selects the method continuously exported to implement and is relatively easy to based on FPGA, only need to control signal, significant data prioritised transmission can be achieved, transmission data and the continuous output data of guarantee, ensure that data will not lose in transmitting procedure using fifo as needed.
Description
Technical field
The invention belongs to technical field of communication equipment, realize that data break selection is continuous based on FPGA more particularly, to one kind
The method of output.
Background technology
At present, with the development of the communication technology, the equipment such as communication, observing and controlling, detection can use the tune of FPGA progress base band
System demodulation and the processing of data., it is necessary to receive the related data of Base-Band Processing in the interface module of FPGA and single chip communication,
Screening useful information is transferred to single-chip microcomputer as needed, and generally a little data are all that (data-signal, configuration, state refers to a variety of data
Show) random alignment transmission.For data-signal, single-chip microcomputer in order to read conveniently, it is often desirable that data-signal can exist one
In continuous address space；For control signal, single-chip microcomputer wants to receive within the most fast time.So FPGA's
The problems such as Data processing just occurs the obstruction of data, loses or discontinuously export, it can not only waste substantial amounts of time etc.
Useful information is treated, and emergence message can be caused can not also to read data band to single-chip microcomputer to timely and effectively transmitting
Unnecessary trouble, greatly reduces communication efficiency.
The content of the invention
In view of this, the present invention is directed to propose a kind of realize the method that data break selection is continuously exported based on FPGA, with
When solving current fpga chip and single-chip microcomputer and carrying out data transmission, there is data jamming, lose or discontinuous output etc. is asked
Topic.
To reach above-mentioned purpose, the technical proposal of the invention is realized in this way：
It is a kind of that the method that data break selection is continuously exported is realized based on FPGA, comprise the following steps：
S1, in FPGA use fifo memory buffer data；
S2, the interface that FPGA interface module connects fifo memories is defined, regulation fifo memories input when
Clock frequency and the clock frequency of output, coordinate corresponding control signal, realize the data transfer that selection needs, and realize continuously
Location is exported.
Further, in the step S2, the interface that FPGA interface module connects fifo memories is defined, defined
Method is as follows：
Data_data[19:0]:FPGA needs the data transmitted, and this circuit-switched data is data message；
Data_cfg[19:0]:FPGA needs the data transmitted, and this circuit-switched data is control information；
Data_state[19:0]:FPGA needs the data transmitted, and this circuit-switched data is status indication information；
Each defining interface connects a fifo memory, and the output end of the fifo memories all connects fifo_out
The input of memory, the output end connection single-chip microcomputer of the fif_out memories.Further, it is described in the step S2
Control signal control method is as follows：
Control_data be transmitting data information control signal, when for ' 1 ' when, expression need give single-chip microcomputer transmission；
When for ' 0 ' when represent to transmit to single-chip microcomputer；
Control_cfg for transmission control information control signal, when for ' 1 ' when, expression need give single-chip microcomputer transmission；When
For ' 0 ' when represent to transmit to single-chip microcomputer；
Control_state be transmission state configured information control signal, when for ' 1 ' when, expression need to single-chip microcomputer
Transmission；When for ' 0 ' when represent to transmit to single-chip microcomputer；
Data_out[19:0]:Output datas of the FPGA to single-chip microcomputer.
Further, the output clock frequency of the fifo memories is faster than input clock frequency.
Further, the Data_data [19 of the FPGA:0] the fifo memories of interface connection, are deposited using two fifo
Reservoir carries out table tennis read-write.
It is of the present invention to realize that the method that data break selection is continuously exported has based on FPGA relative to prior art
Following advantage：
It is of the present invention to realize that the method that data break selection is continuously exported is realized easily based on FPGA, it is only necessary to control
Signal, you can realize significant data prioritised transmission, transmission data and the continuous output data of guarantee, are protected using fifo as needed
Card data will not lose in transmitting procedure.
Brief description of the drawings
The accompanying drawing for constituting the part of the present invention is used for providing a further understanding of the present invention, schematic reality of the invention
Apply example and its illustrate to be used to explain the present invention, do not constitute inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is to realize the Method And Principle signal that data break selection is continuously exported based on FPGA described in the embodiment of the present invention
Figure.
Embodiment
It should be noted that in the case where not conflicting, the embodiment in the present invention and the feature in embodiment can phases
Mutually combination.
In the description of the invention, it is to be understood that term " " center ", " longitudinal direction ", " transverse direction ", " on ", " under ",
The orientation or position relationship of the instruction such as "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom ", " interior ", " outer " are
Based on orientation shown in the drawings or position relationship, it is for only for ease of the description present invention and simplifies description, rather than indicate or dark
Specific orientation must be had, with specific azimuth configuration and operation by showing the device or element of meaning, therefore it is not intended that right
The limitation of the present invention.In addition, term " first ", " second " etc. are only used for describing purpose, and it is not intended that indicating or implying phase
To importance or the implicit quantity for indicating indicated technical characteristic.Thus, the feature for defining " first ", " second " etc. can
To express or implicitly include one or more this feature.In the description of the invention, unless otherwise indicated, " multiple "
It is meant that two or more.
In the description of the invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or be integrally connected；Can
To be mechanical connection or electrical connection；Can be joined directly together, can also be indirectly connected to by intermediary, Ke Yishi
The connection of two element internals.For the ordinary skill in the art, above-mentioned term can be understood by concrete condition
Concrete meaning in the present invention.
Describe the present invention in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
As shown in figure 1, a kind of realize the method that data break selection is continuously exported based on FPGA, comprise the following steps：
S1, in FPGA use fifo memory buffer data；
S2, the interface that FPGA interface module connects fifo memories is defined, regulation fifo memories input when
Clock frequency and the clock frequency of output, coordinate corresponding control signal, realize the data transfer that selection needs, and realize continuously
Location is exported.
Wherein, in the step S2, the interface that FPGA interface module connects fifo memories is defined, method is defined
It is as follows：
Data_data[19:0]:FPGA needs the data transmitted, and this circuit-switched data is data message；
Data_cfg[19:0]:FPGA needs the data transmitted, and this circuit-switched data is control information；
Data_state[19:0]:FPGA needs the data transmitted, and this circuit-switched data is status indication information；
Each defining interface connects a fifo memory, and the output end of the fifo memories all connects fifo_out
The input of memory, the output end connection single-chip microcomputer of the fif_out memories.Wherein, in the step S2, the control
Signal control method is as follows：
Control_data be transmitting data information control signal, when for ' 1 ' when, expression need give single-chip microcomputer transmission；
When for ' 0 ' when represent to transmit to single-chip microcomputer；
Control_cfg for transmission control information control signal, when for ' 1 ' when, expression need give single-chip microcomputer transmission；When
For ' 0 ' when represent to transmit to single-chip microcomputer；
Control_state be transmission state configured information control signal, when for ' 1 ' when, expression need to single-chip microcomputer
Transmission；When for ' 0 ' when represent to transmit to single-chip microcomputer；
Data_out[19:0]:Output datas of the FPGA to single-chip microcomputer.
Wherein, the output clock frequency of the fifo is faster than input clock frequency.
Wherein, the Data_data [19 of the FPGA:0] the fifo memories of interface connection, using two fifo memories
Carry out table tennis read-write.
As shown in figure 1, first by fifo memories are by data receiver and store in FPGA, it is ensured that data are not lost.It is logical
Cross whether control signal decidings data need to be transferred to single-chip microcomputer.Further according to the priority of the good data output of predefined
Data are aligned in fifo_out memories in order,
In order to ensure inside FPGA can processing data, and ensure that data can be exported timely in time, I, II, III 3
The clock frequency divided is different.II clock needs to divide input clock.In order to ensure that data can be handled in time
Excessive obstruction or fifo is not caused to overflow to fifo, the frequency of frequency dividing needs careful consideration.Need according to number inside FPGA
The quantity of the valid data controlled according to speed and control signals considers how decision divides.
Each fifo can have the current data cases of one group of signal designation fifo, and fifo_empty represents that current fifo is
No is sky, and signal is that ' 1 ' expression fifo is empty, and signal represents fifo non-NULLs for ' 0 ', that is, has data；Fifo_full represents current
Whether fifo is full, and signal is that ' 1 ' expression fifo expires, and signal represents that fifo is discontented with for ' 0 ', i.e., can be with input data；fifo_
Rd_en indicates whether to read current fifo data, and signal is ' 1 ' to represent to read fifo, and signal is ' 0 ' to represent not read
fifo；Fifo_wr_en indicates whether to write current fifo, and signal is ' 1 ' to represent write-in fifo, and signal is ' 0 ' to represent to be not written into
fifo。
As shown in figure 1, three circuit-switched datas are sent to fifo memories, the different (numbers in packet header packed first according to data by FPGA
A packet header can be inserted before signal according to prior defined signal type according to before being transferred to FPGA, such as data message is inserted
Packet header 0X00FFF；Control information insertion packet header 0X00EEE etc.) caching in three fifo is internally stored in, prevent loss of data.
When fifo_out fifo_full signals are ' 0 ', represent that fifo_out also has time, data can be written into.Fifo1
~fifo3 read signal fifo_rd_en can selectively put 1, according to control_cfg, control_state,
Control_data knowledge, starts to read data.3 fifo read signal will be according to priority orders data_cfg>data_
state>Data_data is detected, if data_cfg fifo fifo_empty is ' 0 ', indicates that data_cfg information is needed
Transmit, when control_cfg is ' 1 ', then existing that data_cfg fifo_rd_en is put ' 1 ', otherwise zero setting；By that analogy
Whether detection data_state has data to need transmission, after data_cfg and data_state data all end of transmissions, will
Data_data fifo_rd_en puts 1, starts transmitting data information.It can so ensure that configuration information and status information are preferential
Transmission, it is ensured that the Effec-tive Function of system.
When fifo1~fifo3 read signal fifo_rd_en and corresponding control signals are simultaneously effective, representing should
Signal is the useful information for needing to export, and at this time fifo_out write signal fifo_wr_en puts 1, fifo1~fifo3 number
It is next according to being sequentially read out.The data of reading are deposited into fifo_out.Because control signals are not to be continuously 1, therefore
The data being written in fifo_out are not write continuously.After fifo_out, this data can be just continuous data,
Each clock cycle continuously exports.
Because be accomplished that parallel data switchs to serial data in II part, thus also need to each fifo depth and
Ith, the clock rate of II, III part is rationally set, it is desirable to should be ensured the reasonability of fifo depth, be saved to greatest extent
Limited resource inside FPGA, three kinds of data being capable of full storage.Selection for fifo depth needs to be entered according to actual conditions
Row is set, and such as fifo1, which deposits several data messages, needs deeper fifo, fifo2 and fifo3 the storage configuration information of depth and state to believe
Cease, then the more moderate fifo of depth ratio can meet in requirement, the specific setting present invention of fifo depth and not be described in detail.For all the time
The setting of speed, it is also desirable to reasonable arrangement is carried out according to the characteristics of data.Such as, if the free time of data_data data
It is shorter, if II clock rate is identical with I, fifo1 will certainly be caused, fifo2, fifo3 data are largely stored, by certain
The accumulation of time, fifo1 can be fully written, and cause the obstruction and loss of data.Therefore the clock rate of II part is than I part
Clock rate is fast, and reading data_cfg and data_state frequency also should be reduced suitably, to ensure data_data
Transmission.In addition, clock rate it is too fast can cause FPGA internal clockings constraint it is more strict, FPGA resource consumption is excessive, right
Two fifo can be used to carry out table tennis read-writes for data volume very big fifo1, the specific design present invention for the fifo that rattles
It is not described in detail.Therefore to consider above-mentioned many factors when designing the clock frequency of II part, select suitable clock
Frequency.The clock frequency of III part is not required too much, it is not necessary to individually designed clock frequency.If it is desired to FPGA design side
Just, it can use and I part identical clock frequency；If it is desired to which single-chip microcomputer design is convenient, it can use and be matched with single-chip microcomputer
Clock frequency.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
God is with principle, and any modification, equivalent substitution and improvements made etc. should be included in the scope of the protection.
Claims (5)
1. a kind of realize the method that data break selection is continuously exported based on FPGA, it is characterised in that comprises the following steps：
S1, in FPGA use fifo memory buffer data；
S2, the interface to FPGA interface module connection fifo memories are defined, the clock frequency of regulation fifo memory inputs
Rate and the clock frequency of output, coordinate corresponding control signal, realize the data transfer that selection needs, and realize that continuation address is defeated
Go out.
2. according to claim 1 realize the method that data break selection is continuously exported based on FPGA, it is characterised in that：Institute
State in step S2, the interface that FPGA interface module connects fifo memories is defined, define method as follows：
Data_data[19:0]:FPGA needs the data transmitted, and this circuit-switched data is data message；
Data_cfg[19:0]:FPGA needs the data transmitted, and this circuit-switched data is control information；
Data_state[19:0]:FPGA needs the data transmitted, and this circuit-switched data is status indication information；
Each defining interface connects a fifo memory, and the output end of the fifo memories all connects fifo_out storages
The input of device, the output end connection single-chip microcomputer of the fif_out memories.
3. according to claim 1 realize the method that data break selection is continuously exported based on FPGA, it is characterised in that：Institute
State in step S2, the control signal control method is as follows：
Control_data be transmitting data information control signal, when for ' 1 ' when, expression need give single-chip microcomputer transmission；When for
Represent to transmit to single-chip microcomputer when ' 0 '；
Control_cfg for transmission control information control signal, when for ' 1 ' when, expression need give single-chip microcomputer transmission；When for
Represent to transmit to single-chip microcomputer when ' 0 '；
Control_state be transmission state configured information control signal, when for ' 1 ' when, expression need give single-chip microcomputer transmission；
When for ' 0 ' when represent to transmit to single-chip microcomputer；
Data_out[19:0]:Output datas of the FPGA to single-chip microcomputer.
4. according to claim 1 realize the method that data break selection is continuously exported based on FPGA, it is characterised in that：Institute
The output clock frequency for stating fifo memories is faster than input clock frequency.
5. according to claim 2 realize the method that data break selection is continuously exported based on FPGA, it is characterised in that：Institute
State FPGA Data_data [19:0] the fifo memories of interface connection, table tennis read-write is carried out using two fifo memories.
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| CN201710476305.3A CN107301136A (en) | 2017-06-21 | 2017-06-21 | It is a kind of that the method that data break selection is continuously exported is realized based on FPGA |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108259368A (en) * | 2018-01-11 | 2018-07-06 | 郑州云海信息技术有限公司 | A kind of data transmission system and method based on FPGA |
| CN115309676A (en) * | 2022-10-12 | 2022-11-08 | 浪潮电子信息产业股份有限公司 | Asynchronous FIFO read-write control method, system and electronic equipment |
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| CN101403962A (en) * | 2008-11-13 | 2009-04-08 | 山东大学 | Asynchronous double-FIFO data caching method based on FPGA |
| CN102508631A (en) * | 2011-09-26 | 2012-06-20 | 福建星网锐捷网络有限公司 | Written data processing device of first input first output (FIFO) for writing any byte data |
| CN104298634A (en) * | 2014-09-24 | 2015-01-21 | 四川九洲电器集团有限责任公司 | Data transmission system based on FPGA and DSP |
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2017
- 2017-06-21 CN CN201710476305.3A patent/CN107301136A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101403962A (en) * | 2008-11-13 | 2009-04-08 | 山东大学 | Asynchronous double-FIFO data caching method based on FPGA |
| CN102508631A (en) * | 2011-09-26 | 2012-06-20 | 福建星网锐捷网络有限公司 | Written data processing device of first input first output (FIFO) for writing any byte data |
| CN104298634A (en) * | 2014-09-24 | 2015-01-21 | 四川九洲电器集团有限责任公司 | Data transmission system based on FPGA and DSP |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108259368A (en) * | 2018-01-11 | 2018-07-06 | 郑州云海信息技术有限公司 | A kind of data transmission system and method based on FPGA |
| CN115309676A (en) * | 2022-10-12 | 2022-11-08 | 浪潮电子信息产业股份有限公司 | Asynchronous FIFO read-write control method, system and electronic equipment |
| CN115309676B (en) * | 2022-10-12 | 2023-02-28 | 浪潮电子信息产业股份有限公司 | Asynchronous FIFO read-write control method, system and electronic equipment |
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Application publication date: 20171027 |