CN103077147B - A kind of global function 1553B bus IP Core based on chained list - Google Patents
A kind of global function 1553B bus IP Core based on chained list Download PDFInfo
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Abstract
The invention discloses a kind of global function 1553B bus IP Core based on chained list, comprise BC module, RT module, BM module, scrambler, demoder, message resolution module, memory module, interrupt module, markers module, self-detection module, global register, bus arbiter module.Compared with traditional 1553B bus IP Core, the present invention manages the data of BC module, RT module, BM module by the mode of chained list, by pointer automatic acquisition next address, do not take resource and carry out addressing calculating, data are Coutinuous store in storage space, does not waste storage resources, ensures that resource is utilized to greatest extent, be conducive to simplifying and miniaturization of system, and system performance obtains large increase.<!--1-->
Description
Technical field
The invention belongs to aviation electronic bus technical field, particularly a kind of global function 1553B bus IP Core based on chained list.
Background technology
MIL-STD-1553B defines the multiplex data bus of a kind of digital time-division instruction/response type.This bus has the feature such as transmission delay, transmittability, and stronger fault-tolerant ability reliably determined, is widely used abroad.China has issued national military standard GJB289A-97 corresponding with it in 1997, through development for many years, current 1553B bussing technique has been generalized to the fields such as Aeronautics and Astronautics, naval vessel, guided missile, and achieves good effect.The electronic busses technology trends current from China and practical application, in the 5-10 in future, 1553B bus still can in military electronic bus dominate.
The key component of 1553B bus is protocol processor.At present, most domestic application adopts the 1553B protocol processes chip of import, the UT1553B etc. of HI-6110, UT company of BU-61580, HOLT company of such as DDC company.But along with the development of microelectric technique, system integration technology, the communication technology, the usefulness of guided missile and military spacecraft improves constantly, and complexity is also more and more higher, the miniaturization of system, the microminiaturized requirement having become a kind of reality.Traditional protocol chip is used not to be well positioned to meet application demand to the scheme realizing bus interface.Now based on the mode of IP kernel realize 1553B protocol processes more flexibly, expand more convenient, be easier to integrated, can apply with various embedded system.
And existing 1553B bus IP Core adopts the data management mode based on address, for every bar message distributes a maximum message stores space, in practical application, most of message only takies part storage space, causes storage space utilization factor low; Meanwhile, when processing bus message, need to calculate memory address corresponding to message, computation process holding time, reduces Message Processing speed, additionally takies logical resource simultaneously, strengthen resource consumption, reduce the performance of system, be unfavorable for simplifying and miniaturization of system.
Summary of the invention
The object of the invention is to solve the data management mode of existing 1553B bus IP Core employing based on address, storage space utilization factor is low, and addressing calculates holding time and resource, reduces the performance of system, is unfavorable for that system simplifies the problem with miniaturization.
For achieving the above object, the invention provides a kind of global function 1553B bus IP Core based on chained list, comprise BC module, RT module, BM module, scrambler, demoder, message resolution module, memory module, interrupt module, markers module, self-detection module, global register, bus arbiter module, wherein, the data of BC module, RT module, BM module all adopt the mode of chained list to carry out control and management.
The chained list of BC module is made up of BC Message recover signature block, BC DSB data store block; BC Message recover signature block deposits the control information of 1553B bus message, and comprise BC DSB data store block pointer, type of message, transmission bus, message interval, retry control information, wherein BC DSB data store block pointer chain receives BC DSB data store block; BC DSB data store block deposit the command word of 1553B bus message, data word, status word, message error condition, interrupt enable and error injection information.
The chained list of RT module is made up of RT address list, RT filter list, RT controll block, RT DSB data store block; RT address list comprises one or more RT configured list, and each RT configured list deposits enabled state, status word, filter list pointer, the response time information of this RT, and wherein filter list pointer chain receives this RT filter list; RT filter list is deposited the reception subaddressing of this RT and is sent RT controll block pointer corresponding to subaddressing, and this pointer chain receives RT controll block; RT controll block deposits lawful order word, RT DSB data store block pointer, and this pointer chain receives RT DSB data store block; The each subaddressing that RT DSB data store block deposits RT receive and send the command word of 1553B bus message, data word, message error condition, interrupt enable, error injection information.
The chained list of BM module is made up of BM filter list, BM controll block, BM DSB data store block; The form of BM filter list is identical with the form of RT filter list, and the form of BM controll block is identical with the form of RT controll block; The linking relationship of BM filter list and BM controll block, is equal to the linking relationship of RT filter list and RT controll block; Deposit the DSB data store block pointer of BM in BM controll block, this pointer chain receives BM DSB data store block; BM DSB data store block deposits command word, data word, status word, message time stamp, the error condition of message, the interruption enable information of 1553B bus message.
A corresponding 1553B bus message of BC Message recover signature block, the one or more BC DSB data store block of each BC Message recover signature block chaining; BC module comprises one or more BC Message recover signature block, and BC Message recover signature block comprises BC Message recover signature block pointer, and this pointer chain receives next BC Message recover signature block, and the pointer chain of last BC Message recover signature block receives the BC Message recover signature block of beginning; BC module comprises one or more BC DSB data store block, and the linking relationship between BC DSB data store block is identical with the linking relationship of BC Message recover signature interblock.
BM module comprises one or more BM DSB data store block, and BM DSB data store block comprises BM DSB data store block pointer, and this pointer chain receives next BM DSB data store block, and the pointer chain of last BM DSB data store block receives the BM DSB data store block of beginning.
10 kinds of type of messages that BC module specifies for the treatment of 1553B bus protocol, performance period and non-periodic message send, receive, process; BC module can carry out 1553B bus message mistake retry, and retry condition and retry bus selection adopt IP kernel default value or arranged by host side; BC module can carry out 1553B bus message error injection, and for testing RT error detecting and handling ability, type of error adopts IP kernel default value or arranged by host side.
BC module is the initiation unit of 1553B bus message, comprises BC Message recover signature submodule, BC memory read/write controls submodule, inner buffer district; BC module reads the configuration information in global register, reads BC Message recover signature block and BC data control block, and extracts 1553B bus message, send to transceiver by scrambler by bus arbiter module from external memory storage; Message in 1553B bus by transceiver, demoder, is transferred to message resolution module, message resolution module by this transmission of messages to BC module; After message sends and receiving course completes, whether BC module sends interrupt request to interrupt module according to interrupt configuration Determines.
RT module is the respondent of 1553B message, comprises RT Message Processing submodule, RT memory read/write controls submodule, inner buffer district; Message in 1553B bus by transceiver, demoder, is transferred to message resolution module, message resolution module by transmission of messages to RT module; RT module is according to the RT address of command word in message and RT subaddressing, pass through bus arbiter module, from external memory storage, RT address list corresponding for this RT, RT filter list, RT controll block, RT DSB data store block are read into inner buffer district, and respond suitable status word according to command word; After message sends and receiving course completes, whether RT module sends interrupt request to interrupt module according to interrupt configuration Determines.
BM module in charge carries out record to 1553B bus data, comprises BM record controls submodule, inner buffer district; BM module, by bus arbiter module, obtains the active configuration information of this module from global register; When receiving the message that message resolution module transmission comes, BM module passes through bus arbiter module, BM filter list, BM controll block, BM DSB data store block is read from external memory storage, and according to the configuration information of BM filter block and BM controll block, determine that whether this message is stored in BM DSB data store block; After completing storage, whether BM module sends interrupt request to interrupt module according to interrupt configuration Determines.
Self-detection module completes power-on self-test survey, initialization Autonomous test, periodically Autonomous test; Self-detection module reads Autonomous test order by bus arbiter module from global register, and the result of detection is written in global register.
The described inside of the global function 1553B bus IP Core based on chained list and external interface all adopt unified wishbone STD bus, and repeatedly this IP kernel of exampleization, just can realize multiple 1553B equipment.
The present invention manages the data of BC module, RT module, BM module by the mode of chained list, has following beneficial effect:
1.BC Message recover signature block, BC DSB data store block, RT DSB data store block, BM DSB data store block all adopt the mode of chained list to realize, for BC Message recover signature block, when BC module gets current BC Message recover signature block, the next address needing BC Message recover signature block to be processed can be known by BC Message recover signature block pointer, without the need to any calculating, realize the addressing of BC Message recover signature block efficiently and easily; BC DSB data store block, RT DSB data store block, BM DSB data store block, in like manner;
2. BC DSB data store block, RT DSB data store block, BM DSB data store block all adopt the mode of chained list to carry out data storage, according to the length allocation storage space of 1553B bus message, data are all Coutinuous stores in all storage spaces, the utilization factor of storage space reaches 100%, avoids the waste of storage space;
3.RT module has at most 32 RT address lists, and each RT address list can link at most 64 RT filter list and 64 RT controll blocks, and each RT controll block can link again multiple RT DSB data store block; By above-mentioned on-link mode (OLM), can realize the function of 32 RT, the multiple message corresponding to each subaddressing of each RT process simultaneously simultaneously;
In sum, managed the data of BC module, RT module, BM module by the mode of chained list, resource is utilized to greatest extent, is conducive to simplifying and miniaturization of system, and system performance obtains large increase.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of 1553B bus IP Core of the present invention.
Fig. 2 is the list structure figure of BC module of the present invention.
Fig. 3 is the list structure figure of RT module of the present invention.
Fig. 4 is the list structure figure of BM module of the present invention.
Embodiment
As shown in Figure 1, be the structured flowchart of 1553B bus IP Core of the present invention.Described 1553B bus IP Core comprises BC module, RT module, BM module, scrambler, demoder, message resolution module, memory module, interrupt module, markers module, self-detection module, global register, bus arbiter module.
BC module is the initiation unit of 1553B bus message, comprises BC Message recover signature submodule, BC memory read/write controls submodule, inner buffer district; BC module reads the configuration information in global register, reads BC Message recover signature block and BC data control block, and extracts 1553B bus message, send to transceiver by scrambler A or scrambler B by bus arbiter module from external memory storage; Message in 1553B bus is by transceiver, and demoder A or demoder B, is transferred to message resolution module, message resolution module by this transmission of messages to BC module; After message sends and receiving course completes, whether BC module sends interrupt request to interrupt module according to interrupt configuration Determines.
RT module is the respondent of 1553B message, comprises RT Message Processing submodule, RT memory read/write controls submodule, inner buffer district; Message in 1553B bus is by transceiver, and demoder A or demoder B, is transferred to message resolution module, message resolution module by transmission of messages to RT module; RT module is according to the RT address of command word in message and RT subaddressing, pass through bus arbiter module, from external memory storage, RT address list corresponding for this RT, RT filter list, RT controll block, RT DSB data store block are read into inner buffer district, and respond suitable status word according to command word; After message sends and receiving course completes, whether RT module sends interrupt request to interrupt module according to interrupt configuration Determines.
BM module in charge carries out record to 1553B bus data, comprises BM record controls submodule, inner buffer district; BM module, by bus arbiter module, obtains the active configuration information of this module from global register; When receiving the message that message resolution module transmission comes, BM module passes through bus arbiter module, BM filter list, BM controll block, BM DSB data store block is read from external memory storage, and according to the configuration information of BM filter block and BM controll block, determine that whether this message is stored in BM DSB data store block; After completing storage, whether BM module sends interrupt request to interrupt module according to interrupt configuration Determines.
Self-detection module completes power-on self-test survey, initialization Autonomous test, periodically Autonomous test; Self-detection module reads Autonomous test order by bus arbiter module from global register, and the result of detection is written in global register.
Message resolution module, by resolving the 1553B bus message received, obtains the error condition of type of message, data word type, message, adds the time scale information obtained from markers module, be transferred to BC module, RT module, BM module together.
Interrupt module receives the interrupt request from BC module, RT module, BM module, markers module, self-detection module, and be stored in interruption queue, interrupt the triggering degree of depth that is enable and interruption queue and adopt IP kernel default value or arranged by global register by host side.
Host side, by host-side interface read-write global register and external memory storage, comes the operation of control 1553BIP core, the state of reading 1553B IP kernel, the chained list read and write in external memory storage.
The described global function 1553B bus IP Core based on chained list, adopts two redundant channel, namely comprises two buses, when a bus makes a mistake, be switched to another bus communication; Every bar bus is a corresponding scrambler and a demoder respectively.Decoder internal comprises one and sends FIFO, when detecting that transmission FIFO is not empty, the data in FIFO being sent to transceiver after Manchester's cde, is finally sent in 1553B bus.Demoder converts parallel data to message resolution module after the serial data in bus being decoded.
Demonstrate modules below how to work: in the chained list of BC, set up a subframe, this period of sub-frame is 100 milliseconds, comprise two message, the message interval time is 5 microseconds.These two message are: message 1 is the message of BC to RT, and 32 data words, bus A sends, and are the beginning of subframe, do not carry out retry; Message 2 is the message of RT to BC, and 12 data words, bus A sends, and is the end of subframe, and retry condition is for detecting that RT carries out retry, retry 1 time on different bus without responding or having during bus error.Suppose, each Message recover signature block chaining message stores block of BC module, RT module.
Before BC module, RT module, BM module work, first carry out power-on self-test survey.After Autonomous test passes through, host side carries out the information configuration such as spatial division, list structure establishment, markers, interruption be enable to modules.Configure global register afterwards, BC module, RT module, BM module are brought into operation.During operation, markers module is done always and is added counting, and self-detection module carries out cycle Autonomous test always.
As shown in Figure 2, the course of work of BC module is as follows for the list structure figure of BC module:
(1) BC Message recover signature submodule
When the signal that BC runs being detected, BC Message recover signature submodule can judge whether inner buffer district has loaded.After waiting for that it has loaded, the content in inner buffer district reads by BC Message recover signature submodule, and according to information such as the type of message of specifying in BC Message recover signature block, transmission bus, subframe mark, message interval, retry are arranged, carry out transmission and the error handle of this message.Such as: message 1 is when period of sub-frame count value is full, and command word and 32 data words are write in the FIFO of scrambler A by BC Message recover signature submodule, and finally this message sends on bus A.Message 2 is when message interval time 5 microsecond meter is full, and command word is write in the FIFO of scrambler A by BC Message recover signature submodule, and finally this message sends on bus A.The end of message, BC Message recover signature submodule by the error condition of this message and the RT responsive state word received and data word, stored in the correspondence position of DSB data store block in inner buffer district.Finally, BC Message recover signature submodule judges that this message is the need of carrying out retry, if desired retry, signals to BC memory read/write and controls submodule, BC Message recover signature submodule gets back to the state reading inner buffer district, and carries out the transmission of message in the retry bus of host side setting; If do not need retry or reached host side arrange maximum reattempt times, BC Message recover signature submodule then comes back to and judges whether inner buffer district loads completion status, repeats afterwards always.When the signal that BC stops being detected, BC Message recover signature submodule gets back to original state.
(2) BC memory read/write controls submodule
When the signal that BC runs being detected, BC memory read/write controls the relevant information such as pointer, period of sub-frame that submodule obtains first BC Message recover signature block from global register, and from external memory storage, read the BC DSB data store block of this BC Message recover signature block and this BC Message recover signature block chaining, deposit inner buffer district, signal to BC Message recover signature submodule simultaneously.Owing to adopting the structure of chained list, the pointer of next Message recover signature block therefore can be obtained very easily.When the process of BC Message recover signature submodule completes, BC memory read/write controls submodule and the information in inner buffer district is being updated in external memory storage, and upgrades global register, and now a piece of news process terminates.BC memory read/write controls submodule and judges whether to need retry, if desired, then directly gets back to and waits for BC Message recover signature submodule process completion status; If do not need, BC Message recover signature submodule has then judged whether that non-periodic, message will send, if have, then BC memory read/write controls submodule and changes the pointer of next BC Message recover signature block into aperiodic pointer, preserves the pointer of next BC Message recover signature block simultaneously; Otherwise the pointer of next BC Message recover signature block remains unchanged.Then BC memory read/write controls submodule, according to current BC Message recover signature block pointer, comes back to the state reading BC Message recover signature block and BC DSB data store block from external memory storage, repeats afterwards always.At the end of every bar Message Processing, BC memory read/write controls submodule all will judge that current message interrupts the need of generation, if desired, then sends interrupt request to interrupt module.When the signal that BC stops being detected, BC memory read/write controls submodule and gets back to original state.
By the above-mentioned course of work, the control and management of BC module to message can be realized.Transmission and the reception of other kind of message are similar with it.
As shown in Figure 3, the course of work of RT module is as follows for the list structure figure of RT module:
(1) RT Message Processing submodule
When RT Message Processing submodule detects the signal that RT runs, enter the state of wait-receiving mode command word.If receive the command word that message resolution module sends, RT Message Processing submodule can send command word and control submodule to RT memory read/write, allows it start to load data from external memory storage.After RT Message Processing submodule waits for that inner buffer district has loaded, judge that whether current RT is enable, if not enable, then Message Processing terminates; If enable, then judge whether the current command word is legal command word according to the information of RT controll block.If legal, when RT Message Processing submodule waits until that response time timing is full, according to the control information in type of message and RT data structure, in the bus receiving command word, send status word, if illegally, then directly abandon this command word.Suppose that two message in the above-mentioned example arranged in RT controll block are all legal, 32 data words of BC transmission can be received for message 1, RT Message Processing submodule, and deposit in the RT DSB data store block in inner buffer district.If message inerrancy, then send correct status word; After the inerrancy of message 2, RT Message Processing submodule check command word, send status word and 12 data words.After sending, RT Message Processing submodule upgrades the information of the RT DSB data store block in inner buffer district.Afterwards, RT Message Processing submodule comes back to the state of wait-receiving mode command word.When the signal that RT stops being detected, RT Message Processing submodule gets back to original state.
(2) RT memory read/write controls submodule
When the signal that RT runs being detected, RT memory read/write controls the first address that submodule obtains RT address list from global register.When receiving the effective order word that RT Message Processing submodule provides, the RT subaddressing of known RT address, transmission or reception from command word.If command word is effective, RT memory read/write controls submodule according to RT address, and read the address list of RT from corresponding skew space, and judge that whether this RT is enable, if not enable, process terminates; If enable, from RT address list, obtain the pointer of RT filter list.And according to the transmission in command word or received bit and RT subaddressing, offset from RT filter list the RT controll block that space reads this subaddressing accordingly.Afterwards, RT DSB data store block is read according to the pointer of the RT DSB data store block of RT controll block.Now, the content of RT address list, RT controll block, RT data-carrier store is deposited in inner buffer district by RT memory read/write control submodule.After the process of RT Message Processing submodule terminates, RT memory read/write controls submodule can be updated to external memory storage by these chained lists, and now a piece of news process terminates.Come back to the state waiting for new command word afterwards, repeat always.Every bar message last, RT memory read/write controls submodule and all can judge whether to need to produce to interrupt, and if desired, then sends interrupt request to interrupt module.When the signal that RT stops being detected, RT memory read/write controls submodule and gets back to original state.
By the above-mentioned course of work, the response of RT module to message can be realized.Transmission and the reception of other kind of message are similar with it.
As shown in Figure 4, the course of work of BM module is as follows for the list structure figure of BM module:
When the signal that BM module is run being detected, BM record controls submodule obtains the pointer of first BM DSB data store block from global register, the pointer of BM filter list, BM trigger information such as arranging, and first BM DSB data store block read in inner buffer district.Owing to adopting the structure of chained list, the pointer of next BM DSB data store block therefore can be obtained from current BM DSB data store block.BM record controls submodule receives the command word that message resolution module is sent here, carries out first order filtration to the command word received.Disposal route and RT similar, from the command word received, obtain the subaddressing of RT address, transmission or accepting state, RT, the skew space finding this subaddressing corresponding from BM filter table by these information, reads the BM controll block of this subaddressing.By the filtercondition that host side in BM controll block is arranged, compare with command word, condition meets then carries out second level filtration; Condition is satisfied to be then directly filtered.Second level filter process is: judge that whether BM Trigger Function is enable, if not enable, directly deposits in external memory storage by the message of being filtered by the first order; If enable, then when only having trigger condition to meet, just current BM DSB data store block is updated in external memory storage.After a piece of news process completes, BM record controls submodule reads next BM DSB data store block to internal buffer, repeats afterwards always.After message successfully deposits external memory storage, BM record controls submodule judges that this message is interrupted the need of generation, if desired, then sends interrupt request to interrupt module.When the signal that BM stops being detected, BM record controls submodule gets back to original state.
By the above-mentioned course of work, BM module can be realized to the reception of message and record.
More than by example, describe how working of each functional module in 1553B bus IP Core of the present invention, how to realize the control of 1553B message, process and record, and mutual with host side.
It is last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention but not to be limited, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to technical scheme of the present invention or equivalent replacement, and these are revised or be equal to the spirit and scope that replacement also can not make amended technical scheme disengaging technical solution of the present invention.
Claims (9)
1. the global function 1553B bus IP Core based on chained list, comprise BC module, RT module, BM module, scrambler, demoder, message resolution module, memory module, interrupt module, markers module, self-detection module, global register, bus arbiter module, it is characterized in that: BC module, RT module, BM module all adopt the mode of chained list to carry out control and management to data;
The chained list of BC module is made up of BC Message recover signature block, BC DSB data store block; BC Message recover signature block deposits the control information of 1553B bus message, and comprise BC DSB data store block pointer, type of message, transmission bus, message interval, retry control information, wherein BC DSB data store block pointer chain receives BC DSB data store block; BC DSB data store block deposit the command word of 1553B bus message, data word, status word, message error condition, interrupt enable and error injection information;
The chained list of RT module is made up of RT address list, RT filter list, RT controll block, RT DSB data store block; RT address list comprises one or more RT configured list, and each RT configured list deposits enabled state, status word, filter list pointer, the response time information of this RT, and wherein filter list pointer chain receives this RT filter list; RT filter list is deposited the reception subaddressing of this RT and is sent RT controll block pointer corresponding to subaddressing, and RT controll block pointer chain receives RT controll block; RT controll block deposits lawful order word, RT DSB data store block pointer, and RT DSB data store block pointer chain receives RT DSB data store block; The each subaddressing that RT DSB data store block deposits RT receive and send the command word of 1553B bus message, data word, message error condition, interrupt enable, error injection information;
The chained list of BM module is made up of BM filter list, BM controll block, BM DSB data store block; The form of BM filter list is identical with the form of RT filter list, and the form of BM controll block is identical with the form of RT controll block; The linking relationship of BM filter list and BM controll block, is equal to the linking relationship of RT filter list and RT controll block; Deposit the DSB data store block pointer of BM in BM controll block, the DSB data store block pointer chain of BM receives BM DSB data store block; BM DSB data store block deposits command word, data word, status word, message time stamp, the error condition of message, the interruption enable information of 1553B bus message.
2. the global function 1553B bus IP Core based on chained list according to claim 1, is characterized in that:
A corresponding 1553B bus message of BC Message recover signature block, the one or more BC DSB data store block of each BC Message recover signature block chaining;
BC module comprises one or more BC Message recover signature block, and BC Message recover signature block comprises BC Message recover signature block pointer, and BC Message recover signature block pointer is linked to next BC Message recover signature block, and the pointer chain of last BC Message recover signature block receives the BC Message recover signature block of beginning;
BC module comprises one or more BC DSB data store block, and the linking relationship between BC DSB data store block is identical with the linking relationship of BC Message recover signature interblock.
3. the global function 1553B bus IP Core based on chained list according to claim 1, is characterized in that:
BM module comprises one or more BM DSB data store block, and BM DSB data store block comprises BM DSB data store block pointer, and BM DSB data store block pointer chain receives next BM DSB data store block, and the pointer chain of last BM DSB data store block receives the BM DSB data store block of beginning.
4. the global function 1553B bus IP Core based on chained list according to claim 1, is characterized in that:
10 kinds of type of messages that BC module specifies for the treatment of 1553B bus protocol, performance period and non-periodic message send, receive, process;
BC module can carry out 1553B bus message mistake retry, and retry condition and retry bus selection adopt IP kernel default value or arranged by host side;
BC module can carry out 1553B bus message error injection, and for testing RT error detecting and handling ability, type of error adopts IP kernel default value or arranged by host side.
5. the global function 1553B bus IP Core based on chained list according to claim 1, is characterized in that:
BC module is the initiation unit of 1553B bus message, comprises BC Message recover signature submodule, BC memory read/write controls submodule, inner buffer district;
BC module reads the configuration information in global register, reads BC Message recover signature block and BC data control block, and extracts 1553B bus message, send to transceiver by scrambler by bus arbiter module from external memory storage;
Message in 1553B bus by transceiver, demoder, is transferred to message resolution module, message resolution module by this transmission of messages to BC module;
After message sends and receiving course completes, whether BC module sends interrupt request to interrupt module according to interrupt configuration Determines.
6. the global function 1553B bus IP Core based on chained list according to claim 1, is characterized in that:
RT module is the respondent of 1553B message, comprises RT Message Processing submodule, RT memory read/write controls submodule, inner buffer district;
Message in 1553B bus by transceiver, demoder, is transferred to message resolution module, message resolution module by transmission of messages to RT module;
RT module is according to the RT address of command word in message and RT subaddressing, pass through bus arbiter module, from external memory storage, RT address list corresponding for this RT, RT filter list, RT controll block, RT DSB data store block are read into inner buffer district, and respond suitable status word according to command word;
After message sends and receiving course completes, whether RT module sends interrupt request to interrupt module according to interrupt configuration Determines.
7. the global function 1553B bus IP Core based on chained list according to claim 1, is characterized in that:
BM module in charge carries out record to 1553B bus data, comprises BM record controls submodule, inner buffer district;
BM module, by bus arbiter module, obtains the active configuration information of BM module from global register;
When receiving the message that message resolution module transmission comes, BM module passes through bus arbiter module, BM filter list, BM controll block, BM DSB data store block is read from external memory storage, and according to the configuration information of BM filter block and BM controll block, determine that whether this message is stored in BM DSB data store block;
After completing storage, whether BM module sends interrupt request to interrupt module according to interrupt configuration Determines.
8. the global function 1553B bus IP Core based on chained list according to claim 1, is characterized in that:
Self-detection module completes power-on self-test survey, initialization Autonomous test, periodically Autonomous test;
Self-detection module reads Autonomous test order by bus arbiter module from global register, and the result of detection is written in global register.
9. the global function 1553B bus IP Core based on chained list according to claim 1, it is characterized in that: the described inside of the global function 1553B bus IP Core based on chained list and external interface all adopt unified wishbone STD bus, repeatedly this IP kernel of exampleization, just can realize multiple 1553B equipment.
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| CN104717155B (en) * | 2013-12-15 | 2017-10-24 | 中国航空工业集团公司第六三一研究所 | Network traffics process circuit and method in a kind of sampling system |
| CN104717087B (en) * | 2013-12-15 | 2018-02-06 | 中国航空工业集团公司第六三一研究所 | A kind of flow process circuit and method for supporting small business |
| CN104199794A (en) * | 2014-09-04 | 2014-12-10 | 上海航天电子通讯设备研究所 | Co-processor system and co-processing method for 1553B bus |
| CN104317764B (en) * | 2014-10-10 | 2017-11-10 | 北京石竹科技股份有限公司 | A kind of real-time control method of 1553B buses asynchronous message |
| CN107579894B (en) * | 2017-09-22 | 2020-03-20 | 成都旋极历通信息技术有限公司 | FPGA-based EBR1553 bus protocol implementation device |
| CN108092865B (en) * | 2017-11-28 | 2020-07-14 | 北京空间技术研制试验中心 | Balanced distribution method for periodic bus messages |
| CN109450761B (en) * | 2018-12-20 | 2021-07-30 | 成都旋极历通信息技术有限公司 | Multifunctional 1553B communication module |
| CN110213143B (en) * | 2019-05-21 | 2021-04-09 | 中国科学院国家空间科学中心 | 1553B bus IP core and monitoring system |
| CN112235207B (en) * | 2020-10-14 | 2023-02-03 | 天津津航计算技术研究所 | RT address-based 1553B message receiving method |
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