CN107579894B - FPGA-based EBR1553 bus protocol implementation device - Google Patents
FPGA-based EBR1553 bus protocol implementation device Download PDFInfo
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Abstract
The invention discloses an EBR1553 bus protocol implementation device based on an FPGA. The system comprises a host interface module, a BM recording module, a scheduling module, a message sending control module, a message processing module, a logic hub control module, an encoding module and a decoding module. The modules realize BC, 31 RT and BM functions specified by EBR1553 completely through FPGA internal logic and can synthesize a protocol stack. Through the mode, the multifunctional EBR1553 protocol stack can be realized by using the FPGA, so that the cost and the complexity of simulation and test are reduced.
Description
Technical Field
The invention relates to the technical field of bus communication, simulation and test, in particular to an EBR1553 bus protocol implementation device based on an FPGA.
Background
In order to meet the requirements of increasing the complexity of avionics, improving the real-time performance, improving the transmission rate and the like, the American SAE organization formulates an EBR1553 bus protocol on the basis of the MIL-STD-1553B standard. The bus protocol uses a star topology, employs a subset of MIL-STD-1553B messages, again consisting of BC (bus controller), RT (remote terminal) and BM (bus monitoring). At present, the functions of EBR1553 protocol stack products can only realize single functions, namely, one of BC, RT and BM with limited quantity is realized in a time-sharing manner. In the actual bus simulation and test process, a complex network environment needs to be built according to the star topology structure of the EBR1553 by using the single-function EBR1553 protocol stack product, so that the cost and the complexity of the simulation and test are increased, and the efficiency is reduced.
Disclosure of Invention
The technical problem mainly solved by the invention is to provide the EBR1553 bus protocol implementation device based on the FPGA, which can use the FPGA to implement a multifunctional EBR1553 protocol stack so as to reduce the cost and complexity of simulation and test.
In order to solve the technical problems, the invention adopts a technical scheme that: the device for realizing the EBR1553 bus protocol based on the FPGA comprises a host interface module, a BM recording module, a scheduling module, a message sending control module, a message processing module, a logic line concentration control module, a coding module and a decoding module; the encoding module is used for converting the EBR1553 message words from parallel communication into serial communication, converting the EBR1553 message words from a unipolar non-return-to-zero code into a unipolar Manchester code to obtain a data stream, and sending the encoded data stream to the outside through RT interfaces, wherein the number of the RT interfaces is 31; the decoding module is used for detecting whether the coding module is in a sending enabling state or a sending forbidding state currently, receiving an internal data stream coded by the coding module when the coding module is in the sending enabling state, receiving an external data stream from an RT interface when the coding module is in the sending forbidding state, judging whether the internal data stream or the external data stream is a legal EBR1553 message word or not, converting the internal data stream or the external data stream from a unipolar Manchester code into a unipolar non-return-to-zero code to obtain an EBR1553 message word when the internal data stream or the external data stream is the legal EBR1553 message word, converting the EBR1553 message word from serial communication into parallel communication and uploading the converted EBR1553 message word to the logical edit set control module; the logic centralized control module is used for determining the type of a message word currently sent by the message sending control module, controlling the coding module to send the message word to an RT interface when the currently sent message word belongs to BC message, sending a data word and a state word to a corresponding RT interface according to a current RT interface mapping table when the currently sent message word belongs to RT message, monitoring the EBR1553 message word uploaded by the decoding module in real time, receiving the EBR1553 message word of the corresponding RT interface according to the current RT interface mapping table, discarding the EBR1553 message word when the RT interface address in the command word or the state word of the received EBR1553 message word is illegal, uploading the discarded EBR1553 message word to the message processing module when more than one EBR1553 message word of the corresponding RT interface is discarded, and when the RT interface address field in the command word of the received EBR1553 message word is 0, the RT interface address in the command word is modified into the current RT interface address and then uploaded to the message processing module; the message processing module is used for judging whether the currently received EBR1553 message word belongs to the preset message word which is currently required to be received and has 8 legal types or not according to the current receiving state machine, if the currently received EBR1553 message word belongs to the preset message word, informing the host interface module to finish updating the message word to be sent or sending a start sending application to the scheduling module according to the type of the preset message word, caching the EBR1553 message word uploaded by the logic hub control module, and uploading the cached EBR1553 message word to the BM recording module; the scheduling module is used for receiving a start sending application from the message processing module and the host, determining the type of a message word needing to be sent currently according to the start sending application, writing the BC message into the message sending control module through the host interface module when the BC message needs to be sent, and sending a start sending command to the message sending control module, and when the RT message needs to be sent, if an RT address and a sub-address in an internal RT enable register are in an enable state, automatically sending the start sending command to the message sending control module; the message sending control module is used for caching BC messages and RT messages from a host interface module and informing the logic centralized control module whether the messages sent currently are BC messages or RT messages according to the starting sending command; the BM recording module is used for packing and caching the EBR1553 message words, adding time mark information and state information in the packed EBR1553 message words, and informing a host computer to read the message packet through the host computer interface module; the host interface module is used for establishing communication connection with a host so that the host can complete reading and writing of the message packet.
The logic bus control module is specifically configured to, when a currently sent message word belongs to a BC message, determine a BC message sending mode, if the BC message sending mode is a SPEC sending mode, control the encoding module to send the message word to all RT interfaces, if the SPEC sending mode is a SWITCH sending mode, control the encoding module to send the message word to a corresponding RT interface after querying a RT interface mapping table, and if the SWITCH sending mode is a LINK sending mode, query the RT interface mapping table, clear 0 from an RT address field of a command word in the message word, and control the encoding module to send the message word to the corresponding RT interface.
And the coding module is also used for carrying out synchronous head addition and parity check on the coded data stream and then sending the coded data stream to the outside through an RT interface.
The decoding module is further configured to perform parity check when the EBR1553 message word is obtained.
The scheduling module is further configured to complete control of message response time, message interval time, and BC message linked list transmission.
The device also comprises a register which is used for caching the message packet written by the host to the host interface module and the message packet required to be read by the host.
The invention has the beneficial effects that:
the EBR1553 protocol stack is realized through internal logic of the FPGA, any IP core (IntellulalProperty core) resource can not be used, and the EBR1553 protocol stack can be directly used on each series of FPGA of each brand without transplantation;
2, the EBR1553 protocol stack is designed by adopting a VHDL language, and the functions of the protocol stack realized by using a VHDL code can be arbitrarily cut and increased, so that the modification is convenient;
the EBR1553 can realize multiple functions, can be compatible with a single function downwards, and is suitable for various application occasions.
Drawings
Fig. 1 is a schematic structural diagram of an apparatus for implementing an FPGA-based EBR1553 bus protocol according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic structural diagram of an apparatus for implementing an EBR1553 bus protocol based on an FPGA according to an embodiment of the present invention. The EBR1553 bus protocol implementation apparatus of this embodiment includes a host interface module 1, a BM recording module 2, a scheduling module 3, a message sending control module 4, a message processing module 5, a logic line concentration control module 6, an encoding module 7, and a decoding module 8:
the encoding module 7 is configured to convert the EBR1553 message words from parallel communication to serial communication, convert the EBR1553 message words from a unipolar non-return-to-zero code to a unipolar manchester code to obtain a data stream, and send the encoded data stream to the outside through an RT interface, where the number of the RT interfaces is 31. In this embodiment, the encoding module 7 is further configured to perform sync header addition and parity check on the encoded data stream, and then send the encoded data stream to the outside through the RT interface.
The decoding module 8 is configured to detect whether the encoding module 7 is currently in a transmission enabled state or a transmission disabled state, receive the internal data stream encoded by the encoding module 7 when the encoding module 7 is in the transmission enabled state, receive the external data stream from the RT interface when the encoding module 7 is in the transmission disabled state, determine whether the internal data stream or the external data stream is a legal EBR1553 message word, convert the internal data stream or the external data stream from the unipolar manchester code to the unipolar non-return-to-zero code to obtain the EBR1553 message word when the internal data stream or the external data stream is the legal EBR1553 message word, convert the EBR1553 message word from serial communication to parallel communication, and upload the EBR1553 message word to the logic integrated line control module 6. In this embodiment, the decoding module 8 is further configured to perform parity check when the inner data stream or the outer data stream is converted from the unipolar manchester code to the unipolar non-return-to-zero code to obtain the EBR1553 message word.
The logic centralized control module 6 is used for determining the type of the message word currently sent by the message sending control module 4, when the currently sent message word belongs to a BC message, the control coding module 7 sends the message word to an RT interface, when the currently sent message word belongs to an RT message, the control coding module 7 sends a data word and a status word to a corresponding RT interface according to a current RT interface mapping table, and is also used for monitoring the EBR1553 message word uploaded by the decoding module 8 in real time, receives the EBR1553 message word of the corresponding RT interface according to the current RT interface mapping table, when the RT interface address in the command word or the status word of the received EBR1553 message word is illegal, discards the EBR1553 message word, when more than one EBR1553 message word of the corresponding RT interface is discarded, uploads the discarded EBR1553 message word to the message processing module 5, when the RT interface address field in the command word of the received EBR1553 message word is 0, and the RT interface address in the command word is modified into the current RT interface address and then uploaded to the message processing module 5.
The message processing module 5 is configured to determine whether a currently received EBR1553 message word belongs to a preset message word that needs to be received currently in 8 legal types according to a current receiving state machine, and if the currently received EBR1553 message word belongs to the preset message word, notify the host interface module 1 to complete updating of the message word to be sent or send a start-up sending application to the scheduling module 3 according to the type of the preset message word, cache the EBR1553 message word uploaded by the logic hub control module 6, and upload the cached EBR1553 message word to the BM recording module 2.
The scheduling module 3 is configured to receive a start transmission application from the message processing module 5 and the host, determine a type of a message word that needs to be currently transmitted according to the start transmission application, write the BC message into the message transmission control module 4 through the host interface module 1 when the BC message needs to be transmitted, and transmit a start transmission command to the message transmission control module 4, and when the RT message needs to be transmitted, automatically transmit the start transmission command to the message transmission control module 4 if the RT address and the sub-address in the internal RT enable register are in an enable state. In this embodiment, the scheduling module 3 is further configured to complete control of message response time, message interval time, and BC message linked list transmission.
The message sending control module 4 is configured to cache the BC message and the RT message from the host interface module 1, and notify the logic hub control module 6 whether the currently sent message is the BC message or the RT message according to the sending start command.
The BM recording module 2 is used for packing and caching the EBR1553 message words, adding time mark information and state information in the packed EBR1553 message words, and informing a host to read the message packet through the host interface module 1.
The host interface module 1 is used to establish a communication connection with the host, so that the host completes reading and writing of the message packet.
Considering that when a currently sent message word belongs to a BC message, there are three sending modes, which are SPEC, SWITCH and LINK sending modes, respectively, in this embodiment, the logic line concentration control module 6 is specifically configured to determine the BC message sending mode when the currently sent message word belongs to the BC message, if the currently sent message word belongs to the BC message sending mode, control the encoding module 7 to send the message word to 31 RT interfaces, if the currently sent message word belongs to the SWITCH sending mode, after querying the RT interface mapping table, control the encoding module 7 to send the message word to the corresponding RT interface, and if the currently sent message word belongs to the LINK sending mode, after clearing 0 from the RT address field of the command word in the message word, control the encoding module 7 to send the message word to the corresponding RT interface. In this way, the logic bus control module 6 can support BC and 31 RTs working simultaneously.
In this embodiment, the EBR1553 bus protocol implementation apparatus further includes a register 9, where the register 9 is used to cache a message packet written by the host to the host interface module 1 and a message packet that needs to be read by the host. The host interface module 1 provides the host with the capability of accessing the register 9, and the host interface module 1 can notify the host of completing the reading and writing of the message packet through the interrupt.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (6)
1. An EBR1553 bus protocol implementation device based on FPGA is characterized by comprising a host interface module, a BM recording module, a scheduling module, a message sending control module, a message processing module, a logic line concentration control module, an encoding module and a decoding module;
the encoding module is used for converting the EBR1553 message words from parallel communication into serial communication, converting the EBR1553 message words from a unipolar non-return-to-zero code into a unipolar Manchester code to obtain a data stream, and sending the encoded data stream to the outside through RT interfaces, wherein the number of the RT interfaces is 31;
the decoding module is used for detecting whether the coding module is in a sending enabling state or a sending forbidding state currently, receiving an internal data stream coded by the coding module when the coding module is in the sending enabling state, receiving an external data stream from an RT interface when the coding module is in the sending forbidding state, judging whether the internal data stream or the external data stream is a legal EBR1553 message word or not, converting the internal data stream or the external data stream from a unipolar Manchester code into a unipolar non-return-to-zero code to obtain an EBR1553 message word when the internal data stream or the external data stream is the legal EBR1553 message word, converting the EBR1553 message word from serial communication into parallel communication and uploading the converted EBR1553 message word to the logical edit set control module;
the logic centralized control module is used for determining the type of a message word currently sent by the message sending control module, controlling the coding module to send the message word to an RT interface when the currently sent message word belongs to BC message, sending a data word and a state word to a corresponding RT interface according to a current RT interface mapping table when the currently sent message word belongs to RT message, monitoring the EBR1553 message word uploaded by the decoding module in real time, receiving the EBR1553 message word of the corresponding RT interface according to the current RT interface mapping table, discarding the EBR1553 message word when the RT interface address in the command word or the state word of the received EBR1553 message word is illegal, uploading the discarded EBR1553 message word to the message processing module when more than one EBR1553 message word of the corresponding RT interface is discarded, and when the RT interface address field in the command word of the received EBR1553 message word is 0, the RT interface address in the command word is modified into the current RT interface address and then uploaded to the message processing module;
the message processing module is used for judging whether the currently received EBR1553 message word belongs to the preset message word which is currently required to be received and has 8 legal types or not according to the current receiving state machine, if the currently received EBR1553 message word belongs to the preset message word, informing the host interface module to finish updating the message word to be sent or sending a start sending application to the scheduling module according to the type of the preset message word, caching the EBR1553 message word uploaded by the logic hub control module, and uploading the cached EBR1553 message word to the BM recording module;
the scheduling module is used for receiving a start sending application from the message processing module and the host, determining the type of a message word needing to be sent currently according to the start sending application, writing the BC message into the message sending control module through the host interface module when the BC message needs to be sent, and sending a start sending command to the message sending control module, and when the RT message needs to be sent, if an RT address and a sub-address in an internal RT enable register are in an enable state, automatically sending the start sending command to the message sending control module;
the message sending control module is used for caching BC messages and RT messages from a host interface module and informing the logic centralized control module whether the messages sent currently are BC messages or RT messages according to the starting sending command;
the BM recording module is used for packing and caching the EBR1553 message words, adding time mark information and state information in the packed EBR1553 message words, and informing a host computer to read the message packet through the host computer interface module;
the host interface module is used for establishing communication connection with a host so that the host can complete reading and writing of the message packet.
2. The EBR1553 bus protocol implementation device of claim 1, wherein the logic bus control module is specifically configured to determine a BC message transmission mode when a currently transmitted message word belongs to a BC message, control the encoding module to transmit the message word to all RT interfaces if the currently transmitted message word belongs to the BC message, control the encoding module to transmit the message word to a corresponding RT interface after querying an RT interface mapping table if the currently transmitted message word belongs to the SPEC transmission mode, and control the encoding module to transmit the message word to a corresponding RT interface after querying an RT interface mapping table if the currently transmitted message word belongs to the SWITCH transmission mode, or control the encoding module to transmit the message word to the corresponding RT interface after clearing 0 from an RT address field of a command word in the message word.
3. The EBR1553 bus protocol implementation apparatus of claim 1, wherein the encoding module is further configured to perform sync header addition and parity check on the encoded data stream and then send the encoded data stream out through an RT interface.
4. The EBR1553 bus protocol implementation device of claim 1, wherein the decoding module is further configured to perform parity checking when an EBR1553 message word is obtained.
5. The EBR1553 bus protocol implementing device of claim 1, wherein the scheduling module is further configured to complete control of message response time, message interval time, and BC message linked list transmission.
6. The EBR1553 bus protocol implementation apparatus of claim 1, further comprising a register for buffering message packets written by the host to the host interface module and message packets that need to be read by the host.
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| CN109542818A (en) * | 2018-11-16 | 2019-03-29 | 陕西千山航空电子有限责任公司 | A kind of general 1553B interface arrangement |
| CN109450761B (en) * | 2018-12-20 | 2021-07-30 | 成都旋极历通信息技术有限公司 | Multifunctional 1553B communication module |
| CN110188054B (en) * | 2019-05-27 | 2023-10-27 | 中国航空无线电电子研究所 | 1553 bus network product |
| CN116232964B (en) * | 2023-03-07 | 2024-05-03 | 深圳市中航工控半导体有限公司 | Monitoring method for realizing RTMT function in 1553B bus communication network |
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