CN110188054B - 1553 bus network product - Google Patents
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- CN110188054B CN110188054B CN201910445670.7A CN201910445670A CN110188054B CN 110188054 B CN110188054 B CN 110188054B CN 201910445670 A CN201910445670 A CN 201910445670A CN 110188054 B CN110188054 B CN 110188054B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention discloses a 1553 bus network product, which is realized by an FPGA and comprises 1553 bus network protocol software and a 1553 bus network protocol logic IP core; the 1553 bus network protocol logic IP core is used for analyzing 1553 bus data and performing protocol processing and comprises more than one RT module, more than one BC module and a BM module; the RT module uploads a datagram on a 1553 bus to the BM module, the BC module uploads an error state of a message on the 1553 bus to the BM module, and the BM module transmits the data uploaded by the RT module and the BC module to 1553 bus network protocol software; the 1553 bus network protocol software is used for data transmission and forwarding. The invention greatly reduces the dependence of the product on a hardware platform, improves the stability, reliability and reusability of the product, and obviously reduces the development and maintenance cost of the product.
Description
Technical Field
The invention relates to the field of airborne bus networks of avionics systems, in particular to a 1553 bus network product composed of logic cores of an FPGA.
Background
The 1553 bus network product is widely applied to the aerospace field, the requirements of the current market on the miniaturization, low power consumption, low cost and high reliability of the 1553 bus network product are increasingly increased, and the current design mode of the FPGA external protocol processing chip cannot meet the requirements of users. Accordingly, there is an increasing demand for design of a 1553 bus network logical IP core capable of replacing a protocol processing chip. In addition, in order to implement the application of the 1553 bus network protocol, a set of software drivers and testing environments capable of adapting to the network protocol IP need to be developed.
In conclusion, the design and implementation of the 1553 bus network protocol are realized based on the FPGA, including the IP core design, the bus network software design and the test environment design of the 1553 bus network protocol. The technology implementation method capable of greatly improving the design of the 1553 bus network product is provided based on the current market demand and the development prospect of the 1553 bus network product.
Disclosure of Invention
The invention aims to provide a 1553 bus network product which is used for meeting the different requirements of different projects on the 1553 bus network product and meeting the requirements of the current market on the miniaturization, low power consumption, low product design and maintenance cost of the 1553 bus network product. The 1553 bus network product designed by the invention greatly reduces the dependence of the product on a hardware platform, improves the stability, reliability and reusability of the product, and obviously reduces the development and maintenance cost of the product.
The invention aims at realizing the following technical scheme:
a1553 bus network product is realized by an FPGA and comprises 1553 bus network protocol software and a 1553 bus network protocol logic IP core;
the 1553 bus network protocol logic IP core is used for analyzing 1553 bus data and performing protocol processing and comprises more than one RT module, more than one BC module and a BM module; the RT module uploads a datagram on a 1553 bus to the BM module, the BC module uploads an error state of a message on the 1553 bus to the BM module, and the BM module transmits the data uploaded by the RT module and the BC module to 1553 bus network protocol software;
the 1553 bus network protocol software is used for data transmission and forwarding.
Preferably, the RT module comprises an RT data transceiver module and an RT message control/filtering module;
the RT data transceiver module is used for controlling the analysis and the generation of the waveform of the bus message;
the RT message control/filtering module is used for responding to a channel used by the BC command word, if the RT number in the received BC command word is irrelevant to the RT number, the RT message control/filtering module does not respond, otherwise, the validity of the command word is checked, and if the sub address in the command word is not in the valid range or the command word is invalid, the RT message control/filtering module does not respond; and simultaneously, the received datagrams are sent to the BM module through a data record input channel of the BM data FIFO.
Preferably, the RT data transceiver module includes a first transmitting module, where the first transmitting module includes a first command status FIFO, a first data FIFO, a first transmission control interface, a first bus channel status, and a first manchester encoder, and a data transmission flow is as follows:
1) The RT message control/filtering module sends the data needing to be continuously sent into a first command state FIFO;
2) The RT message control/filtering module sends the number of the words needing to be continuously sent into a first data FIFO;
3) The first sending control interface checks whether the first data FIFO is empty or not, checks whether a channel in the channel state of the first bus is empty or not, and if the first data FIFO is not empty and the channel state is empty, reads the number N of the words which need to be continuously sent of a data packet from the first data FIFO;
4) The first transmission control interface controls the first Manchester encoder to transmit the data in the first command state FIFO and the N words in the first data FIFO to the data record input path of the BM data FIFO.
Preferably, the RT data transceiver module includes a first receiving module, where the first receiving module includes a first receiving control interface, a first control signal receiver, a first receiving data FIFO, a first receiving data number FIFO, and a first receiving window control module, and a data receiving flow is as follows:
1) The first receiving control interface detects receiving signals RxD+ and RxD-, the first control signal receiver receives data under a receiving window and stores the data into a first receiving data FIFO, and the first receiving window control module is controlled to be opened and closed by the first control signal receiver according to a synchronous head and a baud rate in the receiving signals;
2) The first receiving control interface stores the number of the received message data into a first receiving data number FIFO;
3) The RT message control/filtering module reads the data in the first received data FIFO through the new data identifier in the first received data number FIFO.
Preferably, the BC module comprises a BC data transceiver module and a BC message control module;
the BC data receiving and transmitting module is used for controlling analysis and generation of bus message waveforms;
the BC message control module is used for completing the transmission control of the message, error detection and retry, switching transmission channels, and simultaneously, transmitting the state of message error to the BM module through the data record input channel of the error state data FIFO.
Preferably, the BC data transceiver module comprises a second transmission module, the second transmission module comprising a second command status FIFO, a second data FIFO, a second transmission control interface, a second bus channel status, and a second manchester encoder, and the data transmission process is as follows:
1) The BC message control module sends the data to be continuously sent into a second command state FIFO;
2) The BC message control module sends the number of the words to be continuously sent to the second data FIFO;
3) The second sending control interface checks whether the second data FIFO is empty or not, checks whether a channel in the second bus channel state is empty or not, and if the second data FIFO is not empty and the channel state is empty, reads the number N of the continuous sent data packets from the second data FIFO;
4) The second transmit control interface controls the second Manchester encoder to transmit the data in the second command state FIFO and the N words in the second data FIFO to the data record input path of the error state data FIFO.
Preferably, the BC data transceiver module comprises a second receiving module, the second receiving module comprises a second receiving control interface, a second control signal receiver, a second receiving data FIFO, a second receiving data number FIFO, and a second receiving window control module, and the data receiving flow is as follows:
1) The second receiving control interface detects the receiving signals RxD+ and RxD-, the second control signal receiver receives data under a receiving window and stores the data into a second receiving data FIFO, and the second receiving window control module is controlled to be opened and closed by the second control signal receiver according to the synchronous head and the baud rate in the receiving signals;
2) The second receiving control interface stores the received data number of one message into a second receiving data number FIFO;
3) The BC message control module reads the data in the second received data FIFO through the new data identifier in the second received data number FIFO.
Preferably, the BM module comprises a BM control module, a BM data FIFO consisting of an RT data record FIFO and an RT control FIFO, an error status data FIFO consisting of a BC data record FIFO and a BC control FIFO;
the RT data record FIFO is used for storing the datagrams uploaded by the RT module;
the RT control FIFO is used for storing the control information uploaded by the RT module;
the BC data record FIFO is used for storing datagrams uploaded by the BC module;
the BC control FIFO is used for storing control information uploaded by the BC module;
the BM control module polls each data record input channel of the BM data FIFO and the error state data FIFO, when data records exist, takes out a corresponding datagram and control information from the RT data record FIFO and the RT control FIFO or the BC data record FIFO and the BC control FIFO, packages the datagram and the control information, stores the datagram and the control information into a data buffer area, and takes out the data record from the data buffer area according to an instruction of 1553 bus network protocol software and uploads the data record to the 1553 bus network protocol software.
Preferably, the bus network protocol software module comprises:
control layer: controlling switching among the RT module, the BC module and the BM module, and mode switching; the modes include BC mode, RT mode, BM mode;
service processing layer: according to the mode set by the control layer, making correspondent mode treatment,
interface adaptation layer: aiming at read-write access processing of different hardware interfaces, the layer packages the different hardware interfaces into different modules respectively;
hardware adaptation layer: the hardware adaptation layer realizes access and operation of the 1553 bus network protocol logic IP core, and adapts to different running hardware platforms.
The invention has the beneficial effects that:
the 1553 bus network protocol is realized through the 1553 bus network protocol logic IP card, the functions of BC (bus controller), RT (remote terminal) and BM (bus monitoring) in the 1553 bus protocol are integrated, and the system has IP core expansibility.
And a plurality of RT modules and a plurality of BC modules can be flexibly configured according to requirements, so that the function of multi-path 1553 bus communication is realized.
Drawings
FIG. 1 is a schematic diagram of a 1553 bus network product;
FIG. 2 is a schematic diagram of a 1553 bus network protocol logic IP core structure;
FIG. 3 is a schematic diagram of an RT data transceiver module;
fig. 4 is a schematic structural diagram of 1553 bus network protocol software;
FIG. 5 is a schematic diagram of a 1553 bus network product testing environment;
fig. 6 is a schematic structural diagram of a 1553 bus network hardware module;
fig. 7 is a software schematic diagram of a 1553 bus network hardware module.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples.
Example 1
As shown in fig. 1. The 1553 bus network product shown in the embodiment mainly comprises 1553 bus network protocol software and a 1553 bus network protocol logic IP core. The 1553 bus network protocol software mainly has the functions of shielding the implementation details of the logic IP check application, carrying out data transmission and forwarding, providing a data interaction interface of a protocol layer and a driving layer, integrating BC (bus controller), RT (remote terminal) and BM (bus monitoring) functions in the 1553 bus protocol by the 1553 bus network protocol logic IP core, and mainly has the functions of analyzing 1553 bus data, carrying out protocol processing and realizing the analysis and processing functions of the protocol.
1553 bus network protocol logic IP core
As shown in fig. 2, an illustration of 1553 bus network protocol logic IP is provided, comprising RT module, BC module and BM module. Wherein, the BM module has only one; the RT module and the BC module can flexibly configure a plurality of RT modules and a plurality of BC modules according to requirements, which is an advantage place compared with a protocol chip. The 1553 bus network protocol logic IP core is implemented in a multi-path bus interface module (Multi Bus Interface, hereinafter referred to as MBI module), and a main processing module (Host Processor Module, hereinafter referred to as HPM) controls the MBI module through a PCIE bus to implement 1553 bus data communication and processing.
1. RT module
The RT module mainly comprises an RT data transceiver module and an RT message control/filtering module, wherein the RT data transceiver module is mainly used for realizing data receiving and transmitting, the receiver is provided with a function of recording the arrival time of a datagram, detecting Manchester coding errors, bit number errors, parity errors and the like of message command words or data words and the like in received data, and the RT message control/filtering module is mainly used as a protocol processing function.
As shown in fig. 3, the RT data transceiver module includes a first transmitting module and a first receiving module, and a data transmission flow of the first transmitting module is as follows:
1) The RT message control/filtering module (U0) sends data (command/state, data) to be continuously sent into a first command state FIFO (U1);
2) The RT message control/filtering module (U0) sends the number of words (one frame number, containing command/state and data) needing to be continuously sent into the first data FIFO (U2);
3) The first sending control interface (U5) checks whether the first data FIFO (U2) is empty or not, checks whether a first bus channel state (U8) channel is idle or not, and if the first data FIFO (U2) is not empty and the channel state is idle, reads the number N of the words which need to be continuously sent of a data packet from the first data FIFO (U2);
4) The first transmission control interface (U5) controls the first manchester encoder (U7) to transmit the data (command word/status word) in the first command status FIFO (U1) and the N numbers (data words) in the first data FIFO (U2).
The data receiving flow of the first receiving module is as follows:
1) The first receiving control interface (U6) detects the received signals RxD+ and RxD-, the first control signal receiver (U9) receives and stores data into the first receiving data FIFO (U3) under a receiving window, and the first receiving window control module is controlled to be opened and closed by the first control signal receiver (U9) according to a synchronous head and a baud rate in the received signals;
2) The first receiving control interface (U6) stores the number of received message data into a first received data number FIFO (U4);
3) The RT message control/filter module (U0) reads the data in the first receive data FIFO (U3) through the new data identification in the first receive data number FIFO (U4).
In the RT message control/filtering module, the data read from the RT data transceiver module is parsed according to 1553 protocol. The RT message control/filtering module responds to the channel used by the BC command word, and if the RT number in the received BC command word is irrelevant to the RT number, the RT message control/filtering module does not respond, i.e. filters the message irrelevant to the RT number. If the sub address in the received BC command word is not in the valid range or the command word is invalid, the RT message control/filtering module does not respond, such as a bus message Manchester encoding error, a bit number error of a message command word or a data word, and a parity error exist, and the RT message control/filtering module sets an error identification and replies a response word with an error state set. And meanwhile, the received datagrams are sent to the BM module through a data record input channel of the BM data FIFO.
The RT message control/filtering module organizes command words and data words of 1553 bus messages according to the setting in the register and the requirement, wherein the command words are defined according to the register of the logic IP core, and the data words are derived from the data transceiver module when RT sending operation is executed; when performing RT receive class operations, the data word is sourced from the data buffer. When the RT works, the RT message control/filtering module organizes data transmission/reception according to the message command word on the 1553 bus, generates and transmits a response word in a specified time, and processes the data through the data receiving and transmitting module when the data is transmitted/received.
2. BC module
The BC module mainly comprises a BC data transceiver module and a BC message control module, the structure of the BC data transceiver module and the structure of the RT data transceiver module are basically the same, and the BC module is mainly used for realizing data transceiving, wherein the receiver is provided with a function of recording the arrival time of a datagram, detecting the Manchester coding error, the bit number error of a message command word or a data word, the parity error and the like in received data, and the BC message control module is mainly used as a protocol processing function.
The BC data transceiver module comprises a second sending module and a second receiving module, and the data sending flow of the second sending module is as follows:
1) The BC message control module sends the data (command/state, data) to be continuously sent into a second command state FIFO;
2) The BC message control module sends the number of the words (one frame number, containing commands/states and data) to be continuously sent into a second data FIFO;
3) The second sending control interface checks whether the second data FIFO is empty or not, checks whether a second bus channel state channel is empty or not, and if the second data FIFO is not empty and the channel state is empty, reads the number N of the continuous sent data packets from the second data FIFO;
4) The second transmission control interface controls the second manchester encoder to finish transmitting the data (command word/status word) in the second command status FIFO and the N numbers (data words) in the second data FIFO.
The data receiving flow of the second receiving module is as follows:
1) The second receiving control interface detects the receiving signals RxD+ and RxD-, the second control signal receiver receives data under a receiving window and stores the data into a second receiving data FIFO, and the second receiving window control module is controlled to be opened and closed by the second control signal receiver according to the synchronous head and the baud rate in the receiving signals;
2) The second receiving control interface stores the received data number of one message into a second receiving data number FIFO;
3) The BC message control module (U0) reads the data in the second received data FIFO (U3) through the new data identifier in the second received data number FIFO.
The BC message control module completes the operations of message transmission control, error detection, retry, transmission channel switching and the like. At the same time, the status of the message error is sent to the BM module via the data record input channel of the error status data FIFO. The error detection includes manchester code error detection, bit number error detection of message command words or data words, parity error detection, and the like.
The BC message control module organizes command words and data words of 1553 bus messages according to the setting in the register and the requirements, wherein the command words are defined according to the register of the logic IP core.
The BC module has the capability of A/B double-channel switching processing, and when the BC message control module judges that the communication is abnormal, the BC message control module actively switches the message transmission channel into another channel.
3. BM module
The BM module includes a BM control module, a BM data FIFO consisting of an RT data record FIFO and an RT control FIFO, and an error status data FIFO consisting of a BC data record FIFO and a BC control FIFO. The BM data FIFO and the error state data FIFO are both in a double-FIFO structure, the BM data FIFO consists of an RT data recording FIFO and an RT control FIFO, and the RT data recording FIFO is used for storing datagrams uploaded by an RT module; the RT control FIFO is used for storing control information such as the length, time scale, datagram type and the like of the datagram uploaded by the RT module. The error state data FIFO consists of a BC data recording FIFO and a BC control FIFO, and the BC data recording FIFO is used for storing datagrams uploaded by the BC module; the BC control FIFO is used for storing the control information of the datagram uploaded by the BC module. The number of data record input channels of the double FIFO structure is configured according to the requirement. The data from the RT module is a datagram on a 1553 bus, and each data record is a datagram on the 1553 bus; the data from the BC module is information such as an error status of a message on the 1553 bus, and each data is recorded as information such as an error status of a message transmitted on the 1553 bus. The BM control module polls the data record input channel of each double FIFO structure, when there is data record, takes out one piece of recorded control information and data, packs it and stores it into the data buffer zone BM_BUF. The data buffer zone BM_BUF adopts a double buffer zone structure, comprises BUF_A and BUF_B, and the BM control module is responsible for the management of two data buffer zones. Another function of the BM control module is to receive the HPM instruction, take the record from the data buffer, parse the record according to the 1553 protocol, and upload the record. And the BM data storage control is responsible for taking out the record in the BM_BUF and storing the record in an off-chip nonvolatile memory (BM flash).
1553 bus network protocol software
The 1553 bus network protocol software is transmission layer software on the upper layer of the 1553 bus network protocol logic IP core, and is used for controlling the initialization, data receiving and transmitting control of the 1553 bus network protocol logic IP core, realizing data transmission of a driving layer and an application layer, and the 1553 bus network protocol software design mainly refers to the generalized design of a bus network software platform. The generalized software is designed according to a modularized and layered design idea, and a detailed software module structure diagram is shown in fig. 4.
1) Control layer: the control layer mainly controls the RT module, the BC module and the BM module in the 1553 bus network protocol logic IP core to switch, and also controls the mode switching, wherein the mode comprises BC mode, RT and BM;
2) Service processing layer: the business processing layer is used for carrying out corresponding mode processing mainly according to the mode set by the control layer, and the layer is used for mainly realizing the functions of modes such as BC, RT, BM and the like under 1553 protocol;
3) Interface adaptation layer: the interface adaptation layer is mainly used for the read-write access processing of different hardware interfaces, and encapsulates the different hardware interfaces into different modules respectively, so that the different hardware interfaces can be completely decoupled;
4) Hardware adaptation layer: the hardware adaptation layer mainly realizes the access and operation of the internal logic IP interface of the FPGA and adapts to different running hardware platforms.
Fig. 6 is a product of a 1553 bus network hardware module developed by using the present embodiment, and the detailed description is as follows:
1) The configuration of the 1553 bus network hardware module is shown in fig. 6. Wherein the FPGA internally comprises
The MircoBlaze soft core and the 1553 protocol logic IP realize the processing of a 1553 bus protocol layer.
2) The software constitution of the 1553 bus network hardware module is shown in FIG. 7
The configuration header files of different projects are stored under the config directory, and different configuration header files are added for the different projects; config.h is the total configuration header file in which configuration header file information is contained; mbi _main.c is the processing program of the main control module; mbi _bc.c/mbi _bc.h/mbi _rt.c/mbi _rt.h, and the like; dp.c/dp.h is a dual port memory interface module handler; protocol_chip.c is a protocol chip interface module handler; hardware_adapter_layer.c is a hardware adaptation module handler; log.c is the log system handler; common_circular_buffer.c is a Common module program that performs Circular Buffer access to dual-port memory.
Referring to fig. 1, the present embodiment also provides a 1553 bus network protocol testing environment, which is mainly used for testing 1553 bus network products.
As shown in fig. 5, the 1553 bus network product test hardware platform should include three main parts: MBI test cartridge, MBI test equipment and power supply unit. The MBI test box is mainly used for loading an MBI module, a main control CPU module, test points and the like; the MBI testing equipment mainly realizes Ethernet and serial port communication with a main control CPU module in the testing box and 1553 communication with the MBI module; the power supply device mainly supplies power to the power supply of the test device and the test box.
The test environment should have the following basic functions:
1) The device has the functions of buses BC, RT and BM and performance test;
2) The bus pressure test function is provided;
3) The bus fault injection testing function is provided;
4) The system has the adaptation test function of MBI modules of various projects;
5) The bus access test function of buses such as PCI/PCIe/custom is provided.
It will be understood that equivalents and modifications will occur to those skilled in the art in light of the present invention and their spirit, and all such modifications and substitutions are intended to be included within the scope of the present invention as defined in the following claims.
Claims (7)
1. A1553 bus network product is realized by an FPGA and comprises 1553 bus network protocol software and a 1553 bus network protocol logic IP core;
the 1553 bus network protocol logic IP core is used for analyzing 1553 bus data and performing protocol processing and comprises more than one RT module, more than one BC module and a BM module; the RT module uploads a datagram on a 1553 bus to the BM module, the BC module uploads an error state of a message on the 1553 bus to the BM module, and the BM module transmits the data uploaded by the RT module and the BC module to 1553 bus network protocol software;
the 1553 bus network protocol software is used for carrying out data transmission and forwarding;
wherein the RT module comprises an RT data transceiver module and an RT message control/filtering module;
the RT message control/filtering module is used for responding to a channel used by the BC command word, if the RT number in the received BC command word is irrelevant to the RT number, the RT message control/filtering module does not respond, otherwise, the validity of the command word is checked, and if the sub address in the command word is not in the valid range or the command word is invalid, the RT message control/filtering module does not respond; the received datagrams are sent to the BM module by a data record input channel of the BM data FIFO;
the RT data transceiver module is used for controlling analysis and generation of bus message waveforms and comprises a first transmitting module, wherein the first transmitting module comprises a first command state FIFO, a first data FIFO, a first transmitting control interface, a first bus channel state and a first Manchester encoder, and the data transmitting flow is as follows:
1) The RT message control/filtering module sends the data needing to be continuously sent into a first command state FIFO;
2) The RT message control/filtering module sends the number of the words needing to be continuously sent into a first data FIFO;
3) The first sending control interface checks whether the first data FIFO is empty or not, checks whether a channel in the channel state of the first bus is empty or not, and if the first data FIFO is not empty and the channel state is empty, reads the number N of the words which need to be continuously sent of a data packet from the first data FIFO;
4) The first transmission control interface controls the first Manchester encoder to transmit the data in the first command state FIFO and the N words in the first data FIFO to the data record input path of the BM data FIFO.
2. The 1553 bus network product of claim 1, wherein the RT data transceiver module further comprises a first receiving module comprising a first receiving control interface, a first control signal receiver, a first receiving data FIFO, a first receiving data number FIFO, a first receiving window control module, and the data receiving flow is as follows:
1) The first receiving control interface detects receiving signals RxD+ and RxD-, the first control signal receiver receives data under a receiving window and stores the data into a first receiving data FIFO, and the first receiving window control module is controlled to be opened and closed by the first control signal receiver according to a synchronous head and a baud rate in the receiving signals;
2) The first receiving control interface stores the number of the received message data into a first receiving data number FIFO;
3) The RT message control/filtering module reads the data in the first received data FIFO through the new data identifier in the first received data number FIFO.
3. A 1553 bus network product according to claim 1, wherein said BC module comprises a BC data transceiver module and a BC message control module;
the BC data receiving and transmitting module is used for controlling analysis and generation of bus message waveforms;
the BC message control module is used for completing the transmission control of the message, error detection and retry, switching transmission channels, and simultaneously, transmitting the state of message error to the BM module through the data record input channel of the error state data FIFO.
4. A 1553 bus network product according to claim 3, wherein said BC data transceiver module comprises a second transmission module comprising a second command status FIFO, a second data FIFO, a second transmission control interface, a second bus channel status, and a second manchester encoder, the data transmission flow being as follows:
1) The BC message control module sends the data to be continuously sent into a second command state FIFO;
2) The BC message control module sends the number of the words to be continuously sent to the second data FIFO;
3) The second sending control interface checks whether the second data FIFO is empty or not, checks whether a channel in the second bus channel state is empty or not, and if the second data FIFO is not empty and the channel state is empty, reads the number N of the continuous sent data packets from the second data FIFO;
4) The second transmission control interface controls the second Manchester encoder to transmit the data in the second command state FIFO and the N words in the second data FIFO to the data record input channel of the dual FIFO structure.
5. A 1553 bus network product according to claim 3, wherein the BC data transceiver module comprises a second receiving module comprising a second receiving control interface, a second control signal receiver, a second received data FIFO, a second received data count FIFO, and a second receiving window control module, the data receiving process comprising:
1) The second receiving control interface detects the receiving signals RxD+ and RxD-, the second control signal receiver receives data under a receiving window and stores the data into a second receiving data FIFO, and the second receiving window control module is controlled to be opened and closed by the second control signal receiver according to the synchronous head and the baud rate in the receiving signals;
2) The second receiving control interface stores the received data number of one message into a second receiving data number FIFO;
3) The BC message control module reads the data in the second received data FIFO through the new data identifier in the second received data number FIFO.
6. A 1553 bus network product according to claim 1 wherein the BM module comprises a BM control module, a BM data FIFO comprised of an RT data record FIFO and an RT control FIFO, an error status data FIFO comprised of a BC data record FIFO and a BC control FIFO;
the RT data record FIFO is used for storing the datagrams uploaded by the RT module;
the RT control FIFO is used for storing the control information uploaded by the RT module;
the BC data record FIFO is used for storing datagrams uploaded by the BC module;
the BC control FIFO is used for storing control information uploaded by the BC module;
the BM control module polls each data record input channel of the BM data FIFO and the error state data FIFO, when data records exist, takes out a corresponding datagram and control information from the RT data record FIFO and the RT control FIFO or the BC data record FIFO and the BC control FIFO, packages the datagram and the control information, stores the datagram and the control information into a data buffer area, and takes out the data record from the data buffer area according to an instruction of 1553 bus network protocol software and uploads the data record to the 1553 bus network protocol software.
7. A 1553 bus network product according to claim 1 wherein the bus network protocol software module comprises:
control layer: controlling switching among the RT module, the BC module and the BM module, and mode switching; the modes include BC mode, RT mode, BM mode;
service processing layer: according to the mode set by the control layer, making correspondent mode treatment,
interface adaptation layer: aiming at read-write access processing of different hardware interfaces, the layer packages the different hardware interfaces into different modules respectively;
hardware adaptation layer: the hardware adaptation layer realizes access and operation of the 1553 bus network protocol logic IP core, and adapts to different running hardware platforms.
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