CN110188054A - 1553 bus network products - Google Patents

1553 bus network products Download PDF

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Publication number
CN110188054A
CN110188054A CN201910445670.7A CN201910445670A CN110188054A CN 110188054 A CN110188054 A CN 110188054A CN 201910445670 A CN201910445670 A CN 201910445670A CN 110188054 A CN110188054 A CN 110188054A
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data
module
fifo
control
bus network
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CN110188054B (en
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马志涛
陈栋
章宇东
万宁
章敏
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China Aeronautical Radio Electronics Research Institute
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China Aeronautical Radio Electronics Research Institute
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Communication Control (AREA)

Abstract

The invention discloses a kind of 1553 bus network products, are realized by FPGA, include the 1553 bus network protocol softwares and 1553 bus network protocol logic IP kernels；1553 bus network protocol logic IP kernels are used to parse 1553 bus datas and protocol processes, include more than one RT module, more than one BC module and a BM module；RT module uploads the datagram in 1553 buses to BM module, and BC module uploads the error condition of 1553 total Thread Messages to BM module, and the data that RT module and BC module upload are transferred to the 1553 bus network protocol softwares by BM module；The 1553 bus network protocol softwares are for carrying out data transmission and forwarding.The present invention greatly reduces product to the dependence of hardware platform, improves the stability, reliability, reusability of product, significantly reduces the exploitation maintenance cost of product.

Description

1553 bus network products
Technical field
It is specifically a kind of to be made of the Logic Core of FPGA the present invention relates to avionics system airborne-bus network field 1553 bus network products.
Background technique
1553 bus network products are widely used in aerospace field, and Vehicles Collected from Market is small to 1553 bus network products Type, low-power consumption, low cost, the demand of high reliability increasingly increase, at present the design method of the external protocol processing chip of FPGA It can no longer meet user demand.Accordingly, it is set for capableing of 1553 bus network logic IP kernels of alternative processing chip Meter demand increasingly improves.In addition, the application in order to realize 1553 bus network agreements, palpus exploitation is a set of being capable of adaptation network agreement The software-driven and test environment of IP.
To sum up, realization is designed to 1553 bus network agreements based on FPGA, including to 1553 bus network protocol IPs Nuclear design, bus network software design, test Environment Design.It is to be sent out based on current market demand and 1553 bus network products What exhibition prospect proposed, the Implementation Technology of 1553 bus network product designs can be greatly improved.
Summary of the invention
Goal of the invention of the invention is to provide a kind of 1553 bus network products, total to 1553 for meeting disparity items The otherness demand of line networking products, and meet miniaturization, low-power consumption, low yield of the Vehicles Collected from Market to 1553 bus network products The demand of product design and maintenance cost.It is flat to hardware to greatly reduce product for the 1553 bus network products that the present invention designs The dependence of platform improves the stability, reliability, reusability of product, significantly reduces the exploitation maintenance cost of product.
Goal of the invention of the invention is achieved through the following technical solutions:
A kind of 1553 bus network products, are realized by FPGA, include the 1553 bus network protocol softwares and 1553 bus networks Network protocol logic IP kernel；
1553 bus network protocol logic IP kernels are used to parse 1553 bus datas and protocol processes, include one A above RT module, more than one BC module and a BM module；RT module uploads the number in 1553 buses to BM module According to report, BC module uploads the error condition of 1553 total Thread Messages to BM module, and BM module uploads RT module and BC module Data are transferred to the 1553 bus network protocol softwares；
The 1553 bus network protocol softwares are for carrying out data transmission and forwarding.
Preferably, the RT module includes RT data transmit-receive module and RT message control/filtering module；
RT data transmit-receive module is used for the parsing and generation of control bus message waveform；
The channel that RT message control/filtering module is used to use BC command word responds, if the BC life received Enable No. RT in word it is unrelated with this RT numbers, then without response, otherwise, the validity of command word is checked, if the life It enables the subaddressing in word not in effective range or the command word is invalid, then without response；The data that will be received simultaneously Report is all sent to BM module by the data record input channel of BM data FIFO.
Preferably, the RT data collector module includes the first sending module, and the first sending module includes the first order State FIFO, the first data FIFO, first send control interface, the first bus channel state and the first Manchester encoder, Data transmission flow is as follows:
1) data for needing to continuously transmit are sent into the first coomand mode FIFO by RT message control/filtering module；
2) the word number for needing to continuously transmit is sent into the first data FIFO by RT message control/filtering module；
3) the first transmission control interface checks whether the first data FIFO is empty, checks that channel is in the first bus channel state The no free time, if channel status is idle simultaneously for the first data FIFO non-empty, a data packet is read from the first data FIFO to be needed The word number N to be continuously transmitted；
4) first send control interface control the first Manchester encoder by the first coomand mode FIFO data and N number of word in first data FIFO is sent to the data record input channel of BM data FIFO.
Preferably, the RT data collector module includes the first receiving module, and the first receiving module includes the first reception Control interface, first control signal receiver, first receive data FIFO, the first reception data amount check FIFO, the first reception window Mouth control module, data receiver process are as follows:
1) first control interface detection reception signal RxD+ and RxD- are received, first control signal receiver is receiving window It is lower by data receiver deposit first receive data FIFO, first receive window controlling module by first control signal receiver according to Synchronous head and the baud rate control received in signal opens and closes；
2) first control interface is received by the first reception of received a piece of news data amount check deposit data amount check FIFO；
3) New Data Flag that RT message control/filtering module is received by first in data amount check FIFO is received first Reading data in data FIFO comes out.
Preferably, the BC module includes BC data transmit-receive module and BC message control module；
BC data transmit-receive module is used for the parsing and generation of control bus message waveform；
BC message control module is used to complete the transmission control of message, error detection and retries, switches transmission channel, together When, by the state of message mistake, BM module is sent to by the data record input channel of error state data FIFO.
Preferably, second sending module of BC data transmit-receive module, the second sending module include the second coomand mode FIFO, the second data FIFO, second send control interface, the second bus channel state and the second Manchester encoder, data Transmission flow is as follows:
1) data for needing to continuously transmit are sent into the second coomand mode FIFO by BC message control module；
2) the word number for needing to continuously transmit is sent into the second data FIFO by BC message control module；
3) the second transmission control interface checks whether the second data FIFO is empty, checks that channel is in the second bus channel state The no free time, if channel status is idle simultaneously for the second data FIFO non-empty, a data packet is read from the second data FIFO to be needed The word number N to be continuously transmitted；
4) second send control interface control the second Manchester encoder by the second coomand mode FIFO data and N number of word in second data FIFO is sent to the data record input channel of error state data FIFO.
Preferably, second receiving module of BC data transmit-receive module, the second receiving module include that the second reception control connects Mouth, second control signal receiver, second receive data FIFO, the second reception data amount check FIFO, the second reception window control Module, data receiver process are as follows:
1) second control interface detection reception signal RxD+ and RxD- are received, second control signal receiver is receiving window It is lower by data receiver deposit second receive data FIFO, second receive window controlling module by second control signal receiver according to Synchronous head and the baud rate control received in signal opens and closes；
2) second control interface is received by the second reception of received a piece of news data amount check deposit data amount check FIFO；
3) New Data Flag that BC message control module is received by second in data amount check FIFO receives data for second Reading data in FIFO comes out.
Preferably, BM module includes BM control module, the BM data being made of RT data record FIFO and RT control FIFO FIFO, the error state data FIFO being made of BC data record FIFO and BC control FIFO；
RT data record FIFO is used to save the datagram of RT module upload；
RT control FIFO is used to save the control information of RT module upload；
BC data record FIFO is used to save the datagram of BC module upload；
BC control FIFO is used to save the control information of BC module upload；
Each data record input channel of BM control module poll BM data FIFO and error state data FIFO, when having When data record, it is corresponding that FIFO or BC data record FIFO and BC control FIFO taking-up one is controlled from RT data record FIFO and RT Datagram and control information after be packaged, data buffer zone is stored in, and according to the instruction of the 1553 bus network protocol softwares The 1553 bus network protocol softwares are uploaded to by data record is taken out in data buffer area.
Preferably, bus network protocol software module includes:
Control layer: control RT module, switching and pattern switching between BC module and BM module；The mode includes BC mode, RT mode, BM mode；
Bussiness processing layer: the mode being arranged according to control layer carries out corresponding mode treatment,
Interface adaptation layer: the read and write access for different hardware interface is handled, this layer seals different hardware interfaces respectively Dress up different modules；
Hardware adaptation layer: hardware adaptation layer realizes the access and operation to 1553 bus network protocol logic IP kernels, for Different operation hardware platforms are adapted to.
The beneficial effects of the present invention are:
1553 bus network agreements are realized by 1553 bus network protocol logic IP kernels, are integrated in 1553 bus protocols BC (bus control unit), RT (remote terminal), BM (monitoring bus) function, and have IP kernel expansibility.
Can the multiple RT modules of flexible configuration and multiple BC modules according to demand, to realize 1553 bus communication of multichannel Function.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of 1553 bus network products；
Fig. 2 is the structural schematic diagram of 1553 bus network protocol logic IP kernels；
Fig. 3 is the structural schematic diagram of RT data collector module；
Fig. 4 is the structural schematic diagram of the 1553 bus network protocol softwares；
Fig. 5 is the structural schematic diagram of 1553 bus network product test environment；
Fig. 6 is the structural schematic diagram of 1553 bus network hardware modules；
Fig. 7 is the software schematic diagram of 1553 bus network hardware modules.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.
Embodiment one
As shown in Figure 1.1553 bus network products shown in the present embodiment mainly include the 1553 bus network protocol softwares With 1553 bus network protocol logic IP kernels.1553 bus network protocol software major functions are mask logic IP kernels to application It realizes details, carries out data transmission and forward, protocol layer is provided and drives the data interaction interface of layer, 1553 bus network agreements Logic IP kernel is integrated with BC (bus control unit), RT (remote terminal), BM (monitoring bus) function in 1553 bus protocols, main Wanting function is to parse to 1553 bus datas and protocol processes, realizes the parsing and processing function of agreement.
(1) 1553 bus network protocol logic IP kernel
As shown in Fig. 2, be one of 1553 bus network protocol logic IP for example, comprising RT module, BC module and BM module.Wherein, BM module, have and only one；RT module, BC module can according to demand the multiple RT modules of flexible configuration and Multiple BC modules, this is than the place with protocol chip advantage.1553 bus network protocol logic IP kernels are in multiple bus interface It is realized in module (Multi Bus Interface, hereinafter referred to as MBI module), main processing block (Host Processor Module, hereinafter referred to as HPM) by PCIE bus marco MBI module, realize 1553 bus data communications and processing.
1, RT module
RT module is mainly made of RT data collector module and RT message control/filtering module, RT data transmit-receive module It is mainly used for realizing data transmit-receive, wherein receiver has the time that record datagram reaches, and detection receives graceful thorough in data The position number mistake of this special code error, information order word or data word etc., parity error etc., RT message control/filtering Module is mainly as protocol processes function.
As shown in figure 3, RT data collector module includes the first sending module and the first receiving module, the first sending module Data transmission flow it is as follows:
1) data (order/state, data) for needing to continuously transmit are sent into first by RT message control/filtering module (U0) Coomand mode FIFO (U1)；
2) RT message control/filtering module (U0) by needs continuously transmit word number (a frame number, contain order/state, Data) it is sent into the first data FIFO (U2)；
3) the first transmission control interface (U5) checks whether the first data FIFO (U2) is empty, checks the first bus channel state (U8) whether channel is idle, if channel status is idle simultaneously for the first data FIFO (U2) non-empty, from the first data FIFO (U2) the word number N that a data packet needs to continuously transmit is read in；
4) first control interface (U5) control the first Manchester encoder (U7) is sent by the first coomand mode FIFO (U1) N number of number (data word) in data (command word/status word) and the first data FIFO (U2) in distributes.
The data receiver process of first receiving module is as follows:
1) first control interface (U6) detection reception signal RxD+ and RxD- are received, first control signal receiver (U9) exists It receives and data receiver deposit first is received into data FIFO (U3) under window, first receives window controlling module is believed by the first control Number receiver (U9) is opened and closed according to synchronous head and the baud rate control received in signal；
2) first control interface (U6) is received by received a piece of news data amount check deposit the first reception data amount check FIFO(U4)；
3) New Data Flag that RT message control/filtering module (U0) is received by first in data amount check FIFO (U4) will First reading data received in data FIFO (U3) comes out.
In RT message control/filtering module, by the data read from RT data collector module according to 1553 agreements It is parsed.RT message control/filtering module is responded for the channel that BC command word uses, if the BC order received No. RT in word is unrelated with this RT numbers, then without response, i.e., will be filtered in this RT numbers unrelated message.If received BC command word in subaddressing is not in effective range or the command word is invalid, then RT message control/filtering module not into Row response, such as there are the position number mistakes of bus message Manchester's code mistake, information order word or data word, odd even school Error checking mistake etc., error identification is arranged in RT message control/filtering module, replys the response word of error condition set.Meanwhile it will receive To datagram BM module is all sent to by the data record input channel of BM data FIFO.
RT message control/filtering module organizes the order of 1553 bus messages according to the setting in register as requested Word, data word, wherein command word is according to the register definitions of logic IP kernel, and when executing RT transmission generic operation, data word is From data collector module；When executing RT reception generic operation, data word is derived from data buffer.It works as RT When, RT message control/filtering module organizes organization data transmission/reception according to the information order word in 1553 buses, and in regulation The interior generation and transmission for carrying out response word, when transmission/reception data, is handled data by data transmit-receive module.
2, BC module
BC module is mainly made of BC data collector module and BC message control module, BC data collector module and RT The structure of data transmit-receive module is essentially identical, is mainly used for realizing data transmit-receive, wherein receiver has record datagram and reaches Time, detection receives the position number mistake of Manchester's code mistake, information order word or data word etc. in data, odd even Check errors etc., BC message control module is mainly as protocol processes function.
BC data collector module includes the second sending module and the second receiving module, and the data of the second sending module are sent Process is as follows:
1) data (order/state, data) for needing to continuously transmit are sent into the second coomand mode by BC message control module FIFO；
2) the word number (a frame number contains order/state, data) that BC message control module continuously transmits needs is sent into Second data FIFO；
3) the second transmission control interface checks whether the second data FIFO is empty, whether checks the second bus channel status channel Free time reads a data packet from the second data FIFO and needs if channel status is idle simultaneously for the second data FIFO non-empty The word number N continuously transmitted；
4) second control interface the second Manchester encoder of control is sent by the data (life in the second coomand mode FIFO Enable word/status word) and the second data FIFO in N number of number (data word) distribute.
The data receiver process of second receiving module is as follows:
1) second control interface detection reception signal RxD+ and RxD- are received, second control signal receiver is receiving window It is lower by data receiver deposit second receive data FIFO, second receive window controlling module by second control signal receiver according to Synchronous head and the baud rate control received in signal opens and closes；
2) second control interface is received by the second reception of received a piece of news data amount check deposit data amount check FIFO；
3) New Data Flag that BC message control module (U0) is received by second in data amount check FIFO is received second Reading data in data FIFO (U3) comes out.
BC message control module completes the transmission control of message, error detection and retries, the operation such as switching transmission channel.Together When, by the state of message mistake, BM module is sent to by the data record input channel of error state data FIFO.Wherein, wrong Error detection includes the position number error detection of Manchester's code error detection, information order word or data word etc., even-odd check Error detection etc..
BC message control module organizes command word, the number of 1553 bus messages according to the setting in register as requested According to word, wherein command word is the register definitions according to logic IP kernel.
BC module has the ability of A/B binary channels hand-off process, when BC message control module determines communication abnormality, actively Message transmission channel is switched to an other channel.
3, BM module
BM module include BM control module, by RT data record FIFO and RT control FIFO form BM data FIFO, by BC data record FIFO and BC control the error state data FIFO of FIFO composition.BM data FIFO and error state data FIFO It is all made of double-FIFO structure, BM data FIFO is made of RT data record FIFO and RT control FIFO, and RT data record FIFO is used In the datagram for saving the upload of RT module；RT control FIFO is used to save length, markers, the data of the datagram of RT module upload Report the control information such as type.Error state data FIFO is made of BC data record FIFO and BC control FIFO, BC data record FIFO is used to save the datagram of BC module upload；BC control FIFO is used to save the control letter of the datagram of BC module upload Breath.The number of the data record input channel of double-FIFO structure, configures on demand.The data come from RT module are in 1553 buses Datagram, each data record is the datagram in 1553 bus；The data come from BC module are disappeared in 1553 buses The information such as the error condition of breath, each data record are the information such as the error condition of the message transmitted in 1553 buses. The data record input channel of each double-FIFO structure of BM control module poll takes out a record when there is data record Control information and data is wrapped into, and is stored in data buffer zone BM_BUF.Data buffer zone BM_BUF uses double buffering knot Structure, includes BUF_A and BUF_B, and BM control module is responsible for the management of two data buffer areas.Another function of BM control module It is the instruction for receiving HPM, record is taken out from data buffer area, carries out dissection process according to 1553 agreements, upload.BM data Storage control is responsible for taking out the record in BM_BUF, is saved in the outer nonvolatile storage of piece (BM flash).
(2) the 1553 bus network protocol softwares
The 1553 bus network protocol softwares are used in the transport layer software on 1553 bus network protocol logic IP kernel upper layers Initialization, the data transmit-receive control for controlling 1553 bus network protocol logic IP kernels, realize and drive the data of layer and application layer Transmission, the design of the 1553 bus network protocol softwares are primarily referred to as carrying out General design for bus network software platform.It is general Change software to be designed according to modularization, hierarchical design thinking, detailed block diagram for software modules is as shown in Figure 4.
1) control layer: control layer mainly controls the RT module in 1553 bus network protocol logic IP kernels, BC module and BM Switching between module, goes back control mode switch, and mode includes BC mode, RT, BM；
2) bussiness processing layer: the mode that bussiness processing layer is mainly arranged according to control layer carries out corresponding mode treatment, should Main BC, RT, BM the isotype function realized under 1553 agreements of layer；
3) interface adaptation layer: interface adaptation layer is handled primarily directed to the read and write access of different hardware interface, which will not Same hardware interface is packaged into different modules respectively, so that can be full decoupled between different hardware interfaces；
4) hardware adaptation layer: hardware adaptation layer mainly realizes the access and operation to FPGA internal logic IP interface, for Different operation hardware platforms are adapted to.
Fig. 6 is the 1553 bus network hardware module products developed using the present embodiment, and detailed description are as follows:
1) structure of 1553 bus network hardware modules is as shown in Figure 6.Wherein, soft comprising MircoBlaze inside FPGA Core and 1553 protocol logic IP realize the processing of 1553 bus protocol layers.
2) software sharing of 1553 bus network hardware modules is as shown in Figure 7
Wherein, the configuration header file for disparity items being stored under config catalogue adds different configurations for disparity items Header file；Config.h is total configuration header file, in this document, includes configuration header file information；Mbi_main.c is main Control the processing routine of module；Business processing logic module when the files such as mbi_bc.c/mbi_bc.h/mbi_rt.c/mbi_rt.h Program；Dp.c/dp.h is twoport memory interface module processor；Protocol_chip.c is at protocol chip interface module Manage program；Hardware_adapter_layer.c is hardware adaptation module processor；Log.c is log system service program； Common_Circular_Buffer.c is the general module program that circulation Buffer access is carried out to twoport memory.
Shown in Figure 1, the present embodiment as an example, additionally provides a kind of 1553 bus network protocol test rings Border is mainly used for testing 1553 bus network products.
As shown in figure 5,1553 bus network product test hardware platforms should include main three parts: MBI testing cassete, MBI Test equipment and power supply unit.Wherein, MBI testing cassete is mainly used for loading MBI module and master cpu module and test point Deng；MBI test equipment mainly realize and testing cassete in master cpu module carry out Ethernet and serial communication and MBI module into Row 1553 communicates；Power supply unit mainly realizes the power supply power supply to test equipment and testing cassete.
Test environment should have following basic function:
1) have bus B C, RT, BM function, performance test function；
2) has bus pressure test function；
3) has bus failure injection test function；
4) has the adaptation test function of a variety of project MBI modules；
5) has the bus access test function for the buses such as PCI/PCIe/ is customized.
It, can according to the technique and scheme of the present invention and its hair it is understood that for those of ordinary skills Bright design is subject to equivalent substitution or change, and all these changes or replacement all should belong to the guarantor of appended claims of the invention Protect range.

Claims (9)

  1. It include the 1553 bus network protocol softwares and 1553 bus network 1. a kind of 1553 bus network products, are realized by FPGA Protocol logic IP kernel；
    1553 bus network protocol logic IP kernels for being parsed to 1553 bus datas and protocol processes, comprising one with On RT module, more than one BC module and a BM module；RT module uploads the datagram in 1553 buses to BM module, BC module uploads the error condition of 1553 total Thread Messages to BM module, and BM module passes the data that RT module and BC module upload It is defeated by the 1553 bus network protocol softwares；
    The 1553 bus network protocol softwares are for carrying out data transmission and forwarding.
  2. 2. a kind of 1553 bus network product according to claim 1, it is characterised in that the RT module includes RT data Transceiver module and RT message control/filtering module；
    RT data transmit-receive module is used for the parsing and generation of control bus message waveform；
    The channel that RT message control/filtering module is used to use BC command word responds, if the BC command word received In No. RT it is unrelated with this RT numbers, then without response, otherwise, the validity of command word is checked, if the command word In subaddressing is not in effective range or the command word is invalid, then without response；The datagram received is all by BM number BM module is sent to according to the data record input channel of FIFO；
  3. 3. a kind of 1553 bus network product according to claim 2, it is characterised in that the RT data collector module Comprising the first sending module, the first sending module sends control comprising the first coomand mode FIFO, the first data FIFO, first and connects Mouth, the first bus channel state and the first Manchester encoder, data transmission flow are as follows:
    1) data for needing to continuously transmit are sent into the first coomand mode FIFO by RT message control/filtering module；
    2) the word number for needing to continuously transmit is sent into the first data FIFO by RT message control/filtering module；
    3) the first transmission control interface checks whether the first data FIFO is empty, checks whether channel is empty in the first bus channel state Spare time reads a data packet from the first data FIFO and needs to connect if channel status is idle simultaneously for the first data FIFO non-empty The word number N that supervention is sent；
    4) first control interface the first Manchester encoder of control is sent by the data and first in the first coomand mode FIFO N number of word in data FIFO is sent to the data record input channel of BM data FIFO.
  4. 4. a kind of 1553 bus network product according to claim 2, it is characterised in that the RT data collector module Comprising the first receiving module, the first receiving module includes the first reception control interface, first control signal receiver, the first reception Data FIFO, first receive data amount check FIFO, the first reception window controlling module, and data receiver process is as follows:
    1) first control interface detection reception signal RxD+ and RxD- are received, first control signal receiver will in the case where receiving window Data receiver deposit first receives data FIFO, and first receives window controlling module by first control signal receiver according to reception Synchronous head and baud rate control in signal open and close；
    2) first control interface is received by the first reception of received a piece of news data amount check deposit data amount check FIFO；
    3) New Data Flag that RT message control/filtering module is received by first in data amount check FIFO receives data for first Reading data in FIFO comes out.
  5. 5. a kind of 1553 bus network product according to claim 1, it is characterised in that the BC module includes BC data Transceiver module and BC message control module；
    BC data transmit-receive module is used for the parsing and generation of control bus message waveform；
    BC message control module is used to complete the transmission control of message, error detection and retries, and switches transmission channel, meanwhile, it will The state of message mistake is sent to BM module by the data record input channel of error state data FIFO.
  6. 6. a kind of 1553 bus network product according to claim 5, it is characterised in that the BC data transmit-receive module Two sending modules, the second sending module include the second coomand mode FIFO, the second data FIFO, second send control interface, the Two lines bus channel status and the second Manchester encoder, data transmission flow are as follows:
    1) data for needing to continuously transmit are sent into the second coomand mode FIFO by BC message control module；
    2) the word number for needing to continuously transmit is sent into the second data FIFO by BC message control module；
    3) the second transmission control interface checks whether the second data FIFO is empty, checks whether channel is empty in the second bus channel state Spare time reads a data packet from the second data FIFO and needs to connect if channel status is idle simultaneously for the second data FIFO non-empty The word number N that supervention is sent；
    4) second control interface the second Manchester encoder of control is sent by the data and second in the second coomand mode FIFO N number of word in data FIFO is sent to the data record input channel of double-FIFO structure.
  7. 7. a kind of 1553 bus network product according to claim 5, it is characterised in that the BC data transmit-receive module Two receiving modules, the second receiving module include the second reception control interface, second control signal receiver, the second reception data FIFO, second receive data amount check FIFO, the second reception window controlling module, and data receiver process is as follows:
    1) second control interface detection reception signal RxD+ and RxD- are received, second control signal receiver will in the case where receiving window Data receiver deposit second receives data FIFO, and second receives window controlling module by second control signal receiver according to reception Synchronous head and baud rate control in signal open and close；
    2) second control interface is received by the second reception of received a piece of news data amount check deposit data amount check FIFO；
    3) New Data Flag that BC message control module is received by second in data amount check FIFO receives data FIFO for second In reading data come out.
  8. 8. a kind of 1553 bus network product according to claim 1, it is characterised in that BM module include BM control module, By RT data record FIFO and RT control FIFO form BM data FIFO, by BC data record FIFO and BC control FIFO form Error state data FIFO；
    RT data record FIFO is used to save the datagram of RT module upload；
    RT control FIFO is used to save the control information of RT module upload；
    BC data record FIFO is used to save the datagram of BC module upload；
    BC control FIFO is used to save the control information of BC module upload；
    Each data record input channel of BM control module poll BM data FIFO and error state data FIFO, when there is data When record, FIFO or BC data record FIFO and BC control FIFO is controlled from RT data record FIFO and RT and takes out a corresponding number According to being packaged after report and control information, it is stored in data buffer zone, and will count according to the instruction of the 1553 bus network protocol softwares The 1553 bus network protocol softwares are uploaded to according to data record is taken out in buffer area.
  9. 9. a kind of 1553 bus network product according to claim 1, it is characterised in that bus network protocol software module Include:
    Control layer: control RT module, switching and pattern switching between BC module and BM module；The mode includes BC mould Formula, RT mode, BM mode；
    Bussiness processing layer: the mode being arranged according to control layer carries out corresponding mode treatment,
    Interface adaptation layer: the read and write access for different hardware interface is handled, and different hardware interfaces is packaged by this layer respectively Different modules；
    Hardware adaptation layer: hardware adaptation layer realizes the access and operation to 1553 bus network protocol logic IP kernels, for difference Operation hardware platform be adapted to.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112261333A (en) * 2020-10-19 2021-01-22 中国科学院光电技术研究所 Method for transmitting image through optical fiber 1553 bus

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2074073A1 (en) * 1990-02-07 1991-08-08 Craig A. Schauss Interface chip device
US5442754A (en) * 1992-12-04 1995-08-15 Unisys Corporation Receiving control logic system for dual bus network
CN102035658A (en) * 2010-11-26 2011-04-27 北京航空航天大学 High-speed 1553B fiber bus IP core
CN102647320A (en) * 2012-04-09 2012-08-22 中国电子科技集团公司第五十八研究所 Integrated circuit suitable for high-speed 1553 bus protocol control
CN107579894A (en) * 2017-09-22 2018-01-12 成都旋极历通信息技术有限公司 A kind of EBR1553 bus protocol realization devices based on FPGA
CN107943732A (en) * 2017-11-21 2018-04-20 北京宇航系统工程研究所 One kind realizes 1553B bus modules based on production domesticization FPGA device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2074073A1 (en) * 1990-02-07 1991-08-08 Craig A. Schauss Interface chip device
US5442754A (en) * 1992-12-04 1995-08-15 Unisys Corporation Receiving control logic system for dual bus network
CN102035658A (en) * 2010-11-26 2011-04-27 北京航空航天大学 High-speed 1553B fiber bus IP core
CN102647320A (en) * 2012-04-09 2012-08-22 中国电子科技集团公司第五十八研究所 Integrated circuit suitable for high-speed 1553 bus protocol control
CN107579894A (en) * 2017-09-22 2018-01-12 成都旋极历通信息技术有限公司 A kind of EBR1553 bus protocol realization devices based on FPGA
CN107943732A (en) * 2017-11-21 2018-04-20 北京宇航系统工程研究所 One kind realizes 1553B bus modules based on production domesticization FPGA device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
商伟峰等: "基于FPGA的1553B总线远程终端的设计与实现", 《计算机应用》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112261333A (en) * 2020-10-19 2021-01-22 中国科学院光电技术研究所 Method for transmitting image through optical fiber 1553 bus
CN112261333B (en) * 2020-10-19 2022-07-29 中国科学院光电技术研究所 Method for transmitting image through optical fiber 1553 bus

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