CN115866081B - SOC-based industrial Ethernet protocol conversion method - Google Patents
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Abstract
The invention relates to an industrial Ethernet protocol conversion method based on SOC, which belongs to the technical field of communication protocol conversion, designs a novel chip architecture for realizing industrial Ethernet protocol conversion based on SOC architecture, designs data frame coding/decoding IP, realizes coding/decoding of various industrial Ethernet protocol data frames by modifying configuration parameters of the IP, and realizes high-speed data transmission by a bus module; and the designed data frame encoding/decoding module transmits a command to the CPU module for analysis through the host end, and the CPU module transmits configuration information to realize encoding/decoding functions of various industrial Ethernet protocol data frames. The invention ensures the accuracy of data transmission, can realize the encoding and decoding operations of different industrial Ethernet protocol data frames through different configuration information, and improves the use flexibility of the chip; the multi-data frame coding/decoding module can be mounted on the AXI data bus, so that an expansion function is obtained, and the data transmission efficiency is improved.
Description
Technical Field
The invention relates to an industrial Ethernet protocol conversion method based on SOC, belonging to the technical field of communication protocol conversion.
Background
With the development of computer, communication and network technologies, ethernet technology has been widely used in various fields, where the ethernet technology is combined with a field bus, and is compatible with commercial ethernet (i.e. industrial EEE802.3 standard) in technology, and an industrial ethernet bus formed by combining with an industrial data bus has a wide application prospect in terms of manufacturing industry, traffic, building and other automation systems. Industrial ethernet buses offer several advantages, such as: ethernet is the most widely used computer network technology, which is developed in almost all programming languages. The industrial Ethernet bus has high communication rate, strong real-time performance and various types. Meanwhile, the price of the Ethernet network card is much lower than that of the field bus network card, and the overall cost of the system is greatly reduced. However, along with the improvement of the traditional Ethernet in terms of industrial application, the industrial Ethernet technologies of POWERLINK, etherCAT, EPA, NCUC-Bus, etherMAC, SERCOS, etherNetlIP, modBusTCP, profinetSRT, MECHATROLINK and the like are created, the industrial Ethernet protocols are improved on the basis of the original Ethernet protocols, the unique encoding and decoding modes are respectively provided in the aspect of data transmission, and the different protocols have the applicable fields and characteristics. When the data is transmitted to the user end by using a plurality of protocols for cooperative control or different protocols for staggered transmission, the user end needs to continuously perform corresponding encoding and decoding on the data according to the different protocols, and then performs logic operation according to the obtained data, so that the data transmission burden is increased to a certain extent.
Disclosure of Invention
The invention aims to provide an industrial Ethernet protocol conversion method based on SOC, which changes a data transmission mode, utilizes the characteristic of parallel data processing of FPGA, improves the data transmission speed, and finally extracts effective information through CPU configuration by converting all accessed Ethernet protocols and sends the effective information to a user side, thereby being capable of remarkably reducing the workload of a host side, improving the transmission speed and reducing the working complexity.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
an industrial Ethernet protocol conversion method based on SOC is characterized in that a novel chip architecture for realizing industrial Ethernet protocol conversion is designed based on the SOC architecture, IP is encoded/decoded by data frames, encoding/decoding of various industrial Ethernet protocol data frames is realized by modifying configuration parameters of the IP, and high-speed data transmission is realized by a bus module; the method comprises the following steps:
step 1: the host end sends the command information and the control register information to the control register module for storage through the PCIE module;
step 2: the CPU module is used for carrying out polling reading on the control register module, reading out commands and configuration information in the control register module, and analyzing the commands and the configuration information;
step 3: the CPU module sends the analyzed command and configuration information to the DMA module and the data frame encoding/decoding module through the AXI control bus;
step 4: the DMA module and the data frame encoding/decoding module perform function adjustment according to configuration information sent by the control bus;
step 5: when the host computer transmits data to the slave computer, the data transmitted by the host computer is transmitted to the data frame encoding/decoding module by the DMA module through the AXI data bus, the data is packed into data frames according to the protocol specification, and the data frames are transmitted to the slave computer to finish data transmission; when the slave machine transmits data to the host machine, the slave machine transmits the data frames packed according to the protocol to the data frame encoding/decoding module, extracts effective information in the data frames and stores the effective information in the protocol data caching module;
step 6: when the slave sends data to the host, the DMA module reads the data in the protocol data cache module through the AXI data bus according to the configuration information, and adjusts the data bit width and the transmission mode according to the configuration requirement of the host;
step 7: and the DMA module sends the converted data to the PCIE module, and the converted data is sent to the host end through the PCIE module to complete data transmission.
The technical scheme of the invention is further improved as follows: the command information and the control register information in the step 1 comprise read/write command operation description, a slave ID accessed by a Host, an access protocol data cache module address, a selection protocol sequence number to be converted and a clock reset module configuration parameter.
The technical scheme of the invention is further improved as follows: the control register module comprises two parts, wherein one part is an address information register, and the other part is a command information register.
The technical scheme of the invention is further improved as follows: the specific operation of the step 2 is as follows:
step 2-1: the CPU module firstly polls and reads the information in the address information register, and when the CPU judges that the difference value occurs in the data in the address information register of the same address read out twice before and after, the CPU judges that the access address conversion of the client is obtained;
step 2-2: the CPU module adopts R5, when R5 firstly polls and reads the information of the start address and the end address in the address information register, after the difference value between the address data is transformed, the CPU module starts to poll and read the information of the command information register, and analyzes the read information; and the CUP module stores the analyzed command information register information into a configuration information register hung under R5 in the CPU module.
The technical scheme of the invention is further improved as follows: the step 4 specifically comprises the following steps:
step 4-1: the CPU sends configuration information to the DMA module, the DMA module adopts double-channel DMA, and the two channels are respectively used for writing operation and reading operation from the host to the slave; the DMA module is respectively connected with the protocol data cache module and the PCIE module through an AXI data bus, and has the functions of taking out the data in the protocol data cache module and forwarding the data to the PCIE module or reversing the data path; the DMA controller receives configuration information which is issued by a CPU and comprises a source address, a destination address and a transmission quantity, wherein the transmission quantity comprises a total data quantity and a data bit width; the DMA module distinguishes the position of the data to be read and the data forwarding position according to the source address and the destination address, and calculates the burst length required by single AXI transmission through the total data quantity and the data bit width; the DMA controller sends a read-write request to an AXI data bus through configuration information by an AXI interface to complete the configuration of the CPU on the DMA module, and when the operation required by the configuration is completed, namely after receiving a read response or a write response through the AXI interface on the DMA module, the DMA controller feeds back the read response or the write response to the CPU module through a data path to complete the configuration operation;
step 4-2: the CPU sends configuration information to the data frame encoding/decoding module; the data frame coding/decoding module is written for Verilog language and comprises a frame coding module, a frame decoding module and a CRC checking module; the frame decoding module is responsible for adding a preamble, a destination address, a source address, a data length and an Ethernet type to the data; the frame decoding module is responsible for decoding the received frame, identifying a destination address and a source address, identifying a class and extracting effective data transmitted in a protocol; the CRC module comprises two functions, namely adding a CRC code into the data and then sending the data to the frame coding module, and checking the correctness of the data sent by the frame decoding module; the configuration information of the CPU is transmitted into a data frame encoding/decoding module in the form of parameters, and the contents of the parameters comprise: preamble bit width, destination address and source address bit width, packet type bit width, protocol data bit width and check code bit width; after the frame coding/decoding module determines the parameters of each part of the received data frame, the data frame is unfolded according to the bit width; the decoding module expands the received data frame to obtain information including a destination address, a source address and protocol data, and respectively stores the address information and the data in the protocol data buffer module.
The technical scheme of the invention is further improved as follows: the step 5 specifically comprises the following steps:
step 5-1: when the host computer transmits data to the slave computer, the DMA module configured by the CPU module takes out the data to be transmitted from the PCIE module connected with the host computer, adjusts the data bit width and the transmission mode in the DMA module according to the configuration information, transmits the data to the AXI data bus, and finds out a CRC check module in the corresponding slave computer data frame encoding/decoding module according to the address transmitted by the DMA module; after the data frame coding module receives the data, adding a preamble, a destination address, a source address, a data length and an Ethernet type to the data; after the data frame is packed, the data frame is sent to the slave machine to finish data transmission;
step 5-2: when the slave sends data to the host, the data frame is sent to a data frame decoding module by the slave, and the data frame is split into a preamble, a destination address, a source address, a data length, an Ethernet type, valid data and a CRC check code in the module; after the data frame is split, the data frame is selected through a selector in the data frame code receiving module, the destination address and the source address are stored in an address information register of the protocol data buffer module, and the effective data and the CRC check code are stored in a data register of the protocol data buffer module after being compared correctly through the CRC check module.
The technical scheme of the invention is further improved as follows: in the step 5, the data frame encoding/decoding module and the protocol data buffer module can mount a plurality of data frames on the AXI data bus according to design requirements, and in the step 7, the DMA module can mount a plurality of data frames on the AXI data bus according to design requirements.
By adopting the technical scheme, the invention has the following technical effects:
the invention relates to a novel chip architecture for realizing an industrial Ethernet protocol conversion method based on SOC architecture design. Two AXI buses in the chip respectively realize the functions of data transmission and control information transmission, and the accuracy of data transmission is ensured through a handshake mechanism of the AXI buses; it is proposed to distinguish between different industrial ethernet protocol types based on the ID information that the AXI bus can carry.
The data frame coding/decoding module designed by the invention has configurability, and can realize coding and decoding operations on data frames of different industrial Ethernet protocols through different configuration information, thereby improving the use flexibility of the chip.
The invention can mount the multi-data frame coding/decoding module on the AXI data bus, thereby obtaining the expansion function, realizing the data interaction among the slave devices supporting different industrial Ethernet protocols through the configuration of the host end, and improving the data transmission efficiency.
Drawings
FIG. 1 is a diagram of the overall architecture of the present invention;
FIG. 2 is a flow chart of a method for sending data from a host to a slave according to the present invention;
FIG. 3 is a control path flow diagram of the present invention;
FIG. 4 is a data path flow diagram of the present invention;
fig. 5 is a block diagram of a data frame codec module according to the present invention.
Detailed Description
The invention relates to an industrial Ethernet protocol conversion method based on SOC chip architecture design, and the whole architecture design is referred to in FIG. 1. The method can effectively improve the data interaction rate between the host and the slaves of a plurality of different protocol transmission modes, and can carry out configuration according to the ID when different protocols are used in the invention, and the handshake mechanism of the AXI bus ensures the safety and reliability of data transmission. The invention will now be described in further detail with reference to the drawings and to specific examples, which are only illustrative of embodiments of the invention and are not to be construed as limiting the embodiments of the invention.
Referring to fig. 2, the function implementation of the present invention:
step 1: the host side sends the data to the control register module through the AXI control bus by the PCIE module. The command information and the control register information comprise read/write command operation description, a slave ID accessed by a Host, an access protocol data cache module address, a selected protocol sequence number to be converted and a clock reset module configuration parameter.
Step 2: the CPU module polls the contents of the read control register module.
Step 2-1: the control register is divided into two parts, one part is an address information register and the other part is a command information register. The CPU firstly polls and reads the information in the address information register, and when the CPU judges that the difference value occurs in the data in the address information register of the same address read out twice before and after, the CPU judges that the access address conversion of the client is obtained.
Step 2-2: the CPU module adopts a fifth generation Ruilong AMDRyzen processor (R5). When R5 first polls the read address information register to express the start address and the end address register information, after the difference value between the address data is changed, the read command information register information is started to be polled, and the read information is analyzed, wherein the command information register information comprises: the read/write command operation description, the slave ID accessed by the Host, the address of the access protocol data cache module and the protocol sequence number to be converted are selected. And the CUP module stores the analyzed command information register information into a configuration information register hung under R5 in the CPU module.
Step 3: and the CPU module respectively sends the analyzed command and configuration information to the DMA module and the data frame encoding/decoding module through the AXI control bus. The CPU module firstly transmits parameters required by the configuration of the DMA module, the data transmitted by the AXI protocol is hung on an address distributed on an AXI control bus through the DMA module to find the DMA module, and the data is transmitted to the DMA module. After the initialization configuration of the DMA module is completed, the CPU module issues parameters required by the data frame encoding/decoding module through an AXI control bus in a similar manner to the method for configuring the DAM module. Referring to fig. 3, the control path implementation of the present invention.
Step 4: the DMA module and the data frame encoding/decoding module perform function adjustment according to configuration information sent by the control bus.
Step 4-1: the CPU sends configuration information to the DMA module. In the invention, the DMA module adopts double-channel DMA, and the two channels are respectively used for writing operation and reading operation from the host to the slave. The DMA module is respectively connected with the protocol data cache module and the PCIE module through the AXI data bus, and has the functions of taking out the data in the protocol data cache module and forwarding the data to the PCIE module or reversing the data path. The DMA controller receives configuration information which is issued by the CPU and comprises a source address, a destination address and a transmission quantity, wherein the transmission quantity comprises a total data quantity and a data bit width. The DMA distinguishes the position of the data to be read and the data forwarding position according to the source address and the destination address, and calculates the burst length required by single AXI transmission through the total data quantity and the data bit width. The DMA controller sends a read-write request to an AXI data bus through configuration information by an AXI interface to complete the configuration of the CPU to the DMA module, and after the operation required by the configuration is completed, namely after receiving a read response or a write response through the AXI interface on the DMA module, the DMA controller feeds back the read response or the write response to the CPU module through a data path to complete the configuration operation.
Step 4-2: the CPU sends configuration information to the data frame encoding/decoding module. The data frame coding/decoding module is written in Verilog language and comprises a frame coding module, a frame decoding module and a CRC checking module. Wherein the frame decoding module is responsible for adding a preamble, a destination address, a source address, a data length, and an ethernet type to the data. The frame decoding module is responsible for decoding the received frame, identifying destination address and source address, class identification and extracting valid data transmitted in the protocol. The CRC check module has two functions, namely, adding a CRC check code to the data and then sending the data to the frame coding module, and checking the correctness of the data sent by the frame decoding module. The configuration information of the CPU is transmitted into a data frame encoding/decoding module in a parameter form, and the parameter content comprises: preamble bit width, destination address and source address bit width, packet type bit width, protocol data bit width, and check code bit width. And after the frame encoding/decoding module determines the parameters of each part of the received data frame, expanding the data frame according to the bit width. The decoding module expands the received data frame and acquires main information including a destination address, a source address and protocol data. And respectively storing the address information and the data in a protocol data cache module.
Step 5: the slave machine sends the data frames packaged according to the protocol to the data frame encoding/decoding module, extracts effective information in the data frames and stores the effective information in the protocol data caching module. Or the host transmits the data to be transmitted to the data frame encoding/decoding module, encodes the data, packages the data into data frames conforming to the protocol specification, and transmits the data frames to the slave. Frame encoding/decoding module structure referring to fig. 5.
Step 5-1: when the host computer transmits data to the slave computer, the DMA module configured by the CPU module takes out the data to be transmitted from the PCIE module connected with the host computer, adjusts the data bit width and the transmission mode in the DMA module according to the configuration information, transmits the data to the AXI data bus, and finds out the CRC check module in the corresponding slave computer data frame encoding/decoding module according to the address transmitted by the DMA module. After the data frame coding module receives the data, a preamble, a destination address, a source address, a data length and an Ethernet type are added to the data. And after the data frame is packed, the data frame is sent to the slave machine to finish data transmission. Referring to fig. 4, the data path implementation of the present invention.
Step 5-2: when the slave sends data to the host, the data frame is sent by the slave to a data frame decoding module, where the data frame is split into a preamble, a destination address, a source address, a data length, an ethernet type, valid data, and a CRC check code. After the data frame is split, the data frame is selected through a selector in the data frame code receiving module, the destination address and the source address are stored in an address information register of the protocol data buffer module, and the effective data and the CRC check code are stored in a data register of the protocol data buffer module after being compared correctly through the CRC check module.
Step 6: the DMA module reads the protocol data cache module information. When the protocol data buffer module is not empty, the protocol data buffer module can send the protocol data buffer module to the CPU module for marking information, and the CPU module configures the DMA module to sequentially read the address information register and the data in the data register in the protocol data buffer module through the AXI data bus, and the data are combined into a new data format through the bit width conversion of the DMA module.
Step 7: and the DMA module sends the converted data to the PCIE module through the AXI data bus, and the PCIE module sends the data to the host side to complete data transmission.
The invention provides a protocol conversion method capable of receiving data transmitted by different industrial Ethernet protocols and converting the data into the same specific data format based on an SOC (system on chip) architecture. After real-time analysis and integration of data transmitted by various industrial Ethernet protocols, the received data frames are directly decoded according to the user demands to extract effective information in the data frames. Therefore, the user side does not need to decode the data frame again to acquire the information contained in the data frame, and can acquire the data transmitted by various protocols, so that the workload of the host side is greatly reduced, and the functions of improving the transmission rate and reducing the working complexity are achieved.
Claims (5)
1. An industrial Ethernet protocol conversion method based on SOC is characterized in that: based on the SOC architecture, a novel chip architecture for realizing industrial Ethernet protocol conversion is designed, an IP is encoded/decoded by a data frame, the encoding and decoding of various industrial Ethernet protocol data frames are realized by modifying the configuration parameters of the IP, and the high-speed data transmission is realized by a bus module; the method comprises the following steps:
step 1: the host end sends the command information and the control register information to the control register module for storage through the PCIE module;
step 2: the CPU module is used for carrying out polling reading on the control register module, reading out commands and configuration information in the control register module, and analyzing the commands and the configuration information;
step 3: the CPU module sends the analyzed command and configuration information to the DMA module and the data frame encoding/decoding module through the AXI control bus;
step 4: the DMA module and the data frame encoding/decoding module perform function adjustment according to configuration information sent by the control bus; the step 4 specifically comprises the following steps:
step 4-1: the CPU sends configuration information to the DMA module, the DMA module adopts double-channel DMA, and the two channels are respectively used for writing operation and reading operation from the host to the slave; the DMA module is respectively connected with the protocol data cache module and the PCIE module through an AXI data bus, and has the functions of taking out the data in the protocol data cache module and forwarding the data to the PCIE module or reversing the data path; the DMA controller receives configuration information which is issued by a CPU and comprises a source address, a destination address and a transmission quantity, wherein the transmission quantity comprises a total data quantity and a data bit width; the DMA module distinguishes the position of the data to be read and the data forwarding position according to the source address and the destination address, and calculates the burst length required by single AXI transmission through the total data quantity and the data bit width; the DMA controller sends a read-write request to an AXI data bus through configuration information by an AXI interface to complete the configuration of the CPU on the DMA module, and when the operation required by the configuration is completed, namely after receiving a read response or a write response through the AXI interface on the DMA module, the DMA controller feeds back the read response or the write response to the CPU module through a data path to complete the configuration operation;
step 4-2: the CPU sends configuration information to the data frame encoding/decoding module; the data frame coding/decoding module is written for Verilog language and comprises a frame coding module, a frame decoding module and a CRC checking module; the frame coding module is responsible for adding a preamble, a destination address, a source address, a data length and an Ethernet type to the data; the frame decoding module is responsible for decoding the received frame, identifying a destination address and a source address, identifying a class and extracting effective data transmitted in a protocol; the CRC module comprises two functions, namely adding a CRC code into the data and then sending the data to the frame coding module, and checking the correctness of the data sent by the frame decoding module; the configuration information of the CPU is transmitted into a data frame encoding/decoding module in the form of parameters, and the contents of the parameters comprise: preamble bit width, destination address and source address bit width, packet type bit width, protocol data bit width and check code bit width; after the frame coding/decoding module determines the parameters of each part of the received data frame, the data frame is unfolded according to the bit width; the decoding module expands the received data frame to obtain information comprising a destination address, a source address and protocol data, and respectively stores the address information and the data in the protocol data cache module;
step 5: when the host computer transmits data to the slave computer, the data transmitted by the host computer is transmitted to the data frame encoding/decoding module by the DMA module through the AXI data bus, the data is packed into data frames according to the protocol specification, and the data frames are transmitted to the slave computer to finish data transmission; when the slave machine transmits data to the host machine, the slave machine transmits the data frames packed according to the protocol to the data frame encoding/decoding module, extracts effective information in the data frames and stores the effective information in the protocol data caching module; the step 5 specifically comprises the following steps:
step 5-1: when the host computer transmits data to the slave computer, the DMA module configured by the CPU module takes out the data to be transmitted from the PCIE module connected with the host computer, adjusts the data bit width and the transmission mode in the DMA module according to the configuration information, transmits the data to the AXI data bus, and finds out a CRC check module in the corresponding slave computer data frame encoding/decoding module according to the address transmitted by the DMA module; after the data frame coding module receives the data, adding a preamble, a destination address, a source address, a data length and an Ethernet type to the data; after the data frame is packed, the data frame is sent to the slave machine to finish data transmission;
step 5-2: when the slave sends data to the host, the data frame is sent to a data frame decoding module by the slave, and the data frame is split into a preamble, a destination address, a source address, a data length, an Ethernet type, valid data and a CRC check code in the module; after the data frame is split, selecting the data frame through a selector in a data frame code receiving module, storing a destination address and a source address in an address information register of a protocol data cache module, and storing effective data and a CRC check code into a data register of the protocol data cache module after being compared correctly through the CRC check module;
step 6: when the slave sends data to the host, the DMA module reads the data in the protocol data cache module through the AXI data bus according to the configuration information, and adjusts the data bit width and the transmission mode according to the configuration requirement of the host;
step 7: and the DMA module sends the converted data to the PCIE module, and the converted data is sent to the host end through the PCIE module to complete data transmission.
2. The SOC-based industrial ethernet protocol conversion method of claim 1, wherein: the command information and the control register information in the step 1 comprise read/write command operation description, a slave ID accessed by a Host, an access protocol data cache module address, a selection protocol sequence number to be converted and a clock reset module configuration parameter.
3. The SOC-based industrial ethernet protocol conversion method of claim 1, wherein: the control register module comprises two parts, wherein one part is an address information register, and the other part is a command information register.
4. A method for converting an industrial ethernet protocol based on SOC according to claim 3, wherein: the specific operation of the step 2 is as follows:
step 2-1: the CPU module firstly polls and reads the information in the address information register, and when the CPU judges that the difference value occurs in the data in the address information register of the same address read out twice before and after, the CPU judges that the access address conversion of the client is obtained;
step 2-2: the CPU module adopts a fifth generation Ruilong AMDRyzen processor R5, when R5 firstly polls and reads the information of the start address and the end address in the address information register, after the difference value between the address data is transformed, the CPU module starts to poll and read the information of the command information register, and analyzes the read information; and the CPU module stores the analyzed command information register information into a configuration information register hung under R5 in the CPU module.
5. The SOC-based industrial ethernet protocol conversion method of claim 1, wherein: in the step 5, the data frame encoding/decoding module and the protocol data buffer module can mount a plurality of data frames on the AXI data bus according to design requirements, and in the step 7, the DMA module can mount a plurality of data frames on the AXI data bus according to design requirements.
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