CN115866081A - Industrial Ethernet protocol conversion method based on SOC - Google Patents
Industrial Ethernet protocol conversion method based on SOC Download PDFInfo
- Publication number
- CN115866081A CN115866081A CN202211396522.9A CN202211396522A CN115866081A CN 115866081 A CN115866081 A CN 115866081A CN 202211396522 A CN202211396522 A CN 202211396522A CN 115866081 A CN115866081 A CN 115866081A
- Authority
- CN
- China
- Prior art keywords
- data
- module
- information
- address
- decoding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 22
- 230000005540 biological transmission Effects 0.000 claims abstract description 36
- 230000006870 function Effects 0.000 claims abstract description 14
- 230000004044 response Effects 0.000 claims description 9
- 125000004122 cyclic group Chemical group 0.000 claims description 3
- 239000000284 extract Substances 0.000 claims description 3
- 238000004891 communication Methods 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
Images
Abstract
The invention relates to an industrial Ethernet protocol conversion method based on SOC, belonging to the technical field of communication protocol conversion, and based on an SOC architecture, a novel chip architecture for realizing industrial Ethernet protocol conversion is designed, a data frame encoding/decoding IP is designed, the encoding/decoding of various industrial Ethernet protocol data frames is realized by modifying configuration parameters of the IP, and the high-speed transmission of data is realized through a bus module; the designed data frame coding/decoding module issues commands to the CPU module for analysis through the host end, and the CPU module issues configuration information to realize the coding/decoding functions of various industrial Ethernet protocol data frames. The invention ensures the accuracy of data transmission, can realize the coding and decoding operation of different industrial Ethernet protocol data frames through different configuration information, and improves the use flexibility of a chip; the multiple data frame encoding/decoding module can be mounted on the AXI data bus, so that the expansion function is obtained, and the data transmission efficiency is improved.
Description
Technical Field
The invention relates to an industrial Ethernet protocol conversion method based on SOC, belonging to the technical field of communication protocol conversion.
Background
With the development of computer, communication and network technologies, ethernet technology has been widely applied in various fields, in which ethernet technology is combined with field bus, and technically adopted to be compatible with commercial ethernet (i.e. industrial EEE802.3 standard), and an industrial ethernet bus formed by combining with an industrial data bus has a wide application prospect in the aspect of automation systems in manufacturing industry, traffic, building and the like. Industrial ethernet buses have several advantages, such as: ethernet is the most widely used computer networking technology, developed in support of almost all programming languages. The industrial Ethernet bus has high communication speed, strong real-time performance and various types. Meanwhile, the price of the Ethernet network card is much lower than that of a field bus network card, and the overall cost of the system is greatly reduced. However, as people improve the traditional ethernet and industrial applications, industrial ethernet technologies such as POWERLINK, etherCAT, EPA, NCUC-Bus, etherMAC, SERCOS, ethernetlp, modBusTCP, profinetSRT, MECHATROLINK and the like are produced, and all the industrial ethernet protocols are improved on the basis of the original ethernet protocol, and have respective unique encoding and decoding modes in the aspect of data transmission, and different protocols have respective applicable fields and characteristics. Therefore, when multiple protocols are used for cooperative control or different protocols transmit data in a staggered manner to the user side, the user side needs to continuously perform corresponding encoding and decoding on the data according to the different protocols, and then performs logic operation according to the obtained data, thereby increasing the data transmission burden to a certain extent.
Disclosure of Invention
The invention aims to provide an industrial Ethernet protocol conversion method based on SOC, which changes a data transmission mode, utilizes the characteristic that FPGA processes data in parallel, improves the data transmission speed, and finally converts all accessed Ethernet protocols through CPU configuration to extract effective information and sends the effective information to a user side, thereby obviously reducing the workload of a host side, improving the transmission rate and reducing the work complexity.
In order to achieve the purpose, the invention adopts the technical scheme that:
an industrial Ethernet protocol conversion method based on SOC is based on SOC architecture, a novel chip architecture for realizing industrial Ethernet protocol conversion is designed, a data frame encoding/decoding IP is designed, a plurality of industrial Ethernet protocol data frame encoding/decoding are realized by modifying configuration parameters of the IP, and high-speed data transmission is realized through a bus module; the method comprises the following steps:
step 1: the host side sends the command information and the control register information to the control register module through the PCIE module for storage;
and 2, step: the CPU module is used for polling and reading the control register module, reading out commands and configuration information in the control register module and analyzing the commands and the configuration information;
and step 3: the CPU module sends the analyzed command and configuration information to the DMA module and the data frame coding/decoding module through an AXI control bus;
and 4, step 4: the DMA module and the data frame coding/decoding module carry out function adjustment according to the configuration information sent by the control bus;
and 5: when the host sends data to the slave, the data sent by the host is sent to a data frame coding/decoding module by a DMA module through an AXI data bus, and the data is packed into a data frame according to a protocol specification and sent to the slave to complete data transmission; when the slave machine sends data to the host machine, the slave machine sends the data frame packed according to the protocol to the data frame coding/decoding module, extracts effective information in the data frame and stores the effective information in the protocol data caching module;
step 6: when the slave sends data to the host, the DMA module reads the data in the protocol data cache module through the AXI data bus according to the configuration information, and adjusts the data bit width and the transmission mode according to the configuration requirement of the host;
and 7: the DMA module sends the converted data to the PCIE module, and the converted data is sent to the host end through the PCIE module to complete data transmission.
The technical scheme of the invention is further improved as follows: the command information and the control register information in the step 1 comprise read/write command operation description, ID of a slave machine accessed by a Host end, address of an access protocol data cache module, serial number of a selection protocol needing to be converted and configuration parameters of a clock reset module.
The technical scheme of the invention is further improved as follows: the control register module comprises two parts, wherein one part is an address information register, and the other part is a command information register.
The technical scheme of the invention is further improved as follows: the step 2 specifically comprises the following operations:
step 2-1: the CPU module firstly polls and reads the information in the address information register, and judges that the access address of the client is changed when the CPU judges that the data in the address information register of the same address read twice before and after has a difference value;
step 2-2: the CPU module adopts R5, when R5 firstly polls and reads the register information of the address information indicating the initial address and the ending address in the register, after the difference value between the address data is transformed, starts to poll and read the register information of the command information, and analyzes the read information; and the CUP module stores the analyzed command information register information into a configuration information register hung under R5 in the CPU module.
The technical scheme of the invention is further improved as follows: the step 4 specifically comprises the following steps:
step 4-1: the CPU sends configuration information to a DMA module, the DMA module adopts dual-channel DMA, and the two channels are respectively used for write operation and read operation from a host to a slave; the DMA module is respectively connected with the protocol data cache module and the PCIE module through an AXI data bus and has the functions of taking out and forwarding data in the protocol data cache module to the PCIE module or reversing the data path; the DMA controller receives configuration information sent by a CPU, wherein the configuration information comprises a source address, a destination address and a transmission quantity, and the transmission quantity comprises a data total quantity and a data bit width; the DMA module distinguishes the position of data to be read and a data forwarding position according to a source address and a destination address, and calculates the burst length required by single AXI transmission according to the total data amount and the data bit width; the DMA controller sends a read-write request to an AXI data bus through an AXI interface through the configuration information to complete the configuration of the DMA module by the CPU, and when the operation required by the current configuration is completed, namely after a read response or a write response is received through the AXI interface on the DMA module, the read-write response is fed back to the CPU module through a data path to complete the current configuration operation;
step 4-2: CPU sends configuration information to data frame coding/decoding module; the data frame coding/decoding module is written by Verilog language and comprises a frame coding module, a frame decoding module and a CRC (cyclic redundancy check) module; the frame decoding module is responsible for adding a lead code, a destination address, a source address, a data length and an Ethernet type to data; the frame decoding module is responsible for decoding the received frame, identifying a destination address and a source address, identifying a class and extracting effective data transmitted in a protocol; the CRC check module has two functions, namely, adding a CRC check code to the data and then sending the data to the frame coding module, and checking the correctness of the data sent by the frame decoding module; the configuration information of the CPU is transmitted into the data frame coding/decoding module in a parameter form, and the parameter content comprises: lead code bit width, destination address and source address bit width, data packet type bit width, protocol data bit width and check code bit width; after the frame coding/decoding module determines parameters of each part of the received data frame, the data frame is expanded according to the bit width; the decoding module expands the received data frame to obtain information including a destination address, a source address and protocol data, and stores the address information and the data in the protocol data caching module respectively.
The technical scheme of the invention is further improved as follows: the step 5 specifically comprises the following steps:
step 5-1: when the host sends data to the slave, the DMA module configured by the CPU module takes the data to be sent out from the PCIE module connected with the host, adjusts the data bit width and the sending mode according to the configuration information in the DMA module, sends the data to the AXI data bus, and finds the CRC check module in the slave data frame coding/decoding module corresponding to the DMA module according to the address sent by the DMA module; after receiving the data, the data frame coding module adds a lead code, a destination address, a source address, a data length and an Ethernet type to the data; after the data frame is packaged, the data frame is sent to the slave machine to complete data transmission;
step 5-2: when the slave machine sends data to the host machine, the data frame is sent to the data frame decoding module by the slave machine, and the data frame is divided into a lead code, a destination address, a source address, a data length, an Ethernet type, effective data and a CRC check code in the module; after the data frame is split, the data frame is selected through a selector in the data frame code receiving module, the destination address and the source address are stored in an address information register of the protocol data caching module, and the valid data and the CRC check code are compared correctly through the CRC check module and then are stored in a data register of the protocol data caching module.
The technical scheme of the invention is further improved as follows: in step 5, a plurality of data frame encoding/decoding modules and protocol data buffer modules can be mounted on the AXI data bus according to design requirements, and in step 7, a plurality of DMA modules can be mounted on the AXI data bus according to design requirements.
Due to the adoption of the technical scheme, the invention has the following technical effects:
the invention relates to a novel chip architecture for realizing an industrial Ethernet protocol conversion method based on SOC architecture design. Two AXI buses in the chip respectively realize data transmission and control information transmission functions, and the data transmission accuracy is ensured through a handshaking mechanism of the AXI buses; it is proposed to distinguish different industrial ethernet protocol types according to the ID information that an AXI bus can carry.
The data frame coding/decoding module designed by the invention has configurability, can realize coding and decoding operations on different industrial Ethernet protocol data frames through different configuration information, and improves the use flexibility of a chip.
The invention can mount a multi-data frame coding/decoding module on the AXI data bus, thereby obtaining an expansion function, realizing data interaction among slave devices supporting different industrial Ethernet protocols through host configuration, and improving the data transmission efficiency.
Drawings
FIG. 1 is an overall architecture diagram of the present invention;
FIG. 2 is a flow chart of the present invention for a master to send data to a slave;
FIG. 3 is a control path flow diagram of the present invention;
FIG. 4 is a data path flow diagram of the present invention;
fig. 5 is a block diagram of a data frame encoding/decoding module according to the present invention.
Detailed Description
The invention relates to an industrial Ethernet protocol conversion method based on SOC chip architecture design, and the overall architecture design refers to FIG. 1. The method can effectively improve the data interaction rate of the host and the slave in various different protocol transmission modes, and the ID is configured according to the use of different protocols in the method, and the handshaking mechanism of the AXI bus ensures the safety and reliability of data transmission. The present invention will be described in further detail with reference to the drawings and specific examples, which are provided for the purpose of illustrating embodiments of the present invention and are not to be construed as limiting the embodiments of the present invention.
Referring to fig. 2, the function of the present invention is implemented:
step 1: the host side sends the control register module through the AXI control bus through the PCIE module. The command information and the control register information comprise read/write command operation description, ID of a slave machine accessed by a Host end, address of an access protocol data cache module, serial number of a selection protocol needing to be converted and configuration parameters of a clock reset module.
Step 2: and the CPU module polls and reads the contents of the control register module.
Step 2-1: the control register is divided into two parts, one part is an address information register, and the other part is a command information register. The CPU firstly polls and reads the information in the address information register, and judges that the access address of the client is changed when the CPU judges that the data in the address information register of the same address read twice before and after has a difference value.
Step 2-2: the CPU module employs a fifth generation luneron AMDRyzen processor (R5). When R5 firstly polls and reads the register information of the address indicating the initial address and the end address in the register information, after the difference value between the address data is transformed, the information of the command information register starts to poll and read, and the read information is analyzed, wherein the information of the command information register comprises: the method comprises the following steps of reading/writing command operation description, ID of a slave machine accessed by a Host end, address of an access protocol data cache module and selection of a protocol sequence number needing to be converted. And the CUP module stores the analyzed command information register information into a configuration information register hung under R5 in the CPU module.
And step 3: the CPU module sends the analyzed command and configuration information to the DMA module and the data frame coding/decoding module through an AXI control bus respectively. The CPU module firstly sends the parameters needed by the DMA module configuration, the DMA module is found by the data sent by the AXI protocol through the address distributed on the AXI control bus hung by the DMA module, and the data is sent to the DMA module. After the DMA module is initialized and configured, the CPU module issues the parameters required by the data frame coding/decoding module through the AXI control bus, and the method is similar to the method for configuring the DAM module. Referring to fig. 3, the control path implementation of the present invention.
And 4, step 4: and the DMA module and the data frame coding/decoding module carry out function adjustment according to the configuration information sent by the control bus.
Step 4-1: the CPU sends the configuration information to the DMA module. The DMA module adopts dual-channel DMA, and the two channels are respectively used for write operation and read operation from a host computer to a slave computer. The DMA module is respectively connected with the protocol data cache module and the PCIE module through an AXI data bus and has the function of taking out data in the protocol data cache module and forwarding the data to the PCIE module or reversing the data path. The DMA controller receives configuration information sent by the CPU, wherein the configuration information comprises a source address, a destination address and a transmission quantity, and the transmission quantity comprises a data total quantity and a data bit width. The DMA distinguishes the position of the data to be read and the data forwarding position according to the source address and the destination address, and calculates the burst length required by single AXI transmission according to the total data amount and the data bit width. The DMA controller sends a read-write request to an AXI data bus through an AXI interface through the configuration information to complete the configuration of the DMA module by the CPU, and when the operation required by the current configuration is completed, namely after a read response or a write response is received through the AXI interface on the DMA module, the read-write response is fed back to the CPU module through a data path to complete the current configuration operation.
Step 4-2: the CPU sends the configuration information to the data frame encoding/decoding module. The data frame coding/decoding module is written by Verilog language and comprises a frame coding module, a frame decoding module and a CRC (cyclic redundancy check) module. The frame decoding module is responsible for adding a lead code, a destination address, a source address, a data length and an Ethernet type to data. The frame decoding module is responsible for decoding the received frame, identifying the destination address and the source address, identifying the class and extracting the effective data transmitted in the protocol. The CRC check module has two functions, namely, adding a CRC check code to data and then sending the data to the frame coding module, and checking the correctness of the data sent by the frame decoding module. The configuration information of the CPU is transmitted into the data frame coding/decoding module in a parameter form, and the parameter content comprises: lead code bit width, destination address and source address bit width, data packet type bit width, protocol data bit width and check code bit width. And after the frame coding/decoding module determines parameters of each part of the received data frame, expanding the data frame according to the bit width. The decoding module expands the received data frame and acquires the main information of the data frame, wherein the main information comprises a destination address, a source address and protocol data. And respectively storing the address information and the data in the protocol data caching module.
And 5: the slave machine sends the data frame packed according to the protocol to the data frame coding/decoding module, extracts effective information in the data frame and stores the effective information in the protocol data caching module. Or the host transmits the data to be sent to the data frame coding/decoding module, codes the data, packages the data into a data frame meeting the protocol specification, and sends the data frame to the slave. The frame coding/decoding module structure refers to fig. 5.
Step 5-1: when the host sends data to the slave, the DMA module configured by the CPU module takes out the data to be sent from the PCIE module connected with the host, adjusts the data bit width and the sending mode according to the configuration information in the DMA module, sends the data to the AXI data bus, and finds the CRC check module in the slave data frame coding/decoding module according to the address sent by the DMA module. And after receiving the data, the data frame coding module adds a lead code, a destination address, a source address, a data length and an Ethernet type to the data. And sending the data frame to the slave after the data frame is packaged, and finishing data transmission. Referring to fig. 4, the data path implementation of the present invention.
Step 5-2: when the slave machine sends data to the host machine, the data frame is sent to the data frame decoding module by the slave machine, and the data frame is divided into a lead code, a destination address, a source address, a data length, an Ethernet type, effective data and a CRC check code in the module. After the data frame is split, the data frame is selected through a selector in the data frame code receiving module, the destination address and the source address are stored in an address information register of the protocol data caching module, and the valid data and the CRC check code are compared correctly through the CRC check module and then are stored in a data register of the protocol data caching module.
Step 6: and the DMA module reads the information of the protocol data caching module. When the protocol data cache module is not empty, the flag information is sent to the CPU module, and at the moment, the CPU module configures the DMA module to sequentially read data in an address information register and a data register in the protocol data cache module through an AXI data bus, and the data are combined into a new data format through bit width conversion of the DMA module.
And 7: the DMA module sends the converted data to the PCIE module through an AXI data bus, and the PCIE module sends the data to the host end to complete data transmission.
The invention provides a protocol conversion method which is based on an SOC chip architecture and can receive data transmitted by different industrial Ethernet protocols and convert the data into the same specific data format. After data transmitted by various industrial Ethernet protocols are analyzed and integrated in real time, according to user requirements, received data frames are directly decoded to extract effective information in the received data frames. Therefore, the user side does not need to decode the data frame again to acquire the information contained in the data frame, and can acquire the data transmitted by various protocols, so that the workload of the host side is greatly reduced, and the effects of improving the transmission rate and reducing the working complexity are achieved.
Claims (7)
1. An industrial Ethernet protocol conversion method based on SOC is characterized in that: designing a novel chip architecture for realizing industrial Ethernet protocol conversion on the basis of an SOC architecture, designing a data frame encoding/decoding IP, realizing encoding and decoding of various industrial Ethernet protocol data frames by modifying configuration parameters of the IP, and realizing high-speed data transmission through a bus module; the method comprises the following steps:
step 1: the host side sends the command information and the control register information to the control register module through the PCIE module for storage;
step 2: the CPU module is used for polling and reading the control register module, reading out commands and configuration information in the control register module and analyzing the commands and the configuration information;
and step 3: the CPU module sends the analyzed command and configuration information to the DMA module and the data frame coding/decoding module through an AXI control bus;
and 4, step 4: the DMA module and the data frame coding/decoding module carry out function adjustment according to the configuration information sent by the control bus;
and 5: when the host sends data to the slave, the data sent by the host is sent to a data frame coding/decoding module by a DMA module through an AXI data bus, and the data is packed into a data frame according to a protocol specification and sent to the slave to complete data transmission; when the slave machine sends data to the host machine, the slave machine sends the data frame packed according to the protocol to the data frame coding/decoding module, extracts effective information in the data frame and stores the effective information in the protocol data caching module;
step 6: when the slave sends data to the host, the DMA module reads the data in the protocol data cache module through the AXI data bus according to the configuration information, and adjusts the data bit width and the transmission mode according to the configuration requirement of the host;
and 7: the DMA module sends the converted data to the PCIE module, and the converted data is sent to the host end through the PCIE module to complete data transmission.
2. The industrial ethernet protocol conversion method based on SOC according to claim 1, wherein: the command information and the control register information in the step 1 comprise read/write command operation description, ID of a slave machine accessed by a Host end, address of an access protocol data cache module, serial number of a selection protocol needing to be converted and configuration parameters of a clock reset module.
3. The industrial Ethernet protocol conversion method based on SOC of claim 1, wherein: the control register module comprises two parts, wherein one part is an address information register, and the other part is a command information register.
4. The SOC-based industrial Ethernet protocol conversion method of claim 3, wherein: the step 2 specifically comprises the following operations:
step 2-1: the CPU module firstly polls and reads the information in the address information register, and judges that the access address of the client is changed when the CPU judges that the data in the address information register of the same address read twice before and after has a difference value;
step 2-2: the CPU module adopts R5, when R5 firstly polls and reads the register information of the address information indicating the initial address and the ending address in the register, after the difference value between the address data is transformed, starts to poll and read the register information of the command information, and analyzes the read information; and the CUP module stores the analyzed command information register information into a configuration information register hung under R5 in the CPU module.
5. The industrial ethernet protocol conversion method based on SOC according to claim 1, wherein: the step 4 specifically comprises the following steps:
step 4-1: the CPU sends configuration information to a DMA module, the DMA module adopts dual-channel DMA, and the two channels are respectively used for write operation and read operation from a host to a slave; the DMA module is respectively connected with the protocol data cache module and the PCIE module through an AXI data bus and has the functions of taking out and forwarding data in the protocol data cache module to the PCIE module or reversing the data path; the DMA controller receives configuration information sent by a CPU, wherein the configuration information comprises a source address, a destination address and a transmission quantity, and the transmission quantity comprises a data total quantity and a data bit width; the DMA module distinguishes the position of data to be read and a data forwarding position according to a source address and a destination address, and calculates the burst length required by single AXI transmission according to the total data amount and the data bit width; the DMA controller sends a read-write request to an AXI data bus through an AXI interface through the configuration information to complete the configuration of the DMA module by the CPU, and after the operation required by the current configuration is completed, namely after a read response or a write response is received through the AXI interface on the DMA module, the read-write response is fed back to the CPU module through a data path to complete the current configuration operation;
step 4-2: the CPU sends the configuration information to a data frame coding/decoding module; the data frame coding/decoding module is written by Verilog language and comprises a frame coding module, a frame decoding module and a CRC (cyclic redundancy check) module; the frame decoding module is responsible for adding a lead code, a destination address, a source address, a data length and an Ethernet type to data; the frame decoding module is responsible for decoding the received frame, identifying a destination address and a source address, identifying a class and extracting effective data transmitted in a protocol; the CRC check module has two functions, namely, adding a CRC check code to the data and then sending the data to the frame coding module, and checking the correctness of the data sent by the frame decoding module; the configuration information of the CPU is transmitted into the data frame coding/decoding module in a parameter form, and the parameter content comprises: lead code bit width, destination address and source address bit width, data packet type bit width, protocol data bit width and check code bit width; after the frame coding/decoding module determines parameters of each part of the received data frame, the data frame is expanded according to the bit width; the decoding module expands the received data frame to obtain information including a destination address, a source address and protocol data, and stores the address information and the data in the protocol data caching module respectively.
6. The industrial ethernet protocol conversion method based on SOC according to claim 1, wherein: the step 5 specifically comprises the following steps:
step 5-1: when the host sends data to the slave, the DMA module configured by the CPU module takes the data to be sent out from the PCIE module connected with the host, adjusts the data bit width and the sending mode according to the configuration information in the DMA module, sends the data to the AXI data bus, and finds the CRC check module in the slave data frame coding/decoding module corresponding to the DMA module according to the address sent by the DMA module; after receiving the data, the data frame coding module adds a lead code, a destination address, a source address, a data length and an Ethernet type to the data; after the data frame is packaged, the data frame is sent to the slave machine to complete data transmission;
step 5-2: when the slave machine sends data to the host machine, the data frame is sent to the data frame decoding module by the slave machine, and the data frame is divided into a lead code, a destination address, a source address, a data length, an Ethernet type, effective data and a CRC check code in the module; after the data frame is split, the data frame is selected through a selector in the data frame code receiving module, the destination address and the source address are stored in an address information register of the protocol data caching module, and the valid data and the CRC check code are compared correctly through the CRC check module and then are stored in a data register of the protocol data caching module.
7. The SOC-based industrial Ethernet protocol conversion method of claim 6, wherein: in step 5, a plurality of data frame encoding/decoding modules and protocol data buffer modules can be mounted on the AXI data bus according to design requirements, and in step 7, a plurality of DMA modules can be mounted on the AXI data bus according to design requirements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211396522.9A CN115866081B (en) | 2022-11-09 | 2022-11-09 | SOC-based industrial Ethernet protocol conversion method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211396522.9A CN115866081B (en) | 2022-11-09 | 2022-11-09 | SOC-based industrial Ethernet protocol conversion method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115866081A true CN115866081A (en) | 2023-03-28 |
| CN115866081B CN115866081B (en) | 2024-02-27 |
Family
ID=85662871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211396522.9A Active CN115866081B (en) | 2022-11-09 | 2022-11-09 | SOC-based industrial Ethernet protocol conversion method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115866081B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117112469A (en) * | 2023-04-21 | 2023-11-24 | 荣耀终端有限公司 | Instruction transmission module and integrated circuit |
| CN117640783A (en) * | 2024-01-25 | 2024-03-01 | 富瀚微电子(成都)有限公司 | Data transmission method, system, electronic equipment and readable medium |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1206099A2 (en) * | 2000-11-14 | 2002-05-15 | Sancastle Technologies Ltd. | Network interface |
| JP2005216283A (en) * | 2004-01-30 | 2005-08-11 | Internatl Business Mach Corp <Ibm> | Single chip protocol converter |
| CN101483643A (en) * | 2008-12-19 | 2009-07-15 | 北京华力创通科技股份有限公司 | Data conversion method and apparatus |
| CN102170430A (en) * | 2011-03-24 | 2011-08-31 | 华中科技大学 | Multi-port multi-network protocol converter |
| CN103001827A (en) * | 2012-11-30 | 2013-03-27 | 无锡众志和达存储技术股份有限公司 | Method for Ethernet package detection based on 10Gb network card and field programmable gate array (FPGA) hardware check |
| US20160330094A1 (en) * | 2015-05-06 | 2016-11-10 | Marvell World Trade Ltd. | Apparatus and method for remotely testing memory-mapped devices of a system-on-chip via an ethernet interface |
| CN111064545A (en) * | 2019-12-02 | 2020-04-24 | 西安电子科技大学 | Device and method for realizing private network ground inspection with SPW interface based on FPGA |
| CN112100119A (en) * | 2020-08-18 | 2020-12-18 | 中国科学院声学研究所 | High-speed Ethernet frame reconstruction system based on FPGA |
| CN112799992A (en) * | 2021-02-08 | 2021-05-14 | 燕山大学 | Fieldbus chip architecture |
| CN113225376A (en) * | 2021-03-29 | 2021-08-06 | 桂林电子科技大学 | Ethernet frame and SDN data frame adapting method based on FPGA |
| CN114301995A (en) * | 2021-12-30 | 2022-04-08 | 上海交通大学 | Conversion switching and intercommunication fusion system and method of real-time industrial Ethernet protocol |
-
2022
- 2022-11-09 CN CN202211396522.9A patent/CN115866081B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1206099A2 (en) * | 2000-11-14 | 2002-05-15 | Sancastle Technologies Ltd. | Network interface |
| JP2005216283A (en) * | 2004-01-30 | 2005-08-11 | Internatl Business Mach Corp <Ibm> | Single chip protocol converter |
| CN101483643A (en) * | 2008-12-19 | 2009-07-15 | 北京华力创通科技股份有限公司 | Data conversion method and apparatus |
| CN102170430A (en) * | 2011-03-24 | 2011-08-31 | 华中科技大学 | Multi-port multi-network protocol converter |
| CN103001827A (en) * | 2012-11-30 | 2013-03-27 | 无锡众志和达存储技术股份有限公司 | Method for Ethernet package detection based on 10Gb network card and field programmable gate array (FPGA) hardware check |
| US20160330094A1 (en) * | 2015-05-06 | 2016-11-10 | Marvell World Trade Ltd. | Apparatus and method for remotely testing memory-mapped devices of a system-on-chip via an ethernet interface |
| CN111064545A (en) * | 2019-12-02 | 2020-04-24 | 西安电子科技大学 | Device and method for realizing private network ground inspection with SPW interface based on FPGA |
| CN112100119A (en) * | 2020-08-18 | 2020-12-18 | 中国科学院声学研究所 | High-speed Ethernet frame reconstruction system based on FPGA |
| CN112799992A (en) * | 2021-02-08 | 2021-05-14 | 燕山大学 | Fieldbus chip architecture |
| CN113225376A (en) * | 2021-03-29 | 2021-08-06 | 桂林电子科技大学 | Ethernet frame and SDN data frame adapting method based on FPGA |
| CN114301995A (en) * | 2021-12-30 | 2022-04-08 | 上海交通大学 | Conversion switching and intercommunication fusion system and method of real-time industrial Ethernet protocol |
Non-Patent Citations (1)
| Title |
|---|
| 张立国: "基于 IEC 1158 标准的现场总线芯片设计", 《电子技术应用》, 6 April 2022 (2022-04-06), pages 18 - 22 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117112469A (en) * | 2023-04-21 | 2023-11-24 | 荣耀终端有限公司 | Instruction transmission module and integrated circuit |
| CN117640783A (en) * | 2024-01-25 | 2024-03-01 | 富瀚微电子(成都)有限公司 | Data transmission method, system, electronic equipment and readable medium |
| CN117640783B (en) * | 2024-01-25 | 2024-04-09 | 富瀚微电子(成都)有限公司 | Data transmission method, system, electronic equipment and readable medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115866081B (en) | 2024-02-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN115866081B (en) | SOC-based industrial Ethernet protocol conversion method | |
| CN112799992B (en) | Fieldbus chip architecture | |
| CN111327603B (en) | Data transmission method, device and system | |
| US20040139220A1 (en) | Reduced hardware network adapter and communication method | |
| CN108768981B (en) | IP core for realizing Powerlink industrial real-time Ethernet communication | |
| CN110297797B (en) | Heterogeneous protocol conversion device and method | |
| CN111656336A (en) | PCIE sending and receiving method, device, equipment and system | |
| CN112395230A (en) | UART interface extension circuit based on programmable logic device | |
| CN112148651B (en) | Enhanced rapidio interconnection device and equipment | |
| CN102420763A (en) | Direct memory access (DMA) sending method | |
| CN108462620B (en) | Gilbert-level SpaceWire bus system | |
| CN113961494B (en) | Bridging system of PCIE bus and AXI bus | |
| CN114297124B (en) | Communication system of SRIO high-speed bus based on FPGA | |
| CN113810109B (en) | Multi-protocol multi-service optical fiber channel controller and working method thereof | |
| CN109902055B (en) | SLIP coding data stream transmission method suitable for narrow-band data network | |
| CN113051204A (en) | Serial backplane bus communication method and system | |
| CN107579894B (en) | FPGA-based EBR1553 bus protocol implementation device | |
| CN108429707B (en) | Time trigger service repeater and method adapting to different transmission rates | |
| CN108614792B (en) | 1394 transaction layer data packet storage management method and circuit | |
| CN111510363A (en) | Slave station conversion device based on MODBUS protocol and control method thereof | |
| CN116248758A (en) | Efficient bridge type connection structure of kernel-network on chip | |
| CN107342920B (en) | Internet of things gateway access equipment and data interaction method thereof | |
| CN112147918B (en) | Asynchronous data interaction method and system based on ARM + FPGA + DSP architecture | |
| CN107317773B (en) | On-chip network communication interface and communication method | |
| CN114385544A (en) | UART chip and FPGA chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |