CN111656336A

CN111656336A - PCIE sending and receiving method, device, equipment and system

Info

Publication number: CN111656336A
Application number: CN201880087858.2A
Authority: CN
Inventors: 曹雷; 孙学全; 赵阳
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-06-30
Filing date: 2018-06-30
Publication date: 2020-09-11
Anticipated expiration: 2038-06-30
Also published as: WO2020000489A1; CN111656336B

Abstract

Embodiments of the present application provide a PCIE sending and receiving method, an apparatus, a device, and a system, which are used to implement using a PCIE controller without changing an existing software architecture by a large margin. The PCIE sending device comprises a packaging module used for generating first information and a second parameter group; a virtual interface module, configured to receive a second parameter set from a block, and generate a third parameter set that satisfies a PCIE format according to the second parameter set, where the third parameter set includes the storage address and a destination address in a second memory corresponding to the PCIE receiving apparatus; and the PCIE driving module is used for receiving the third parameter group from the virtual interface module and driving the first PCIE controller to send the first information according to the third parameter group. The virtual interface module plays a role in connection between the encapsulation module and the PCIE driving module, so that the PCIE transmission can be realized even if the encapsulation module is not subjected to adaptation adjustment.

Description

PCIE sending and receiving method, device, equipment and system

Technical Field

The present invention relates to the field of electronic science and technology, and in particular, to a PCIE transmitting and receiving method, apparatus, device, and system.

Background

With the development of electronic technology and the increase of user demand, terminal devices need to be capable of implementing more and more functions, and in order to implement the functions, the terminal devices often need to include a plurality of chips. Interconnection needs to be realized among a plurality of chips of the terminal equipment to transmit data, so that the terminal equipment can realize corresponding functions. In the existing terminal device, the chips may be interconnected in various ways, for example, a modulation and demodulation (modem) communication chip and an Application (APP) chip in the terminal device may be interconnected through a Universal Serial Bus (USB) port or a gigabit ethernet media access control (GMAC) network card.

In the 5G technology, the downlink rate at the wireless air interface side can reach 10Gbps or more, while the transmission rate of the GMAC interface is only 1Gbps, the transmission rate of the USB3.0 interface can only reach 5Gbps theoretically, and the actual measurement performance is also reduced, so that the chip interconnection mode of the GMAC network card or the USB interface is difficult to meet the requirement of the 5G technology, and the Peripheral Component Interconnect Express (PCIE) further improves the transmission efficiency between chips due to the high transmission rate of the PCIE interconnection mode, which is one of the important research directions of the interconnection schemes between chips in the 5G technology.

However, if PCIE interconnection is to be used between chips, a plurality of encapsulation modules in software run by a chip processor (for example, encapsulation modules for adding a packet header to run data so that the packet header conforms to a protocol stack specified by a transmission protocol, an AT command handler for dialing and configuring modem, an operation, administration and maintenance (OAM) function for acquiring measurement information) are typically designed specially, so that these encapsulation modules can be adapted to a PCIE driver module, and thus a processor can transmit information generated by running these encapsulation modules through a PCIE controller in a PCIE driver module driver chip, which is complex in modification of software and hinders further use of PCIE interconnection in a chip based on an existing software architecture, and therefore, a scheme capable of simplifying PCIE interconnection design between chips is needed AT present, the existing chip can use the PCIE controller on the basis of not greatly changing the existing software architecture.

Disclosure of Invention

Embodiments of the present application provide a PCIE sending and receiving method, apparatus, device, and system, so as to support a PCIE interface without greatly changing an existing software architecture.

In a first aspect, an embodiment of the present application provides a peripheral device high-speed interconnect PCIE transmitting apparatus, including an encapsulation module, a virtual interface module, and a PCIE driving module. The encapsulation module is used for generating first information to be sent and a second parameter group meeting a preset encapsulation format according to a preset encapsulation rule, wherein the second parameter group comprises a storage address of the first information in a first memory corresponding to the PCIE sending device; the virtual interface module is used for receiving the second parameter group from the encapsulation module and generating a third parameter group meeting the PCIE format according to the second parameter group, wherein the third parameter group comprises the storage address and a destination address in a second memory corresponding to the PCIE receiving device; and the PCIE driving module is configured to receive the third parameter group from the virtual interface module, analyze the third parameter group to obtain the storage address and the destination address, and send a first instruction to a first PCIE controller corresponding to the PCIE sending device, where the first instruction is used to drive the first PCIE controller to send the first information. The first instruction includes the destination address, and further includes the first information or the storage address of the first information in the first memory.

By adopting the scheme, the virtual interface module can receive the second parameter set which is generated by the encapsulation module and meets the preset encapsulation format, and converts the second parameter set into the third parameter set which can be identified and received by the PCIE driving module, and the virtual interface module plays a bearing role between the encapsulation module and the PCIE driving module, so that even if the software structure of the encapsulation module is not adjusted in an adaptive manner according to the PCIE driving module, the PCIE transmission can be realized. Compared with the method for changing the open-source and universal encapsulation module, the method has the advantages that the design brought by adding the virtual interface module in the PCIE sending device is less, so that the existing chip can support the PCIE interface on the basis of not greatly changing the existing software architecture.

Based on the first aspect, in a possible implementation manner, the virtual interface module includes a virtual interface and a PCIE adaptation layer. The virtual interface corresponds to the encapsulation module, and is used for receiving the second parameter set from the corresponding encapsulation module and providing the second parameter set to the PCIE adaptation layer; and the PCIE adaptation layer is used for determining an address space corresponding to a virtual interface which provides the second parameter group for the second memory in the second memory, determining a destination address according to the address space, and generating a third parameter group which meets the PCIE format according to the second parameter group and the destination address.

By adopting the scheme, the virtual interface is adapted upwards to the corresponding encapsulation module, the second parameter group provided by the encapsulation module is received, the PCIE adaptation layer is adapted downwards to the PCIE driving module, the destination address is determined according to the corresponding relation between the virtual interface and the address space in the second memory, and the third parameter group which can be identified and received by the PCIE driving module is generated according to the second parameter and the destination address, so that the receiving effect of the virtual interface module between the encapsulation module and the PCIE driving module is realized.

Based on the first aspect, in a possible implementation manner, the virtual interface is a virtual network interface adapter VNIC or a virtual serial communication port VCOM.

Based on the first aspect, in a possible implementation manner, the PCIE sending apparatus includes a plurality of encapsulation modules, and a virtual interface module of the PCIE sending apparatus includes a plurality of virtual interfaces; each virtual interface corresponds to one encapsulation module, and each virtual interface has a priority; the PCIE adaptation layer is specifically configured to: and acquiring a processing sequence of the plurality of virtual interfaces according to the priorities of the plurality of virtual interfaces, and sequentially generating a third parameter group corresponding to each virtual interface according to the processing sequence.

By adopting the scheme, the service corresponding to the virtual interface with higher priority can be preferentially issued to the PCIE adaptation layer and the PCIE driving module and is preferentially processed, so that the processor operates the PCIE driving module to drive the PCIE controller to preferentially send the information to be sent corresponding to the service with higher priority, and the quality of service (QOS) of the whole system is improved.

Based on the first aspect, in a possible implementation manner, the PCIE transmitting apparatus further includes: the business module is used for generating business operation data in the first memory; based on this, the encapsulation module is specifically configured to perform encapsulation processing on the service operation data according to a preset encapsulation rule to generate first information and a second parameter group corresponding to the type of the service operation data.

Based on the first aspect, in a possible implementation manner, the encapsulation module in the PCIE sending apparatus is a transmission control protocol/internet protocol TCP/IP stack encapsulation module, or an AT command handler encapsulation module, or an operation, administration, and maintenance OAM detection program encapsulation module.

In a second aspect, an embodiment of the present application provides a peripheral device high-speed interconnect PCIE receiving apparatus, including: the device comprises a PCIE driving module, a virtual interface module and an encapsulation module. The PCIE driving module is configured to determine a storage address of the second information to be processed in the second memory corresponding to the PCIE receiving apparatus, and generate a fourth parameter group meeting the PCIE format, where the fourth parameter group includes the storage address; the virtual interface module is configured to receive the fourth parameter group from the PCIE driver module, and generate a fifth parameter group that satisfies a preset encapsulation format according to the fourth parameter group; the fifth parameter set comprises the storage address; and the encapsulation module is used for receiving the fifth parameter group from the virtual interface module, analyzing the fifth parameter group to obtain the storage address, acquiring the second information according to the storage address, and decapsulating the second information according to a preset decapsulation rule to generate to-be-processed data.

By adopting the above scheme, the virtual interface module can receive the fourth parameter set generated by the PCIE driver module, and convert the fourth parameter set into the fifth parameter set that can be recognized and received by the encapsulation module, which plays a role in carrying between the PCIE driver module and the encapsulation module, so that even if the software structure of the encapsulation module is not adapted and adjusted according to the PCIE driver module, PCIE reception can also be achieved. Compared with the method for changing the open-source and universal encapsulation module, the method for changing the virtual interface module in the PCIE receiving device has the advantages that the design caused by adding the virtual interface module in the PCIE receiving device is less, and therefore the PCIE interface can be supported by the existing chip on the basis that the existing software architecture is not required to be changed greatly.

Based on the second aspect, in a possible implementation manner, the virtual interface module includes a virtual interface and a PCIE adaptation layer. The PCIE adapter layer is used for receiving a fourth parameter group from the PCIE driving module and determining an address space corresponding to the storage address according to the fourth parameter group; determining a virtual interface corresponding to the address space; determining a preset packaging format of a packaging module corresponding to the virtual interface; generating a fifth parameter group meeting the preset packaging format according to the fourth parameter group, and providing the fifth parameter group for the virtual interface; and the virtual interface corresponds to the encapsulation module and is used for receiving the fifth parameter set provided by the PCIE adaptation layer and sending the fifth parameter set to the encapsulation module.

By adopting the scheme, the PCIE adaptation layer is adapted to the PCIE driving module, the virtual interface corresponding to the second information is determined according to the corresponding relation between the address space in the second memory and the virtual interface, and the encapsulation format of the fifth parameter set is determined according to the corresponding relation between the virtual interface and the encapsulation module, so that the fourth parameter set is converted into the fifth parameter set which can be identified and received by the encapsulation module. The virtual interface adapts to the corresponding encapsulation module, the fifth parameter set is provided for the encapsulation module, and the virtual interface module can take bearing action between the encapsulation module and the PCIE driving module through the virtual interface and the PCIE adaptation layer.

Based on the second aspect, in a possible implementation manner, the virtual interface is a virtual network interface adapter VNIC or a virtual serial communication port VCOM.

Based on the second aspect, in a possible implementation manner, the encapsulation module is specifically configured to perform decapsulation processing on the second information according to a preset decapsulation rule, so as to generate to-be-processed data corresponding to the type of the encapsulation module; the PCIE receiving apparatus further includes a service module, where the service module is configured to process the to-be-processed data generated by the encapsulation module.

Based on the second aspect, in a possible implementation manner, the encapsulation module in the PCIE receiving apparatus is a transmission control protocol/internet protocol TCP/IP stack encapsulation module, or an AT command handler encapsulation module, or an operation, administration, and maintenance OAM detection program encapsulation module.

In a third aspect, an embodiment of the present application provides a method for sending a peripheral device high-speed interconnect PCIE, including: generating first information to be sent and a second parameter group meeting a preset packaging format by using a packaging module according to a preset packaging rule; the second parameter group comprises a storage address of the first information in a first memory corresponding to the PCIE sending device; generating a third parameter group meeting the PCIE format according to the second parameter group by utilizing a virtual interface module, wherein the third parameter group comprises the storage address and a destination address in a second memory corresponding to the PCIE receiving device; and analyzing the third parameter group by using the PCIE driver module to obtain a storage address and a destination address, and sending a first instruction for driving the first PCIE controller to send the first information to the first PCIE controller corresponding to the PCIE sending device, where the first instruction includes the destination address, and the first instruction further includes the first information or a storage address of the first information in the first memory.

Based on the third aspect, in a possible implementation manner, the virtual interface module includes a virtual interface and a PCIE adaptation layer; generating a third parameter group meeting the PCIE format according to the second parameter group by using the virtual interface module, wherein the third parameter group comprises: receiving a second parameter set from an encapsulation module by using a virtual interface, and providing the second parameter set to the PCIE adaptation layer; and determining an address space corresponding to the virtual interface in the second memory by using the PCIE adaptation layer, determining a destination address of the first information according to the address space, and generating the third parameter group meeting the PCIE format according to the second parameter and the destination address.

Based on the third aspect, in a possible implementation, the virtual interface is a virtual network interface adapter VNIC, and/or a virtual serial communication port VCOM.

Based on the third aspect, in a possible implementation manner, the PCIE sending apparatus includes a plurality of encapsulation modules, and the virtual interface module includes a plurality of virtual interfaces; each virtual interface corresponds to one encapsulation module, and each virtual interface has a priority; generating the third parameter group meeting the PCIE format according to the second parameter and the destination address, including: and obtaining a processing sequence of the plurality of virtual interfaces by using the PCIE adaptation layer according to the priorities of the plurality of virtual interfaces, and sequentially generating the third parameter group corresponding to each virtual interface according to the processing sequence.

In a fourth aspect, an embodiment of the present application provides a peripheral device high-speed interconnect PCIE receiving method, including: determining a storage address of second information to be processed in a second memory corresponding to a PCIE receiving device by using a PCIE driving module, and generating a fourth parameter group meeting the PCIE format, wherein the fourth parameter group comprises the storage address; then, a virtual interface module is used for receiving the fourth parameter group from the PCIE driving module, and a fifth parameter group meeting a preset packaging format is generated according to the fourth parameter group; the fifth parameter set comprises the storage address; and then, receiving the fifth parameter group by using an encapsulation module, analyzing the fifth parameter group to obtain the storage address, acquiring the second information according to the storage address, and decapsulating the second information according to a preset decapsulation rule to generate data to be processed.

Based on the fourth aspect, in a possible implementation manner, the virtual interface module includes a virtual interface and a PCIE adaptation layer; generating a fifth parameter group meeting the identification format of the packaging module by using a virtual interface module according to the storage address of the second information, wherein the fifth parameter group comprises: receiving the fourth parameter group from the PCIE driving module by utilizing the PCIE adaptation layer, and determining an address space corresponding to the storage address according to the fourth parameter group; determining the virtual interface corresponding to the address space; determining a preset packaging format of a packaging module corresponding to the virtual interface; generating a fifth parameter group meeting the preset packaging format according to the fourth parameter group, and providing the fifth parameter group for the virtual interface; and receiving the fifth parameter group provided by the PCIE adaptation layer by using the virtual interface, and sending the fifth parameter group to the encapsulation module.

Based on the fourth aspect, in one possible implementation manner, the virtual interface is a virtual network interface adapter VNIC or a virtual serial communication port VCOM.

In a fifth aspect, the present application provides a peripheral device high-speed interconnect PCIE transmitting device, including a processor and a first PCIE controller, where the processor is configured to: operating a packaging module to generate first information to be sent and a second parameter group meeting a preset packaging format according to a preset packaging rule; the second parameter group comprises a storage address of the first information in a first memory corresponding to the PCIE sending device; generating a third parameter group meeting the PCIE format according to the second parameter group by operating a virtual interface module, wherein the third parameter group comprises the storage address and a destination address in a second memory corresponding to the PCIE receiving equipment; analyzing the third parameter group to obtain the storage address and the destination address by operating a PCIE driver module, and sending a first instruction for driving the first PCIE controller to send the first information to the first PCIE controller, where the first instruction includes the destination address, and the first instruction further includes the first information or a storage address of the first information in the first memory; the first PCIE controller is configured to receive the first instruction, acquire the first information from the first instruction, or acquire the first information from the first memory according to the storage address in the first instruction, and send the first information to a second PCIE controller corresponding to the PCIE receiving device.

Based on the fifth aspect, in a possible implementation manner, the PCIE sending device is a root complex, and the processor is further configured to: operating the PCIE driving module to generate an interrupt message according to the destination address and sending the interrupt message to the first PCIE controller; the first PCIE controller is further configured to send the interrupt message to the second PCIE controller.

In the existing PCIE, an interrupt mechanism is absent in a process of sending information to an endpoint device by a device serving as a root complex, so that the endpoint device cannot determine and process information sent by the root complex after receiving the information sent by the root complex device. According to the method and the device, when the PCIE sending equipment is the root complex, the interrupt information is also sent, so that the corresponding PCIE receiving equipment serving as the endpoint equipment can determine and process the information sent by the PCIE sending equipment through the interrupt information.

In a sixth aspect, an embodiment of the present application provides a peripheral device high-speed interconnect PCIE receiving device, including a processor and a second PCIE controller, where the second PCIE controller is configured to receive second information sent by a first PCIE controller corresponding to a PCIE sending device, and store the second information in a second memory corresponding to the PCIE receiving device according to a destination address corresponding to the second information; the processor is configured to operate the PCIE driver module to determine a storage address of the second information in the second memory, and generate a fourth parameter group meeting the PCIE format, where the fourth parameter group includes the storage address; the virtual interface module is operated to receive the fourth parameter group from the PCIE driving module, and a fifth parameter group meeting a preset packaging format is generated according to the fourth parameter group; the fifth parameter set comprises the storage address; and operating an encapsulation module to receive the fifth parameter group, analyze the fifth parameter group to obtain the storage address, obtain the second information according to the storage address, and decapsulate the second information according to a preset decapsulation rule to generate data to be processed.

Based on the sixth aspect, in a possible implementation manner, the PCIE receiving device is an endpoint, and the PCIE receiving device further includes an interrupt register respectively connected to the second PCIE controller and the processor; the second PCIE controller is further configured to receive an interrupt message sent by the first PCIE controller, and store the interrupt message in the interrupt register; the interrupt register is used for caching the interrupt message and sending a first trigger signal to the processor; the processor is further configured to determine, after receiving the first trigger signal, a storage address in the second memory for storing the second information according to the interrupt message in the interrupt register.

By adopting the above scheme, the interrupt register is added in the PCIE receiving device as the endpoint device, so that an interrupt mechanism is added to the process of receiving the information sent by the root complex device by the endpoint device, and the PCIE receiving device as the endpoint device can determine and process the information sent by the PCIE sending device as the root complex.

In a seventh aspect, an embodiment of the present invention provides a PCIE system for high-speed interconnection of peripheral devices, where the PCIE system includes the PCIE sending device according to the fifth aspect, and/or the PCIE receiving device according to the sixth aspect.

In an eighth aspect, a computer-readable storage medium is provided for storing a computer program comprising instructions for performing the method of any one of the possible implementations of the third aspect, the fourth aspect, or the fourth aspect.

In a ninth aspect, there is provided a computer program product, the computer program product comprising: computer program code which, when run on a computer or processor, causes the computer or processor to perform any of the possible implementations of the third aspect, the fourth aspect, the third aspect or the method of any of the possible implementations of the fourth aspect described above.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of a PCIE interconnection system provided in an embodiment of the present application;

fig. 2 is a schematic diagram of a software architecture executed by a processor according to an embodiment of the present application;

fig. 3 is a schematic diagram of an address space mapping relationship of memories of PCIE devices located at two ends according to an embodiment of the present application;

fig. 4 is a schematic diagram illustrating a correspondence relationship between a virtual interface and an address space according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of a PCIE interconnection system provided in an embodiment of the present application, and as shown in fig. 1, a chip 1 includes a processor 11 and a PCIE controller 12, a chip 2 includes a processor 21 and a PCIE controller 22, and the PCIE controller 12 and the PCIE controller 22 are connected through PCIE physical connection. Furthermore, the chip 1 is also connected to the memory 1, and the processor 11 in the chip 1 processes the data in the memory 1 by running software, and the software run by the processor 11 may also be stored in the memory 1 or another memory coupled to the chip 1. The chip 2 is also connected to the memory 2, and the processor 21 in the chip 2 processes the data in the memory 2 by running software, which the processor 12 runs, and which may also be stored in said memory 2 or in another memory coupled to the chip 2. Each of the above memories may comprise a plurality of different types of memories for implementing different storage capabilities, such as storing different data or software codes, etc. The memory may include at least one of volatile memory or non-volatile memory.

In the PCIE interconnect system shown in fig. 1, a chip 1 serves as a root complex (root complex) in the PCIE interconnect, and a chip 2 serves as an end point (end point) in the PCIE interconnect. In the existing PCIE protocol, there is no mechanism for triggering the chip 2 serving as an endpoint to determine that the information sent by the chip 1 is received, and to process the information in the memory 2. Based on this, in a possible implementation manner, the processor 21 of the chip 2 in this embodiment may periodically query the memory 2 according to a preset cycle interval to determine whether the information sent by the chip 1 is received within the cycle interval, and if it is determined that the information sent by the chip 1 is received within the cycle interval, may determine a storage address of the received information sent by the chip 1 in the memory 2, and process the information.

In another possible alternative implementation, as shown in fig. 1, the chip 2 further includes an interrupt register 23 connected to the processor 21 and the PCIE controller 22, respectively. After the chip 1 sends the information to be sent to the chip 2, it also sends an interrupt message to the chip 2 through the PCIE controller 12, where the interrupt message is determined by the processor 11 according to the destination address of the information to be sent in the memory 2. The PCIE controller 22 of the chip 2 buffers the interrupt message in the interrupt register 23 after receiving the interrupt message. After storing the interrupt message, the interrupt register 23 sends a first trigger signal to the processor 21, so that the processor 21 actively queries the interrupt message buffered by the interrupt register 23 after receiving the first trigger signal, and determines the storage address of the received information in the memory 2 according to the interrupt message, thereby acquiring the information received from the chip 1 from the memory 2 and processing the information.

Since the chip 1 and the chip 2 are interconnected through the PCIE controllers (12, 22), the PCIE controllers (12, 22) need to be driven by the PCIE driver module, and therefore, architectures of software run by the processor 11 and the processor 21 in the existing non-PCIE interconnection system need to be adjusted. Based on this, the embodiment of the present application provides a software architecture capable of driving a processor to work, and an existing chip can use a PCIE controller without greatly changing an existing software architecture that does not support PCIE interconnection. Fig. 2 is a schematic diagram of architectures of software running in processors in the chip 1 and the chip 2, respectively, based on the PCIE interconnect system shown in fig. 1. As shown in fig. 2, the software architecture executed by the processor 11 and the processor 12 includes a service module (111, 211), a plurality of encapsulation modules, a virtual interface module (113, 213), and a PCIE driver module (114, 214), where the encapsulation modules, the virtual interface module (113, 213), and the PCIE driver module (114, 214) may be included in a kernel (kernel) of an operating system in the processor 11 and the processor 12, as shown by a dotted line in fig. 2, the kernel of the processor 11 and the processor 12 may be various types such as a Linux kernel, a Real Time Operation System (RTOS) kernel, and the like.

Next, taking a process of sending information from the chip 1 to the chip 2 as an example, a framework of software running in the processor 11 is described, it should be understood that the process of sending information from the chip 2 to the chip 1 is similar, and details are not repeated in this application. The software architecture, such as an operating system or its kernel, run by the processor 11 may include a service module 111, an encapsulation module (1121, 1122, 1123, 1124), a virtual interface module 113, and a PCIE driver module 114. Thus, the software architecture may exist as a computer program that when executed by a processor or computer performs information or data processing.

The processor 11 generates service operation data in the memory 1 by operating the service module 111 in the software architecture. The specific implementation of the service module 111 is related to the type of the chip 1. For example, when the chip 1 is an application chip, the service module 111 includes various applications, such as a wechat client, a hundredth client, and the like, and the processor 11 generates service operation data in the memory 1 by running the applications in the service module 111. For another example, when the chip 1 is a communication chip, the service module 111 includes various communication-related programs, for example, 4G (fourth generation, 4)^thGeneration) or 5G (fifth Generation, 5)^thGeneration), after the antenna of the communication chip receives the wireless signal, the processor 11 demodulates the received wireless signal by running the 4G or 5G air interface communication program to obtain a received air interface message conforming to an air interface protocol, analyzes the air interface message, obtains an IP message, and stores the IP message as service running data in the memory 1.

In the framework of the software executed by the processor 11, a plurality of encapsulation modules (such as the encapsulation modules 1121, 1122, 1123, and 1124 in fig. 2) are included, and the processor 11 executes different types of encapsulation modules, which can perform different encapsulation processing on the service execution data according to different encapsulation rules, so as to obtain different types of information to be sent, that is, the first information. Each type of information to be transmitted has a data format corresponding to the type. For example, the encapsulation module 1121 may be a transmission control protocol/internet protocol (TCP/IP) protocol stack encapsulation module, and when the chip 1 is an application chip, the processor 11 runs the encapsulation module 1121 to perform operations such as data segmentation and message header addition on the service running data, so as to encapsulate the service running data into an IP message including a destination IP address in the memory 1. For another example, the encapsulation module 1122 may be an AT command handler encapsulation module, and when the service operation data obtained by the processor 11 through the operation of the service module 111 is the AT command data, the processor 11 operates the encapsulation module 1122, and may generate AT command messages according to the AT command data, where the AT command messages have multiple types, such as configuration commands, query commands, and the like, and the AT commands generated by the processor 11 operating the encapsulation module 1122 have multiple formats, and the AT command messages with different formats correspond to the AT command messages with different types. For another example, the encapsulation module 1123 may be an OAM detection program encapsulation module, and when the service operation data obtained by the processor 11 through the operation service module 111 is OAM detection data, the processor 11 operates the encapsulation module 1123, may generate an OAM detection message according to the OAM detection data, and so on.

After the processor 11 generates the service operation data in the memory 1, the service operation module 111 may further generate a first parameter group, where the first parameter group may include parameters such as a storage address and a data length of the service operation data. After generating the first parameter group, the processor 11 continues to operate the encapsulation module corresponding to the type of the service operation data, for example, when the type of the service operation data is communication data, the encapsulation module 1121 is operated to encapsulate the service operation data into an IP packet; when the service operation data type is AT command data, the encapsulation module 1122 is operated to generate an AT command message according to the AT command data; when the type of the service operation data is OAM detection data, the operation encapsulation module 1123 generates an OAM detection message according to the OAM detection data. When the processor 11 operates the encapsulation module corresponding to the service operation data type, the service operation data may be obtained from the memory 1 according to the storage address in the first parameter group, so as to generate information to be sent according to the service operation data. In a possible implementation manner, if the data amount of the service operation data is small, the first parameter group may also include the service operation data, so that when the processor 11 runs the encapsulation module, the service operation data may be directly obtained from the first parameter group.

After the processor 11 generates the information to be sent in the memory 1, it also generates a second parameter set meeting a preset packaging format by operating the packaging module, where the second parameter set includes a storage address of the information to be sent in the memory 1, and may also include parameters such as an information length of the information to be sent. For example, the encapsulating module 1121 is a TCP/IP protocol stack, the information to be sent generated by the processor 11 running the encapsulating module 1121 is an IP packet, and the IP packet may be sent by a network interface adapter (NIC), so that the second parameter set generated by the processor 11 running the encapsulating module 1121 may be used as a running parameter of a driver running the NIC. For another example, the encapsulation module 1122 is an AT command handler, the information to be sent generated by the processor 11 operating the encapsulation module 1122 is an AT command message, and the AT command message can be sent through a serial communication port (COM), so that the second parameter group generated by the encapsulation module 1122 can be used as an operating parameter of a driver operating the COM. In this embodiment, the processor 11 may operate the virtual interface module 113 in the configuration phase, where multiple virtual interfaces in the virtual interface module 113 respectively simulate a registration process of driver software of a physical interface (e.g., NIC, COM), and register the physical interface with a corresponding encapsulation module, where the registration information includes an identifier, a type, a format requirement, and the like of the physical interface, and therefore, for the encapsulation module, the encapsulation module may accept registration of the virtual interface under an existing software structure that does not support PCIE interconnection, so that when the processor 11 operates the encapsulation module, after generating the second parameter set, the processor may invoke the virtual interface corresponding to the encapsulation module by operating an existing program that invokes the physical interface in the encapsulation module, and even an encapsulation module that does not support PCIE interconnection may be coupled with a PCIE driver module on a lower layer through the corresponding virtual interface. Therefore, the virtual interface module plays a role in connection between the encapsulation module and the PCIE driver module.

The processor 11 runs the virtual interface corresponding to the encapsulation module in the virtual interface module 113, and the virtual interface replaces the driver software of the physical interface (such as the above NIC, COM, and the like) in the existing software architecture to receive the second parameter set. As shown in the software architecture of fig. 2, the virtual interface module 113 includes a plurality of virtual interfaces (e.g., the virtual interfaces A, B, C and D in fig. 2), which may be of the same type or different types, and the different types of virtual interfaces may receive the second parameter sets generated by running different encapsulation modules, so that the virtual interface module 113 can adapt the different types of encapsulation modules upwards. For example, the virtual interface a is a Virtual Network Interface Controller (VNIC), and after the processor 11 runs the encapsulation module 1121 to generate the communication packet and the second parameter set, the virtual interface a replaces the driver software of the NIC in the existing software architecture to receive the second parameter set. For another example, the virtual interface B is a virtual serial communication port (VCOM), the processor 11 executes the encapsulation module 1122 to generate an AT command message and a second parameter set, and then calls the virtual interface B, and the virtual interface B replaces the driver software of the COM in the existing software architecture to receive the second parameter set.

In one possible implementation, as shown in fig. 2, the virtual interface module 113 includes a plurality of virtual interfaces and a PCIE adaptation layer 1132. After the processor 11 receives the second parameter set by using the virtual interface instead of the driving software of the actual interface in the existing software architecture, the PCIE adaptation layer 1132 is operated to convert the second parameter set into a third parameter set meeting the PCIE format, so that the third parameter set can be identified and received by the PCIE driving module. The third parameter set at least includes a storage address of the information to be transmitted in the memory 1, a destination address of the information to be transmitted in the memory 2, and may also include parameters such as an information length of the information to be transmitted. Based on the PCIE protocol, the chip 1 serving as the sending end may specify a storage address of information to be sent in the memory 2. As shown in fig. 3, at the beginning of powering on chip 1 and chip 2, chip 1 enumerates and maps the address space configuration of chip 2, so that

address spaces

21, 22, 23, and 24 for storing information sent by chip 1 in memory 2 can be determined (chip 2 is the same way). In the software architecture run by the processor 11, the virtual interfaces in the virtual interface module 113 correspond to the address spaces of the memory 2, respectively, as shown in fig. 4, and the chip 2 is similar. When the processor 11 runs the virtual interface module 113, the destination address of the information to be sent in the memory 2 is determined according to the virtual interface receiving the second parameter group. For example, the virtual interface a corresponds to the address space 21 in the memory 2, and when the processor 11 runs the virtual interface module 113, if the virtual interface a receives the second parameter group, the processor 11 determines that the destination address of the information to be sent is the address space 21.

In a possible implementation manner, the processor 11 may monitor the usage of each address space in the memory 2, and after determining the address space corresponding to the virtual interface, may further specify a more specific destination address in the address space for the information to be sent according to the storage condition of the address space. For example, after the chip 1 enumerates and maps the address space configuration of the chip 2, the processor 11 may partition each address space in the memory 2 into a plurality of memory units by running the PCIE adaptation layer, and continuously monitor the usage of the plurality of memory units in each address space in the memory 2. After determining the address space corresponding to the virtual interface, the processor 11 may further specify one or more unoccupied storage units for the information to be sent by operating the PCIE adaptation layer according to the usage of the plurality of storage units in the address space, so as to store the information to be sent.

The processor 11 runs the PCIE driver module 114 after generating the third parameter set satisfying the PCIE format by running the virtual interface module 113. The processor 11 drives the PCIE controller 12 to send information to be sent to the PCIE controller 22 of the chip 2 according to the third parameter set by operating the PCIE driving module 114, and the specific implementation manners of the method may include at least the following two types: in a feasible implementation manner, the processor 11, by operating the PCIE driver module 114, obtains information to be sent from the memory 1 according to a storage address of the information to be sent in the third parameter set in the memory 1, and drives the PCIE controller to send the information to be sent to the chip 2. This implementation requires the processor 11 to send information to be sent to the PCIE controller 12, and is therefore suitable for a situation where the amount of information data to be sent is small, for example, control plane information with a small data amount, such as an AT command message or an OAM message from the encapsulation module. In another possible implementation manner, the processor 11 obtains a storage address of information to be sent in the third parameter set by operating the PCIE driver module 114, and drives the PCIE controller 12 to obtain the information to be sent from the memory 1 according to the storage address of the information to be sent, and sends the information to be sent to the chip 2. In the implementation manner, the PCIE controller 12 acquires and sends the information to be sent from the memory 1, so compared to the former implementation manner, the implementation manner is more suitable for a situation that the data amount of the information to be sent is large, such as an IP packet from an encapsulation module, where the packet may be from data of a higher-level service module and IP-encapsulated by the encapsulation module, and the data may include user plane data with a large data amount, such as game data or graphic data.

When the processor 11 runs the PCIE driver module 114, the PCIE controller 12 may be driven to send the identification information of the address space 21 to the PCIE controller 22, so that the PCIE controller 22 may store the received information in the address space 21 of the memory 2 according to the identification information of the address space 21. In another feasible implementation manner, the PCIE physical connection between the PCIE controller 12 and the PCIE controller 22 includes a plurality of virtual lanes, which may also be referred to as logical lanes, where the plurality of virtual lanes correspond to a plurality of address spaces of the memories at two ends, and the processor 11 determines the virtual lane corresponding to the address space 21 and drives the PCIE controller 12 to send information to be sent through the virtual lane by operating the PCIE driving module 114, so that the PCIE controller 22 of the chip 2 stores the received information in the address space 21 corresponding to the lane in the memory 2 after receiving the information from the virtual lane.

During the process of sending information from the chip 1 to the chip 2, the second parameter set generated by the processor 11 by running the package module may be the second parameter set of the driver software for running the physical interface in the existing software architecture, the adaptation to the encapsulation module is achieved by running the driver software of the virtual interface in the virtual interface module 113 instead of the physical interface, meanwhile, by operating the PCIE adaptation layer 1132 to convert the second parameter set into a third parameter set recognizable by the PCIE driver module 114, the adaptation with the PCIE driver module 114 is realized, therefore, the PCIE interconnection can be realized without changing the existing encapsulation module, compared with the change of an open source and general encapsulation module, the design brought by adding the virtual interface module 113 in the software architecture operated by the processor 11 is much less, therefore, the PCIE controller can be used by the existing chip on the basis of not greatly changing the existing software architecture. It can be understood that the virtual interface of this embodiment is used to realize the interface with the encapsulation module, so as to adapt to encapsulation modules of different types upwards, and the PCIE adaptation layer adapts to the PCIE driver module downwards. Based on the scheme, the virtual interface module 113 can realize upward docking of different encapsulation modules and downward docking of the PCIE drive module, convert information formed after encapsulation processing of the different encapsulation modules into information that can be recognized by the PCIE drive module, and does not need to substantially modify the existing encapsulation module.

In one possible implementation, the multiple virtual interfaces in the virtual interface module 113 have different priorities. When the processor 11 generates a plurality of second parameter sets by operating different encapsulation modules, the virtual interface module 113 may be operated, the PCIE adaptation layer 1132 may be operated according to priorities of virtual interfaces corresponding to the plurality of second parameter sets, and the second parameter sets received by the virtual interfaces are sequentially converted into third parameter sets according to a sequence from high priority to low priority, and the third parameter sets are sequentially processed. The above scheme enables the service corresponding to the virtual interface with the higher priority to be preferentially issued to the PCIE adaptation layer 1132 and the PCIE driver module 114 and to be preferentially processed. By adopting the above scheme, the processor 11 can operate the PCIE driver module 114 to drive the PCIE controller 12 to preferentially send the to-be-sent information generated by the encapsulation module corresponding to the virtual interface with the higher priority, so as to improve the quality of service (QOS) of the entire system. For example, for the emergency timing service in the service module 111, assuming that the processor 11 encapsulates the service operation data generated by operating the emergency timing service by operating the encapsulation module 1124, the virtual interface D in the virtual interface module 113 has the highest priority. The processor 11 runs the PCIE adaptation layer 1132, first converts the second parameter set received by the virtual interface D into a third parameter set, so that the PCIE driving module 114 can preferentially drive the PCIE controller 12 to send information to be sent corresponding to the emergency timing service according to the third parameter set.

In this embodiment, the information transmitted between the chip 1 and the chip 2 through the PCIE interface may be control plane information, including control information satisfying various control functions, or user plane data, such as various service data. For example, if the virtual interface is a virtual VCOM, it is used to transmit control plane information; if the virtual interface is a virtual VNIC, it is used to transfer user plane data. The control plane information may include control information generated by the encapsulation module, such as an AT command message or an OAM message generated by the encapsulation module, and the control information may be originated by the encapsulation module or may be generated after information originated by the service module is encapsulated by the encapsulation module. The user plane data includes various service data, i.e., various IP messages, generated by the encapsulation module and meeting the user use requirements, the IP messages are generated by the encapsulation module after IP encapsulation of the service data of the service module at the upper layer, and may include user data, such as various service data, such as game data, graphic data, video data, voice data, or communication data.

Correspondingly, taking the process of the chip 2 receiving the information sent by the chip 1 as an example, the architecture of the software running in the processor 21 is described, it should be understood that the process of the chip 1 receiving the information sent by the chip 2 is similar, and the description is omitted here.

The processor 21, by operating the PCIE driver module 214, determines a storage address of the information to be processed in the memory 2 after determining that the information to be processed (i.e., the second information) is received from the chip 1, and generates a fourth parameter group that satisfies the PCIE format, where the fourth parameter group includes the storage address of the information to be processed in the memory 2. The memory address of the information to be processed in the memory 2 may be obtained by the processor 21 by operating the PCIE driving module 214 to query the memory 2 according to a preset period, so as to determine that the information to be processed and the memory address of the information to be processed in the memory 2 are received in a period interval. By operating the PCIE driver module 214, after receiving the first trigger signal sent by the interrupt register 23, it is determined that the information to be processed is received, and actively query the interrupt message cached by the interrupt register 23, where the interrupt message is generated by the processor 11 by operating the PCIE driver module 114 according to the destination address of the information to be sent, and the processor 21 may determine the storage address of the information to be processed in the memory 2 according to the interrupt message.

The processor 21 generates a fifth parameter set satisfying the preset encapsulation format according to the fourth parameter set by operating the virtual interface module 213, where the fifth parameter set includes a storage address of the information to be processed in the memory 21. In a possible implementation manner, the processor 21 determines, by operating the PCIE adaptation layer 2132 in the virtual interface module 213, an address space in the memory 21 for storing the to-be-processed information according to the to-be-processed information in the fourth parameter set, so as to determine a virtual interface corresponding to the address space, and determines, according to the virtual interface, a preset encapsulation format of an encapsulation module corresponding to the virtual interface, so as to convert the fourth parameter set into a fifth parameter set meeting the preset encapsulation format of the encapsulation module, so that the fifth parameter set can be identified by the encapsulation module corresponding to the virtual interface. In the virtual interface module 213, a plurality of virtual interfaces (such as the virtual interfaces E, F, G and H in fig. 2) are included, and the plurality of virtual interfaces respectively correspond to a plurality of address spaces in the memory 2, as shown in fig. 4, and the chip 1 is similar. For example, in fig. 4, the virtual interface E corresponds to the address space 21, the processor 21 may determine the virtual interface E corresponding to the address space 21 by operating the virtual interface module 213, when determining the address space 21 in which the information to be processed is stored in the memory 2 according to the fourth parameter set, where the virtual interface E is a VNIC, the encapsulation module 2121 is a TCP/IP protocol stack, and the processor 21 converts the fourth parameter set into the fifth parameter set for operating the TCP/IP protocol stack by operating the virtual interface module 213. For another example, when the processor 21 determines the address space 22 stored in the memory 2 according to the fourth parameter set by operating the virtual interface module 213, it may determine the virtual interface F corresponding to the address space 22, where the virtual interface F is VCOM, the encapsulation module 2122 is the AT command handler, and the processor 21 converts the fourth parameter set into the fifth parameter set for operating the AT command handler by operating the virtual interface module 213.

After the processor 21 runs the encapsulation module corresponding to the virtual interface determined according to the storage address where the information to be processed is located, the encapsulation module is run to perform decapsulation processing on the information to be processed according to a preset decapsulation rule, so as to obtain data to be processed and generate a sixth parameter group, where the sixth parameter group can be identified by the service module 211. The processor 21 determines and processes the data to be processed from the memory 2 according to the storage address of the data to be processed in the sixth parameter by operating the service module 211. For example, the encapsulation module 2121 is a TCP/IP protocol stack, the information to be processed is an IP packet, when the chip 2 is a communication chip, the encapsulation module 2121 may forward the IP packet to a 4G or 5G air interface communication program in the service module 211, and the processor 21 determines the IP packet from the memory 2 according to the sixth parameter group by operating the 4G or 5G air interface communication program in the service module 211, encapsulates the IP packet into an air interface packet conforming to the 4G or 5G air interface communication protocol, converts the air interface packet into a wireless signal, and sends the wireless signal through the antenna. When the chip 2 is an application chip, the processor 21 may perform decapsulation, merging, and other operations on the IP packet according to the TCP/IP protocol by operating the encapsulation module 2121, so as to obtain to-be-processed data, and then the processor 21 processes the to-be-processed data according to the sixth parameter group by operating the application program in the service module 211. For another example, the encapsulating module 2122 is an AT command processing program, the information to be processed is an AT command message, and the processor 21, by running the encapsulating module 2122, may determine the type of the AT command message according to the format of the AT command message, so as to send the type of the AT command message to the corresponding program in the service module 211 to execute the AT command message.

In the above embodiments, the software modules that can be executed by the processor, such as the service module, the encapsulation module, the virtual interface module, and the PCIE driver module, can be implemented wholly or partially by configurable software, firmware, or any combination thereof, and it is understood that the firmware is also a special software. When any of the modules is implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The procedures or functions according to embodiments of the invention are generated in whole or in part when the computer program instructions are loaded and executed on a computer or a processor of the embodiments. The computer or processor may be equivalently a general purpose computer, special purpose computer, network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium, such as the memory mentioned in the previous embodiments, or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

The present application is described with reference to block diagrams of apparatus (systems), and computer program products according to the present application. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the block or blocks of the block diagrams.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

A Peripheral Component Interconnect Express (PCIE) sending device is characterized by comprising:

the packaging module is used for generating first information to be sent and a second parameter group meeting a preset packaging format according to a preset packaging rule; the second parameter group comprises a storage address of the first information in a first memory corresponding to the PCIE transmitting apparatus;

the virtual interface module is configured to receive the second parameter group from the encapsulation module, and generate a third parameter group that satisfies a PCIE format according to the second parameter group, where the third parameter group includes the storage address and a destination address in a second memory corresponding to the PCIE receiving apparatus;

a PCIE driver module, configured to receive the third parameter set from the virtual interface module, analyze the third parameter set to obtain the storage address and the destination address, and send a first instruction used to drive the first PCIE controller to send the first information to a first PCIE controller corresponding to the PCIE sending device, where the first instruction includes the destination address, and the first instruction further includes the first information or a storage address of the first information in the first memory.
The PCIE transmitting apparatus of claim 1, wherein the virtual interface module comprises a virtual interface and a PCIE adaptation layer;

the virtual interface corresponds to the encapsulation module, and is configured to receive the second parameter set from the encapsulation module and provide the second parameter set to the PCIE adaptation layer;

the PCIE adaptation layer is configured to determine an address space corresponding to the virtual interface in the second memory, determine the destination address according to the address space, and generate the third parameter group meeting the PCIE format according to the second parameter group and the destination address.
The PCIE transmit apparatus of claim 2, wherein the virtual interface is a virtual network interface adapter VNIC or a virtual serial communication port VCOM.
The PCIE transmitter apparatus of claim 2 or 3, wherein the apparatus comprises a plurality of encapsulation modules, and the virtual interface module comprises a plurality of virtual interfaces; each virtual interface corresponds to one encapsulation module, and each virtual interface has a priority;

the PCIE adaptation layer is specifically configured to: and obtaining a processing sequence of the plurality of virtual interfaces according to the priorities of the plurality of virtual interfaces, and sequentially generating the third parameter group corresponding to each virtual interface according to the processing sequence.
The PCIE transmitter apparatus of any one of claims 1 to 4, further comprising:

the business module is used for generating business operation data in the first memory;

the encapsulation module is specifically configured to encapsulate the service operation data according to the preset encapsulation rule to generate the first information and the second parameter group corresponding to the type of the service operation data.
The PCIE transmitter according to any one of claims 1 to 5, wherein the encapsulation module is a transmission control protocol/internet protocol TCP/IP stack encapsulation module, or an AT command handler encapsulation module, or an operation, administration, and maintenance OAM detection handler encapsulation module.
A Peripheral Component Interconnect Express (PCIE) receiving device is characterized by comprising:

the PCIE driving module is configured to determine a storage address of second information to be processed in a second memory corresponding to the PCIE receiving apparatus, and generate a fourth parameter group meeting a PCIE format, where the fourth parameter group includes the storage address;

the virtual interface module is configured to receive the fourth parameter group from the PCIE driver module, and generate a fifth parameter group that satisfies a preset encapsulation format according to the fourth parameter group; the fifth parameter set comprises the storage address;

and the encapsulation module is configured to receive the fifth parameter group from the virtual interface module, analyze the fifth parameter group to obtain the storage address, obtain the second information according to the storage address, and decapsulate the second information according to a preset decapsulation rule to generate to-be-processed data.
The PCIE receiving apparatus of claim 7, wherein the virtual interface module comprises a virtual interface and a PCIE adaptation layer;

the PCIE adaptation layer is configured to receive the fourth parameter group from the PCIE driver module, and determine an address space corresponding to the storage address according to the fourth parameter group; determining the virtual interface corresponding to the address space; determining the preset packaging format of a packaging module corresponding to the virtual interface; generating a fifth parameter group meeting the preset packaging format according to the fourth parameter group, and providing the fifth parameter group for the virtual interface;

the virtual interface corresponds to the encapsulation module, and is configured to receive the fifth parameter set provided by the PCIE adaptation layer and send the fifth parameter set to the encapsulation module.
The PCIE receiving apparatus of claim 8, wherein the virtual interface is a virtual network interface adapter VNIC or a virtual serial communication port VCOM.
The PCIE receiver of any one of claims 7 to 9, wherein:

the encapsulation module is specifically configured to perform decapsulation processing on the second information according to a preset decapsulation rule to generate to-be-processed data corresponding to the type of the encapsulation module;

the PCIE receiving apparatus further includes a service module, configured to process the to-be-processed data.
The PCIE receiver of any one of claims 7 to 10, wherein the encapsulation module is a transmission control protocol/internet protocol TCP/IP stack encapsulation module, or an AT command handler encapsulation module, or an operation, administration, and maintenance OAM detection handler encapsulation module.
A Peripheral Component Interconnect Express (PCIE) sending method is characterized by comprising the following steps:

generating first information to be sent and a second parameter group meeting a preset packaging format by using a packaging module according to a preset packaging rule; the second parameter group comprises a storage address of the first information in a first memory corresponding to the PCIE transmitting apparatus;

generating a third parameter group meeting the PCIE format according to the second parameter group by utilizing a virtual interface module, wherein the third parameter group comprises the storage address and a destination address in a second memory corresponding to the PCIE receiving device;

analyzing the third parameter group by using a PCIE driver module to obtain the storage address and the destination address, and sending a first instruction for driving the first PCIE controller to send the first information to a first PCIE controller corresponding to the PCIE sending device, where the first instruction includes the destination address, and the first instruction further includes the first information or a storage address of the first information in the first memory.
The PCIE transmission method of claim 12, wherein the virtual interface module comprises a virtual interface and a PCIE adaptation layer;

the generating, by the virtual interface module, a third parameter set that satisfies the PCIE format according to the second parameter set includes:

receiving the second parameter group from the encapsulation module by using the virtual interface, and providing the second parameter group to the PCIE adaptation layer;

and determining an address space corresponding to the virtual interface in the second memory by using the PCIE adaptation layer, determining the destination address according to the address space, and generating the third parameter group meeting the PCIE format according to the second parameter group and the destination address.
The PCIE transmission method of claim 13, wherein the virtual interface is a virtual network interface adapter VNIC, and/or a virtual serial communication port VCOM.
The PCIE transmission method according to claim 13 or 14, wherein the PCIE transmission apparatus includes a plurality of encapsulation modules, and the virtual interface module includes a plurality of virtual interfaces; each virtual interface corresponds to one encapsulation module, and each virtual interface has a priority;

generating the third parameter group meeting the PCIE format according to the second parameter and the destination address, including:

and obtaining a processing sequence of the plurality of virtual interfaces by using the PCIE adaptation layer according to the priorities of the plurality of virtual interfaces, and sequentially generating the third parameter group corresponding to each virtual interface according to the processing sequence.
A Peripheral Component Interconnect Express (PCIE) receiving method is characterized by comprising the following steps:

determining a storage address of second information to be processed in a second memory corresponding to a PCIE receiving device by using a PCIE driving module, and generating a fourth parameter group meeting the PCIE format, wherein the fourth parameter group comprises the storage address;

receiving the fourth parameter group from the PCIE driving module by using a virtual interface module, and generating a fifth parameter group meeting a preset packaging format according to the fourth parameter group; the fifth parameter set comprises the storage address;

and receiving the fifth parameter group by using an encapsulation module, analyzing the fifth parameter group to obtain the storage address, acquiring the second information according to the storage address, and decapsulating the second information according to a preset decapsulation rule to generate data to be processed.
The PCIE receiving method of claim 16, wherein the virtual interface module comprises a virtual interface and a PCIE adaptation layer;

generating a fifth parameter group meeting the identification format of the packaging module by using a virtual interface module according to the storage address of the second information, wherein the fifth parameter group comprises:

receiving the fourth parameter group from the PCIE driving module by utilizing the PCIE adaptation layer, and determining an address space corresponding to the storage address according to the fourth parameter group; determining the virtual interface corresponding to the address space; determining a preset packaging format of a packaging module corresponding to the virtual interface; generating a fifth parameter group meeting the preset packaging format according to the fourth parameter group, and providing the fifth parameter group for the virtual interface;

and receiving the fifth parameter group provided by the PCIE adaptation layer by using the virtual interface, and sending the fifth parameter group to the encapsulation module.
The PCIE receiving method of claim 17, wherein the virtual interface is a virtual network interface adapter VNIC or a virtual serial communication port VCOM.
A Peripheral Component Interconnect Express (PCIE) sending device comprises a processor and a first PCIE controller, and is characterized in that the processor is used for:

operating a packaging module to generate first information to be sent and a second parameter group meeting a preset packaging format according to a preset packaging rule; the second parameter group comprises a storage address of the first information in a first memory corresponding to the PCIE sending device; generating a third parameter group meeting the PCIE format according to the second parameter group by operating a virtual interface module, wherein the third parameter group comprises the storage address and a destination address in a second memory corresponding to the PCIE receiving equipment; analyzing the third parameter group to obtain the storage address and the destination address by operating a PCIE driver module, and sending a first instruction for driving the first PCIE controller to send the first information to the first PCIE controller, where the first instruction includes the destination address, and the first instruction further includes the first information or a storage address of the first information in the first memory;

the first PCIE controller is configured to receive the first instruction, acquire the first information from the first instruction, or acquire the first information from the first memory according to the storage address in the first instruction, and send the first information to a second PCIE controller corresponding to the PCIE receiving device.
The PCIE transmitter of claim 19, wherein the PCIE transmitter is a root complex, the processor is further configured to: operating the PCIE driving module to generate an interrupt message according to the destination address and sending the interrupt message to the first PCIE controller;

the first PCIE controller is further configured to send the interrupt message to the second PCIE controller.
A peripheral device high-speed interconnection PCIE receiving device is characterized by comprising a processor and a second PCIE controller;

the second PCIE controller is configured to receive second information sent by the first PCIE controller corresponding to the PCIE sending device, and store the second information in the second memory corresponding to the PCIE receiving device according to a destination address corresponding to the second information;

the processor is configured to operate the PCIE driver module to determine a storage address of the second information in the second memory, and generate a fourth parameter group meeting the PCIE format, where the fourth parameter group includes the storage address; the virtual interface module is operated to receive the fourth parameter group from the PCIE driving module, and a fifth parameter group meeting a preset packaging format is generated according to the fourth parameter group; the fifth parameter set comprises the storage address; and operating an encapsulation module to receive the fifth parameter group, analyze the fifth parameter group to obtain the storage address, obtain the second information according to the storage address, and decapsulate the second information according to a preset decapsulation rule to generate data to be processed.
The PCIE receiver of claim 21, wherein the PCIE receiver is an endpoint, the PCIE receiver further comprises an interrupt register respectively connected to the second PCIE controller and the processor;

the second PCIE controller is further configured to receive an interrupt message sent by the first PCIE controller, and store the interrupt message in the interrupt register;

the interrupt register is used for caching the interrupt message and sending a first trigger signal to the processor;

the processor is further configured to determine, after receiving the first trigger signal, a storage address in the second memory for storing the second information according to the interrupt message in the interrupt register.
A PCIE system for peripheral component interconnect express, comprising a PCIE transmitter device according to claim 19 or claim 20 and/or a PCIE receiver device according to claim 21 or claim 22.