WO2020000489A1

WO2020000489A1 - Pcie sending and receiving method, apparatus, device and system

Info

Publication number: WO2020000489A1
Application number: PCT/CN2018/093927
Authority: WO
Inventors: 曹雷; 孙学全; 赵阳
Original assignee: 华为技术有限公司
Priority date: 2018-06-30
Filing date: 2018-06-30
Publication date: 2020-01-02
Also published as: CN111656336B; CN111656336A

Abstract

Provided are a PCIE sending and receiving method, apparatus, device and system, for realizing usage of a PCIE controller without significantly changing existing software architecture, wherein the PCIE sending apparatus comprises: an encapsulation module for generating first information and a second parameter set; a virtual interface module for receiving the second parameter set from the encapsulation module, and generating, according to the second parameter set, a third parameter set which satisfies a PCIE format, wherein the third parameter set comprises a storage address and a destination address in a second memory corresponding to a PCIE receiving apparatus; and a PCIE drive module for receiving the third parameter set from the virtual interface module, and driving, according to the third parameter set, a first PCIE controller to send the first information. The virtual interface module serves the function of linking between the encapsulation module and the PCIE drive module, so that even if the encapsulation module is not adaptively adjusted, sending of a PCIE can still be realized.

Description

Method and device for transmitting and receiving PCIE, device and system

Technical field

The present invention relates to the field of electronic science and technology, and in particular, to a PCIE sending and receiving method and device, device, and system.

Background technique

With the development of electronic technology and the growth of user needs, terminal devices need to be able to implement more and more functions. In order to realize these functions, terminal devices often need to include many chips. Many chips of the terminal equipment need to be interconnected for data transmission, so that the terminal equipment can realize corresponding functions. In existing terminal equipment, chips can be interconnected in various ways. For example, a modem communication chip and an application (APP) chip in a terminal device can be connected through a universal serial bus. (universal serial bus, USB) port or Gigabit Ethernet media access control (GMAC) network card interconnection.

In 5G technology, the downlink rate of the wireless air interface side can reach 10Gbps or more, while the transmission rate of the GMAC port is only 1Gbps, and the transmission rate of the USB3.0 port can only theoretically reach 5Gbps, and the measured performance will also decrease. As a result, the chip interconnection method of GMAC network card or USB port will be difficult to meet the requirements of 5G technology, and peripheral component high-speed interconnection (PCIE) due to its high transmission rate, which further improves the transmission efficiency between chips. It becomes possible, so it is one of the important research directions of the interconnection scheme between chips in 5G technology.

However, if the chips are to be interconnected by PCIE, multiple packaging modules in the software running on the chip processor are usually required (for example, to add a packet header to the running data so that it conforms to the protocol stack specified by the transmission protocol, and for dialing Specially designed with AT command processing program that configures modems, operation, management, and maintenance (OAM) functions for obtaining maintenance information, etc.) so that these packaging modules can be adapted to The PCIE driver module enables the processor to pass the information generated by running these packaged modules through the PCIE controller running the PCIE driver module driver chip. This software modification is more complicated and prevents the PCIE interconnection from being based on existing software. Further use of the chip in the architecture, therefore, there is an urgent need for a solution that can simplify the design of the PCIE interconnection between the chips, without the need to significantly change the existing software architecture, the existing chip can use the PCIE controller.

Summary of the invention

The embodiments of the present application provide a method and device for transmitting and receiving a PCIE, a device, and a system, so as to support a PCIE interface without substantially changing an existing software architecture.

In a first aspect, an embodiment of the present application provides a high-speed interconnection PCIE transmission device for peripheral devices, including a packaging module, a virtual interface module, and a PCIE driver module. The encapsulation module is configured to generate first information to be transmitted and a second parameter group that satisfies a preset encapsulation format according to a preset encapsulation rule. The second parameter group includes the first information corresponding to the PCIE sending device. A storage address in the first memory; a virtual interface module for receiving a second parameter group from the encapsulation module, and generating a third parameter group that meets the PCIE format according to the second parameter group, the third parameter group including the foregoing storage address and the The destination address in the second memory corresponding to the PCIE receiving device; the PCIE driver module is configured to receive a third parameter group from the virtual interface module, parse the third parameter group to obtain the foregoing storage address and destination address, and send the device address to the PCIE device. The corresponding first PCIE controller sends a first instruction, and the first instruction is used to drive the first PCIE controller to send the first information. The first instruction includes the foregoing destination address, and further includes the first information or a storage address of the first information in the first memory.

With the above solution, the virtual interface module can receive the second parameter group that meets the preset packaging format generated by the packaging module, and convert the second parameter group into a third parameter group that can be recognized and received by the PCIE driver module. The PCIE drive modules play a role of undertaking, so that even if the software structure of the packaging module is not adjusted according to the PCIE drive module, PCIE transmission can be realized. Compared with changing the open source and general-purpose packaging module, using the above-mentioned method to add a virtual interface module to the PCIE transmission device will bring much less design, thereby realizing that the existing software architecture can be made without substantially changing the existing software architecture. Some chips can support PCIE interface.

Based on the above first aspect, in a possible implementation manner, the virtual interface module includes a virtual interface and a PCIE adaptation layer. The virtual interface corresponds to the packaging module and is used to receive the second parameter group from the corresponding packaging module and provide it to the PCIE adaptation layer; the PCIE adaptation layer is used to determine the second memory and provide the second parameter to it. An address space corresponding to the virtual interface of the group, a destination address is determined according to the address space, and a third parameter group that meets the PCIE format is generated according to the second parameter group and the destination address.

With the above solution, the virtual interface is adapted upward to the corresponding packaging module, and the second parameter group provided by the packaging module is received, and the PCIE adaptation layer is downward adapted to the PCIE driver module, and the virtual interface and the address space in the second memory are The corresponding relationship determines the destination address, and generates a third parameter group that can be recognized and received by the PCIE driver module according to the second parameter and the destination address, thereby realizing the role of the virtual interface module between the encapsulation module and the PCIE driver module.

Based on the first aspect, in a possible implementation manner, the virtual interface is a virtual network interface adapter VNIC or a virtual serial communication port VCOM.

Based on the above first aspect, in a possible implementation manner, the PCIE sending device includes multiple packaging modules, and the virtual interface module of the PCIE sending device includes multiple virtual interfaces; each virtual interface corresponds to one packaging module, And each virtual interface has a priority; the PCIE adaptation layer is specifically used to: obtain the processing order of multiple virtual interfaces according to the priorities of multiple virtual interfaces, and sequentially generate a third parameter corresponding to each virtual interface in accordance with the processing order. group.

By adopting the above scheme, services corresponding to a virtual interface with a higher priority can be preferentially delivered to the PCIE adaptation layer and the PCIE driver module and processed preferentially, so that the processor runs the PCIE driver module to drive the PCIE controller to send priority priority. Information to be sent corresponding to a higher service, thereby improving the overall quality of service (QOS) of the system.

Based on the above first aspect, in a possible implementation manner, the PCIE sending device further includes: a service module, configured to generate service running data in the first memory; based on this, the above-mentioned encapsulation module is specifically configured to perform a preset operation according to a preset The encapsulation rule performs encapsulation processing on the business operation data to generate first information and a second parameter group corresponding to the type of the business operation data.

Based on the above first aspect, in a possible implementation manner, the packaging module in the PCIE sending device is a transmission control protocol / network interconnection protocol TCP / IP protocol stack packaging module, or an AT command processing program packaging module, or an operation, Manage and maintain OAM inspection program package modules.

In a second aspect, an embodiment of the present application provides a high-speed interconnection PCIE receiving device for peripheral devices, including: a PCIE driver module, a virtual interface module, and a packaging module. The PCIE driver module is configured to determine a storage address of the second information to be processed in a second memory corresponding to the PCIE receiving device, and generate a fourth parameter group that meets the PCIE format, where the fourth parameter group includes the foregoing storage address; virtual An interface module is configured to receive the fourth parameter group from the PCIE driver module, and generate a fifth parameter group that satisfies a preset encapsulation format according to the fourth parameter group; the fifth parameter group includes the foregoing storage address; The virtual interface module receives the fifth parameter group, parses the fifth parameter group to obtain the foregoing storage address, and obtains the second information according to the foregoing storage address, and decapsulates the second information according to a preset decapsulation rule to generate a to-be-processed data.

With the above solution, the virtual interface module can receive the fourth parameter group generated by the PCIE driver module, and convert the fourth parameter group into a fifth parameter group that can be recognized and received by the packaging module, which starts between the PCIE driver module and the packaging module. With the role of undertaking, even if the software structure of the packaging module is not adjusted according to the PCIE driver module, PCIE reception can be achieved. Compared with changing the open source and general-purpose packaging module, using the above method to add a virtual interface module to the PCIE receiving device will bring much less design, thus realizing that the existing software architecture can be made without substantially changing the existing software architecture. Some chips can support PCIE interface.

Based on the second aspect, in a possible implementation manner, the virtual interface module includes a virtual interface and a PCIE adaptation layer. The PCIE adaptation layer is used to receive a fourth parameter group from the PCIE driver module, and determine an address space corresponding to the storage address according to the fourth parameter group; determine a virtual interface corresponding to the address space; determine a packaging module corresponding to the virtual interface A predetermined package format according to the fourth parameter group; a fifth parameter group that satisfies the preset package format is generated according to the fourth parameter group, and the fifth parameter group is provided to a virtual interface; the virtual interface corresponds to the packaging module and is used to receive PCIE adaptation The fifth parameter group provided by the layer, and sends the fifth parameter group to the encapsulation module.

By adopting the above scheme, the PCIE adaptation layer adapts the PCIE driver module, determines the virtual interface corresponding to the second information through the correspondence between the address space and the virtual interface in the second memory, and uses the correspondence between the virtual interface and the encapsulation module. The encapsulation format of the fifth parameter group is determined, so that the fourth parameter group is converted into a fifth parameter group that the encapsulation module can recognize and receive. The virtual interface is adapted to the corresponding packaging module, and a fifth parameter group is provided to the packaging module. The virtual interface module and the PCIE adaptation layer realize the role of the virtual interface module between the packaging module and the PCIE driver module.

Based on the second aspect, in a possible implementation manner, the virtual interface is a virtual network interface adapter VNIC or a virtual serial communication port VCOM.

Based on the second aspect described above, in a possible implementation manner, the encapsulation module is specifically configured to perform decapsulation processing on the second information according to a preset decapsulation rule to generate data to be processed corresponding to the type of the encapsulation module; The PCIE receiving device further includes a service module, and the service module is configured to process the data to be processed generated by the encapsulation module.

Based on the above second aspect, in a possible implementation manner, the packaging module in the PCIE receiving device is a transmission control protocol / network interconnection protocol TCP / IP protocol stack packaging module, or an AT command processing program packaging module, or an operation, Manage and maintain OAM inspection program package modules.

In a third aspect, an embodiment of the present application provides a high-speed interconnect PCIE transmission method for a peripheral device, including: using a packaging module to generate first information to be sent and a second parameter group that satisfies a preset packaging format according to a preset packaging rule; The second parameter group includes a storage address of the first information in the first memory corresponding to the PCIE transmitting device; and a third parameter group that meets the PCIE format is generated according to the second parameter group by using the virtual interface module, and the third parameter group includes the foregoing storage. The address and the destination address in the second memory corresponding to the PCIE receiving device; using the PCIE driver module to parse the third parameter group to obtain the storage address and the destination address, and sending it to the first PCIE controller corresponding to the PCIE transmitting device for A first instruction that drives the first PCIE controller to send first information, the first instruction includes a destination address, and the first instruction further includes the first information or a storage address of the first information in the first memory.

Based on the third aspect described above, in a possible implementation manner, the virtual interface module includes a virtual interface and a PCIE adaptation layer; using the virtual interface module to generate a third parameter group that meets the PCIE format according to the second parameter group includes: using virtual The interface receives the second parameter group from the encapsulation module and provides it to the PCIE adaptation layer; using the PCIE adaptation layer to determine an address space corresponding to the virtual interface in the second memory, and determining a destination address of the first information according to the address space, Generating the third parameter group that meets the PCIE format according to the second parameter and the destination address.

Based on the third aspect, in a possible implementation manner, the virtual interface is a virtual network interface adapter VNIC, and / or, a virtual serial communication port VCOM.

Based on the above third aspect, in a possible implementation manner, the PCIE sending device includes multiple encapsulation modules, and the virtual interface module includes multiple virtual interfaces; each virtual interface corresponds to one encapsulation module, and each virtual interface The interface has a priority; and generating the third parameter group that meets the PCIE format according to the second parameter and the destination address includes: using the PCIE adaptation layer to obtain a to-many according to the priorities of the multiple virtual interfaces For the processing order of each virtual interface, the third parameter group corresponding to each virtual interface is sequentially generated according to the processing order.

According to a fourth aspect, an embodiment of the present application provides a PCIE receiving method for high-speed interconnection of peripheral devices, which includes: using a PCIE driver module to determine a storage address of the second information to be processed in a second memory corresponding to the PCIE receiving device, and generating a PCIE satisfying PCIE A fourth parameter group of the format, the fourth parameter group including the storage address; and thereafter, using a virtual interface module to receive the fourth parameter group from the PCIE drive module, and generating a satisfying preset according to the fourth parameter group A fifth parameter group in an encapsulated format; the fifth parameter group includes the storage address; and then, receiving the fifth parameter group by using an encapsulation module, parsing the fifth parameter group to obtain the storage address, and The storage address obtains the second information, and generates the data to be processed after decapsulating the second information according to a preset decapsulation rule.

Based on the fourth aspect, in a possible implementation manner, the virtual interface module includes a virtual interface and a PCIE adaptation layer; and a virtual interface module is used to generate a fifth that satisfies the identification format of the encapsulation module according to the storage address of the second information. A parameter group includes: using the PCIE adaptation layer to receive the fourth parameter group from the PCIE driver module, and determining an address space corresponding to the storage address according to the fourth parameter group; and determining to correspond to the address space Determine the preset packaging format of the packaging module corresponding to the virtual interface; generate a fifth parameter group that satisfies the preset packaging format according to the fourth parameter group, and set the fifth parameter group Provided to the virtual interface; using the virtual interface, receiving the fifth parameter group provided by the PCIE adaptation layer, and sending the fifth parameter group to the encapsulation module.

Based on the fourth aspect, in a possible implementation manner, the virtual interface is a virtual network interface adapter VNIC or a virtual serial communication port VCOM.

In a fifth aspect, the present application provides a peripheral device high-speed interconnected PCIE transmission device, including a processor and a first PCIE controller. The processor is configured to: run a packaging module to generate first information to be sent according to a preset packaging rule and satisfy A second parameter group in a preset encapsulation format; the second parameter group includes a storage address of the first information in a first memory corresponding to the PCIE sending device; and a virtual interface module is run according to the second parameter The group generates a third parameter group that meets the PCIE format. The third parameter group includes the storage address and a destination address in a second memory corresponding to the PCIE receiving device. The third parameter group is parsed by running a PCIE driver module. To obtain the storage address and the destination address, and send a first instruction for driving the first PCIE controller to send the first information to the first PCIE controller, where the first instruction includes the A destination address, and the first instruction further includes the first information or a storage address of the first information in the first memory; the first PCIE control A device for receiving the first instruction, obtaining the first information from the first instruction, or obtaining the first information from the first memory according to the storage address in the first instruction And sending the first information to a second PCIE controller corresponding to the PCIE receiving device.

Based on the fifth aspect, in a possible implementation manner, the PCIE sending device is a root complex, and the processor is further configured to: run a PCIE driver module to generate an interrupt message according to the destination address and send the interrupt message to the A first PCIE controller; the first PCIE controller is further configured to send the interrupt message to the second PCIE controller.

In the existing PCIE, the device that is the root complex lacks an interrupt mechanism in the process of sending information to the endpoint device, so that after receiving the information sent by the root complex device, the endpoint device cannot determine and process the information sent by the root complex. When the PCIE sending device is a root complex, this application also sends interrupt information, so that the corresponding PCIE receiving device as the endpoint device can determine and process the information sent by the PCIE sending device through the interrupt message.

According to a sixth aspect, an embodiment of the present application provides a high-speed peripheral PCIE receiving device including a processor and a second PCIE controller. The second PCIE controller is configured to receive a first PCIE corresponding to a PCIE transmitting device. The second information sent by the controller, and storing the second information into the second memory corresponding to the PCIE receiving device according to the destination address corresponding to the second information; the processor, configured to run the PCIE driver module to determine The storage address of the second information in the second memory generates a fourth parameter group that meets the PCIE format, where the fourth parameter group includes the storage address; the running virtual interface module receives all the information from the PCIE driver module. The fourth parameter group generates a fifth parameter group that satisfies a preset package format according to the fourth parameter group; the fifth parameter group includes the storage address; and the operation packaging module receives the fifth parameter group and analyzes the The fifth parameter group to obtain the storage address, and obtain the second information according to the storage address, and decapsulate the second information according to a preset decapsulation rule Generating data to be processed.

Based on the sixth aspect, in a possible implementation manner, the PCIE receiving device is an endpoint, and the PCIE receiving device further includes an interrupt register connected to the second PCIE controller and the processor, respectively; The second PCIE controller is further configured to receive an interrupt message sent by the first PCIE controller, and store the interrupt message in the interrupt register; the interrupt register is used to buffer the interrupt message, and Sending a first trigger signal to the processor; the processor is further configured to, after receiving the first trigger signal, determine, according to the interrupt message in the interrupt register, that the second memory is configured for: A storage address where the second information is stored.

With the above solution, by adding an interrupt register to the PCIE receiving device as the endpoint device, an interrupt mechanism is added to the process of the endpoint device receiving the information sent by the root complex device, so that the PCIE receiving device as the endpoint device can determine and process it as the root device. Information sent by the complex PCIE sending device.

In a seventh aspect, an embodiment of the present invention provides a high-speed interconnected PCIE system for peripheral devices. The PCIE system includes the PCIE transmitting device according to the foregoing fifth aspect, and / or the PCIE receiving device according to the foregoing sixth aspect.

According to an eighth aspect, a computer-readable storage medium is provided for storing a computer program. The computer program includes a method for executing any one of the third aspect, the fourth aspect, the third aspect, or the fourth aspect. Instructions for any of the possible implementations of the method.

In a ninth aspect, a computer program product is provided. The computer program product includes: computer program code that, when the computer program code runs on a computer or a processor, causes the computer or processor to execute the third aspect. , The fourth aspect, the method in any one of the possible implementation manners in the third aspect or the fourth aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to explain the technical solutions in the embodiments of the present invention more clearly, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. Those of ordinary skill in the art can obtain other drawings based on these drawings without paying creative labor.

FIG. 1 is a schematic diagram of a PCIE interconnection system according to an embodiment of the present application;

2 is a schematic diagram of a software architecture run by a processor according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an address space mapping relationship of a memory of a PCIE device at two ends according to an embodiment of the present application; FIG.

FIG. 4 is a schematic diagram of a correspondence relationship between a virtual interface and an address space according to an embodiment of the present application.

detailed description

The embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a PCIE interconnection system according to an embodiment of the present application. As shown in FIG. 1, chip 1 includes a processor 11 and a PCIE controller 12, and chip 2 includes a processor 21 and a PCIE controller 22. It is connected to the PCIE controller 22 through a PCIE physical connection. In addition, the chip 1 is also connected to the memory 1. The processor 11 in the chip 1 processes the data in the memory 1 by running software. The software run by the processor 11 may also be stored in the memory 1 or other memories coupled with the chip 1. . The chip 2 is also connected to the memory 2. The processor 21 in the chip 2 processes data in the memory 2 by running software, and the software running by the processor 12 may also be stored in the memory 2 or other memory coupled with the chip 2. Each of the above memories may include multiple different types of memories, which are used to implement different storage capabilities, such as storing different data or software codes. The memory may include at least one of volatile memory or non-volatile memory.

In the PCIE interconnection system shown in FIG. 1, chip 1 serves as the root complex in the PCIE interconnection, and chip 2 serves as the end point in the PCIE interconnection. In the existing PCIE protocol, there is a lack of a mechanism that triggers chip 2 as an endpoint to determine that it has received the information sent by chip 1 and to process the information in memory 2. Based on this, in a feasible implementation manner, the processor 21 of the chip 2 in this embodiment may periodically query the memory 2 according to a preset periodic interval to confirm whether the information sent by the chip 1 is received within the periodic interval. If it is determined that the information sent by the chip 1 is received within the periodic interval, the storage address of the received information sent by the chip 1 in the memory 2 can be confirmed, and the information can be processed.

In another feasible alternative implementation manner, as shown in FIG. 1, the chip 2 further includes an interrupt register 23 respectively connected to the processor 21 and the PCIE controller 22. After the chip 1 sends the information to be sent to the chip 2, it also sends an interrupt message to the chip 2 through the PCIE controller 12. The interrupt message is determined by the processor 11 according to the destination address of the information to be sent in the memory 2. of. After receiving the interrupt message, the PCIE controller 22 of the chip 2 buffers the interrupt message in the interrupt register 23. After the interrupt register 23 stores the interrupt message, it sends a first trigger signal to the processor 21, so that after receiving the first trigger signal, the processor 21 actively queries the interrupt message buffered by the interrupt register 23 and determines the received message according to the interrupt message. The storage address of the received information in the memory 2, so that the information received from the chip 1 can be obtained from the memory 2, and the information is processed.

Because chip 1 and chip 2 are interconnected through the PCIE controller (12, 22), the PCIE controller (12, 22) needs to be driven by the PCIE driver module, so the

processors

11 and 11 in the existing non-PCIE interconnected system need to be driven. The architecture of the software running by the processor 21 is adjusted. Based on this, the embodiment of the present application provides a software architecture capable of driving a processor to work, which can enable an existing chip to use a PCIE controller without substantially changing an existing software architecture that does not support PCIE interconnection. FIG. 2 provides a schematic diagram of software running on the internal processor of chip 1 and chip 2 on the basis of the PCIE interconnection system shown in FIG. 1. As shown in Figure 2, the software architectures run by the

processors

11 and 12 include business modules (111, 211), multiple packaging modules, virtual interface modules (113, 213), and PCIE driver modules (114, 214). ), Wherein the packaging module, the virtual interface module (113, 213) and the PCIE driver module (114, 214) may be included in the kernel of the operating system in the processor 11 and the processor 12, as shown by the dotted line in FIG. 2 It is shown that the cores of the processor 11 and the processor 12 may be a Linux kernel, a real-time operating system (RTOS) kernel, and other types.

Next, taking the process of sending information from chip 1 to chip 2 as an example, the architecture of the software running in processor 11 is introduced. It should be understood that the process of sending information from chip 2 to chip 1 is similar, and this application is no longer One by one. The software architecture that the processor 11 runs on, for example, the operating system or its kernel may include a service module 111, a packaging module (1121, 1122, 1123, 1124), a virtual interface module 113, and a PCIE driver module 114. Therefore, the software architecture can exist in the form of a computer program, which enables information or data processing when the program is executed by a processor or a computer.

The processor 11 generates service running data in the memory 1 by running the service module 111 in the software architecture. The specific implementation of the service module 111 is related to the type of the chip 1. For example, when the chip 1 is an application chip, the service module 111 includes various application programs, such as a WeChat client, a Baidu client, and the like. The processor 11 generates service operation data in the memory 1 by running the application program in the service module 111. As another example, when the chip 1 is a communications chip, a communication service module 111 includes various types of procedures, e.g., 4G (fourth generation, 4 ^th Generation) or. 5G (fifth generation, 5 ^th Generation) air interface communication program, the communication chip After the wireless antenna receives the wireless signal, the processor 11 runs the 4G or 5G air interface communication program to demodulate the received wireless signal to obtain the received air interface message that conforms to the air interface protocol, parses the air interface message, obtains the IP message and The IP message is stored in the memory 1 as service operation data.

The architecture of the software run by the processor 11 includes a plurality of packaging modules (such as the packaging modules 1121, 1122, 1123, and 1124 in FIG. 2). The processor 11 runs different types of packaging modules, and can be configured according to different packaging rules. The service operation data is subjected to different encapsulation processing, so as to obtain different types of information to be transmitted, that is, the first information. Each type of information to be transmitted has a data format corresponding to the type. For example, the encapsulation module 1121 may be a transmission control protocol / Internet Protocol (TCP / IP) protocol stack encapsulation module. When chip 1 is an application chip, the processor 11 runs the encapsulation module 1121 to run services. The data is divided into data, and a message header is added, so that the service operation data is encapsulated in the memory 1 as an IP message including a destination IP address. For another example, the encapsulation module 1122 may be an AT command processing program encapsulation module. When the service operation data obtained by the processor 11 by running the service module 111 is AT command data, the processor 11 runs the encapsulation module 1122 and may be generated according to the AT command data. AT command messages. There are various types of AT command messages, such as configuration commands and query commands. The AT commands generated by the processor 11 running the encapsulation module 1122 have multiple formats. AT command messages of different formats correspond to different types of AT command messages. . For another example, the encapsulation module 1123 may be an OAM detection program encapsulation module. When the service operation data obtained by the processor 11 by running the service module 111 is OAM detection data, the processor 11 runs the encapsulation module 1123 to generate an OAM according to the OAM detection data. Detect messages, and so on.

After the processor 11 generates service running data in the memory 1, the running service module 111 may further generate a first parameter group, and the first parameter group may include parameters such as a storage address and a data length of the service running data. After generating the first parameter group, the processor 11 continues to run the encapsulation module corresponding to the type of service operation data. For example, when the type of service operation data is communication data, the encapsulation module 1121 is run to encapsulate the service operation data into an IP report. When the service operation data type is AT command data, the encapsulation module 1122 is run to generate AT command messages based on the AT command data; when the service operation data type is OAM detection data, the encapsulation module 1123 is run to generate from the OAM detection data OAM detection message. When the processor 11 runs the packaging module corresponding to the service operation data type, the processor 11 may obtain the service operation data from the memory 1 according to the storage address in the first parameter group, thereby generating information to be sent according to the service operation data. In a feasible implementation manner, if the data amount of the service operation data is small, the first parameter group may also include the service operation data, so that when the processor 11 runs the encapsulation module, the service may be directly obtained from the first parameter group Operating data.

After the processor 11 generates the information to be sent in the memory 1, it also generates a second parameter group that meets the preset packaging format by running the encapsulation module, which includes the storage address of the information to be sent in the memory 1, and may also include the information to be sent. Parameters such as the message length of the message. For example, the encapsulation module 1121 is a TCP / IP protocol stack. The information to be sent generated by the processor 11 running the encapsulation module 1121 is an IP packet. The IP packet can be sent by a network interface adapter (NIC), so it is processed. The second parameter group generated by the processor 11 running the encapsulation module 1121 may be used as an operating parameter of a driver for running the NIC. For another example, the encapsulation module 1122 is an AT command processing program. The information to be sent generated by the processor 11 running the encapsulation module 1122 is an AT command message. The AT command message can be sent by a serial communication port (cluster communication port, COM). The second parameter group generated by the encapsulation module 1122 can be used as an operation parameter of a driver running COM. In the embodiment of the present application, the processor 11 will run the virtual interface module 113 during the configuration phase. Each of the multiple virtual interfaces in the virtual interface module 113 simulates the registration process of the driver software of the physical interface (such as NIC, COM) to the corresponding The encapsulation module registers the physical interface. The registration information includes the identification, type, and format requirements of the physical interface. Therefore, for the encapsulation module, the encapsulation module can accept the registration of the virtual interface under the existing software structure that does not support PCIE interconnection. When the processor 11 runs the packaging module, after generating the second parameter group, the processor 11 can call the virtual interface corresponding to the packaging module by running the existing program that calls the physical interface in the packaging module, even if the packaging module does not support PCIE interconnection. It is coupled with the lower-level PCIE driver module through the corresponding virtual interface. Therefore, the virtual interface module plays a role between the packaging module and the PCIE driver module.

The processor 11 receives the second parameter group by running the virtual interface corresponding to the packaging module in the virtual interface module 113, and the driver software of the physical interface (such as the aforementioned NIC, COM interface) in the existing software architecture is replaced by the virtual interface. The phase virtual interface is registered in the encapsulation module, so the second parameter group generated by the encapsulation module can satisfy the parameter format required by the virtual interface corresponding to the encapsulation module and can be recognized by the virtual interface. As shown in the software architecture shown in FIG. 2, the virtual interface module 113 includes multiple virtual interfaces (such as virtual interfaces A, B, C, and D in FIG. 2). The types of these virtual interfaces may be the same or different. Different types of virtual interfaces The second parameter group generated by running different packaging modules can be received, so that the virtual interface module 113 can adapt to different types of packaging modules upwards. For example, the virtual interface A is a virtual network interface adapter (VNIC). After the processor 11 runs the encapsulation module 1121 to generate a communication packet and a second parameter group, the virtual interface A replaces the existing software architecture. The driver software of the NIC receives the second parameter group. As another example, the virtual interface B is a virtual serial communication port (VCOM). The processor 11 runs the encapsulation module 1122 to generate an AT command message and a second parameter group, and then calls the virtual interface B. The virtual interface B B receives the second parameter group instead of the driver software of COM in the existing software architecture.

In a feasible implementation manner, as shown in FIG. 2, the virtual interface module 113 includes multiple virtual interfaces and a PCIE adaptation layer 1132. After the processor 11 receives the second parameter group through the virtual interface instead of the driver software of the actual interface in the existing software architecture, it runs the PCIE adaptation layer 1132 to convert the second parameter group into a third parameter group that meets the PCIE format. The third parameter group can be recognized and received by the PCIE driver module. The third parameter group includes at least a storage address of the information to be transmitted in the memory 1 and a destination address of the information to be transmitted in the memory 2, and may further include parameters such as the information length of the information to be transmitted. Based on the PCIE protocol, the chip 1 as the transmitting end can specify the storage address of the information to be transmitted in the memory 2. As shown in FIG. 3, during the initial power-up period of chip 1 and chip 2, chip 1 enumerates and maps the address space configuration of chip 2, so that the

address space

21, 22 in memory 2 for storing the information sent by chip 1 can be determined. , 23, 24 (same for chip 2). In the software architecture run by the processor 11, a plurality of virtual interfaces in the virtual interface module 113 respectively correspond to a plurality of address spaces of the memory 2. As shown in FIG. 4, the same is true for the chip 2. When the processor 11 runs the virtual interface module 113, the destination address of the information to be sent in the memory 2 is determined according to the virtual interface receiving the second parameter group. For example, the virtual interface A corresponds to the address space 21 in the memory 2. When the processor 11 runs the virtual interface module 113, if the virtual interface A receives the second parameter group, the processor 11 determines the destination address of the information to be sent For address space 21.

In a feasible implementation manner, the processor 11 can monitor the usage of each address space in the memory 2. After determining the address space corresponding to the virtual interface, the processor 11 can further determine the information to be sent according to the storage conditions of the address space. A more specific destination address is specified in this address space. For example, the processor 11 may enumerate and map the address space configuration of the chip 2 and then run the PCIE adaptation layer to divide each address space in the memory 2 into multiple storage units and continuously monitor each of the memory 2 Usage of multiple storage units in the address space. After the processor 11 determines the address space corresponding to the virtual interface, it can also designate one or more unoccupied storage units for the information to be sent according to the use of multiple storage units in the address space by running the PCIE adaptation layer. Store the information to be sent.

After the processor 11 generates a third parameter group that meets the PCIE format by running the virtual interface module 113, the processor 11 runs the PCIE driving module 114. The processor 11 drives the PCIE controller 12 to send the information to be sent to the PCIE controller 22 of the chip 2 by running the PCIE driver module 114 according to the third parameter group. The specific implementation manners thereof can include at least the following two types: in a feasible implementation In the method, the processor 11 runs the PCIE driver module 114 to obtain the information to be transmitted from the memory 1 according to the storage address of the information to be transmitted in the third parameter group in the memory 1, and drives the PCIE controller to transmit the information to be transmitted. The information is sent to chip 2. This implementation requires the processor 11 to send the information to be sent to the PCIE controller 12, so it is suitable for situations where the amount of information to be sent is small, such as AT command messages or OAM messages from the encapsulation module. Control surface information. In another feasible implementation manner, the processor 11 obtains the storage address of the information to be sent in the third parameter group by running the PCIE driver module 114, and drives the PCIE controller 12 from the memory 1 according to the storage address of the information to be sent. To obtain the information to be sent, and send the information to be sent to the chip 2. In this implementation mode, the PCIE controller 12 obtains and sends information to be sent from the memory 1, so compared to the previous implementation mode, it is more suitable for situations where the amount of data to be sent is large, such as IP from the encapsulation module. A message, which may be data from a higher-level service module and IP-encapsulated by an encapsulation module. The data may include game data, graphic data, and other user-plane data with a large amount of data.

When the processor 11 runs the PCIE driver module 114, it can drive the PCIE controller 12 to send the identification information of the address space 21 to the PCIE controller 22, so that the PCIE controller 22 can receive the received information according to the identification information of the address space 21. The information is stored in the address space 21 of the memory 2. In another feasible implementation manner, the PCIE physical connection between the PCIE controller 12 and the PCIE controller 22 includes multiple virtual channels, which may also be referred to as logical channels, and multiple virtual channels and multiple addresses of the memory at both ends. Spaces correspond to each other. By running the PCIE driver module 114, the processor 11 determines the virtual channel corresponding to the address space 21 and drives the PCIE controller 12 to send information to be sent through the virtual channel, so that the PCIE controller 22 of the chip 2 After receiving the information, the virtual channel stores the received information in the address space 21 corresponding to the channel in the memory 2.

In the process of sending information from chip 1 to chip 2, the second parameter set generated by processor 11 by running the packaging module may be the second parameter set of the driving software for running the physical interface in the existing software architecture. The virtual interface in the virtual interface module 113 replaces the driver software of the physical interface to achieve the adaptation to the encapsulation module. At the same time, by running the PCIE adaptation layer 1132, the second parameter group is converted into a third parameter that the PCIE driver module 114 can recognize. Group, to achieve the adaptation to the PCIE driver module 114, so that the PCIE interconnection can be achieved without changing the existing packaging module. Compared with changing the open source and general packaging module, the embodiment of this application The design brought by adding the virtual interface module 113 to the running software architecture will be much less, thereby realizing that the existing chip can use the PCIE controller without substantially changing the existing software architecture. It can be understood that the virtual interface of this embodiment is used to implement the connection with the packaging module to adapt to different types of packaging modules upwards, and the PCIE adaptation layer downwardly adapts to the PCIE driver module. Based on this solution, the virtual interface module 113 can realize the upward connection with different packaging modules and the downward connection with the PCIE driver module. The information formed after the packaging and processing of different packaging modules is converted into information that can be recognized by the PCIE driver module, without the need to significantly modify the existing Packaging module.

In a feasible implementation manner, multiple virtual interfaces in the virtual interface module 113 have different priorities. When the processor 11 generates multiple second parameter groups simultaneously by running different encapsulation modules, it can run the virtual interface module 113 to run the PCIE adaptation layer according to the priorities of the virtual interfaces corresponding to the multiple second parameter groups. In 1132, the second parameter group received by the virtual interface is sequentially converted into a third parameter group in order of priority from high to low, and processed in sequence. The above scheme enables services corresponding to a virtual interface with a higher priority to be preferentially delivered to the PCIE adaptation layer 1132 and the PCIE driver module 114 and processed preferentially. With the above solution, the processor 11 can run the PCIE driver module 114 to drive the PCIE controller 12 to preferentially send the information to be sent generated by the packaging module corresponding to the virtual interface with a higher priority, thereby improving the overall quality of service of the system. service, QOS). For example, for the emergency sequence service in the service module 111, assuming that the processor 11 encapsulates service operation data generated by running the emergency sequence service by running the encapsulation module 1124, the virtual interface D in the virtual interface module 113 has the highest priority. The processor 11 runs the PCIE adaptation layer 1132, and firstly converts the second parameter group received by the virtual interface D into a third parameter group, so that the PCIE driver module 114 can preferentially drive the PCIE controller 12 to send an emergency according to the third parameter group. Information to be sent corresponding to the time series service.

In this embodiment, the information transmitted between the chip 1 and the chip 2 through the PCIE interface may be control plane information, including control information that meets various control functions, or user plane data, such as various service data. For example, if the virtual interface is a virtual VCOM, it is used to transmit control plane information; if the virtual interface is a virtual VNIC, it is used to transmit user plane data. The control plane information may include control information generated by the encapsulation module, such as AT command messages or OAM messages generated by the encapsulation module. The control information may be initiated by the encapsulation module, or it may be generated after the information initiated by the service module is encapsulated by the encapsulation module. . The user plane data includes various types of business data generated by the encapsulation module that meets user requirements, that is, various types of IP packets. The IP packets are generated after the encapsulation module performs IP encapsulation on the business data of the upper-level business module. Includes user data, such as game data, graphic data, video data, voice data, or communication data.

Correspondingly, taking the process in which chip 2 receives information sent by chip 1 as an example, the architecture of the software running in processor 21 is introduced. It should be understood that the process in which chip 1 receives information sent by chip 2 is similar to this. Repeat them one by one.

The processor 21 runs the PCIE driver module 214, and after determining that the to-be-processed information (ie, the second information) is received from the chip 1, determines the storage address of the to-be-processed information in the memory 2 and generates a fourth address that meets the PCIE format A parameter group, and the fourth parameter group includes a storage address of the information to be processed in the memory 2. Wherein, the storage address of the information to be processed in the memory 2 can be queried by the processor 21 by running the PCIE driver module 214 according to a preset period, so as to determine that the information to be processed and the information to be processed are received within the period interval. Storage address in memory 2. Alternatively, by running the PCIE driver module 214, after receiving the first trigger signal sent by the interrupt register 23, it is determined that the information to be processed is received, and the interrupt message buffered by the interrupt register 23 is actively queried, where the interrupt message is processed The processor 11 is generated by running the PCIE driver module 114 according to the destination address of the information to be sent, and the processor 21 may determine the storage address of the information to be processed in the memory 2 according to the interrupt message.

The processor 21 runs the virtual interface module 213 to generate a fifth parameter group that satisfies a preset packaging format according to the fourth parameter group, and the fifth parameter group includes a storage address of the information to be processed in the memory 21. In a feasible implementation manner, the processor 21 determines that the memory 21 stores the memory 21 in the memory 2 according to the information to be processed in the fourth parameter group by running the PCIE adaptation layer 2132 in the virtual interface module 213. The address space of the information is processed to determine a virtual interface corresponding to the address space, and according to the virtual interface, a preset packaging format of a packaging module corresponding to the virtual interface is determined, so as to convert the fourth parameter group to meet the packaging module The fifth parameter group of the packaging format is set so that the fifth parameter group can be identified by the packaging module corresponding to the virtual interface. The virtual interface module 213 includes multiple virtual interfaces (such as virtual interfaces E, F, G, and H in FIG. 2), and the multiple virtual interfaces correspond to multiple address spaces in the memory 2, as shown in FIG. 4, Chip 1 is the same. For example, the virtual interface E in FIG. 4 corresponds to the address space 21. By running the virtual interface module 213, the processor 21 can determine the information to be processed according to the fourth parameter group and store the address space 21 in the memory 2. The virtual interface E corresponding to the address space 21, the virtual interface E is a VNIC, the encapsulation module 2121 is a TCP / IP protocol stack, and the processor 21 converts the fourth parameter group into a TCP / IP protocol stack by running the virtual interface module 213 The fifth parameter group. As another example, when the processor 21 runs the virtual interface module 213 and determines the address space 22 to be stored in the memory 2 according to the fourth parameter group, it can determine the virtual interface F and virtual interface corresponding to the address space 22 F is VCOM, the encapsulation module 2122 is an AT command processing program, and the processor 21 converts the fourth parameter group into a fifth parameter group for running the AT command processing program by running the virtual interface module 213.

After the processor 21 runs the encapsulation module corresponding to the virtual interface determined according to the storage address where the information to be processed is located, the processor 21 decapsulates the information to be processed according to a preset decapsulation rule by running the encapsulation module to obtain the data to be processed and A sixth parameter group is generated, and the sixth parameter group can be identified by the service module 211. The processor 21 determines the data to be processed from the memory 2 according to the storage address of the data to be processed in the sixth parameter by running the service module 211 and performs processing. For example, the encapsulation module 2121 is a TCP / IP protocol stack, and the information to be processed is an IP packet. When the chip 2 is a communication chip, the encapsulation module 2121 can forward the IP packet to the 4G or 5G air interface communication program in the service module 211. The processor 21 determines the IP message from the memory 2 according to the sixth parameter group by running the 4G or 5G air interface communication program in the service module 211, and encapsulates the IP message into an air interface message conforming to the 4G or 5G air interface communication protocol and converts the IP message. It is a wireless signal and sent out through the antenna. When chip 2 is an application chip, the processor 21 can perform decapsulation and merge operations on the IP packet according to the TCP / IP protocol by running the encapsulation module 2121. After obtaining the data to be processed, the processor 21 runs the service module 211 The application processes the data to be processed according to the sixth parameter group. For another example, the encapsulation module 2122 is an AT command processing program, and the information to be processed is an AT command message. The processor 21 can determine the type of the AT command message according to the format of the AT command message by running the encapsulation module 2122, and send it to the service module 211. The corresponding program executes the AT command message.

In the above embodiments, each software module that can be run by the processor, such as a business module, a packaging module, a virtual interface module, and a PCIE driver module, can be implemented in whole or in part through configurable software, firmware, or any combination thereof. It can be understood that firmware is also a special kind of software. When any module is implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer or a processor of the embodiment, the processes or functions according to the embodiment of the present invention are wholly or partially generated. The computer or processor may be equivalent to a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, such as the memory mentioned in the previous embodiment, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from A website site, computer, server, or data center uses wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) to another website site, computer, server, or data Center for transmission. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, a data center, and the like that includes one or more available medium integrations. The available medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (Solid State Disk (SSD)), and the like.

The present application is described with reference to block diagrams of an apparatus (system) and a computer program product according to the present application. These computer program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to produce a machine, so that the instructions generated by the processor of the computer or other programmable data processing device are used to generate instructions Means for implementing the functions specified in one or more blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to work in a specific manner such that the instructions stored in the computer-readable memory produce a manufactured article including an instruction device, the instructions The device implements the functions specified in one or more blocks of the block diagram.

Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, this application also intends to include these modifications and variations.

Claims

A high-speed interconnected PCIE transmission device for peripheral devices is characterized in that it includes:

An encapsulation module, configured to generate first information to be transmitted and a second parameter group that satisfies a preset encapsulation format according to a preset encapsulation rule; the second parameter group includes the first information corresponding to the PCIE sending device A storage address in the first memory;

A virtual interface module, configured to receive the second parameter group from the encapsulation module, and generate a third parameter group that meets the PCIE format according to the second parameter group, where the third parameter group includes the storage address and the The destination address in the second memory corresponding to the PCIE receiving device;

A PCIE driver module is configured to receive the third parameter group from the virtual interface module, parse the third parameter group to obtain the storage address and the destination address, and send the first corresponding to the PCIE device to the first The PCIE controller sends a first instruction for driving the first PCIE controller to send the first information, the first instruction includes the destination address, and the first instruction further includes the first information or A storage address of the first information in the first memory.
The PCIE transmitting device according to claim 1, wherein the virtual interface module comprises a virtual interface and a PCIE adaptation layer;

The virtual interface corresponds to the encapsulation module, and is configured to receive the second parameter group from the encapsulation module and provide it to the PCIE adaptation layer;

The PCIE adaptation layer is configured to determine an address space corresponding to the virtual interface in the second memory, determine the destination address according to the address space, and determine the destination address according to the second parameter group and the destination address. Generating the third parameter group that satisfies the PCIE format.
The PCIE transmitting device according to claim 2, wherein the virtual interface is a virtual network interface adapter VNIC or a virtual serial communication port VCOM.
The PCIE transmitting device according to claim 2 or 3, wherein the device includes multiple encapsulation modules, and the virtual interface module includes multiple virtual interfaces; each virtual interface corresponds to one encapsulation module, and each Virtual interfaces have priority;

The PCIE adaptation layer is specifically configured to obtain a processing order for multiple virtual interfaces according to the priorities of the multiple virtual interfaces, and sequentially generate the third parameter corresponding to each virtual interface according to the processing order. group.
The PCIE sending device according to any one of claims 1 to 4, further comprising:

A service module, configured to generate service running data in the first memory;

The encapsulation module is specifically configured to perform encapsulation processing on the service operation data according to the preset encapsulation rule to generate the first information and the second parameter group corresponding to the type of the service operation data. .
The PCIE transmitting device according to any one of claims 1 to 5, wherein the encapsulation module is a transmission control protocol / network interconnection protocol TCP / IP protocol stack encapsulation module, or an AT command processing program encapsulation module, or Operate, manage, and maintain OAM inspection program packaging modules.
A high-speed interconnected PCIE receiving device for peripheral devices, comprising:

A PCIE driver module, configured to determine a storage address of the second information to be processed in a second memory corresponding to the PCIE receiving device, and generate a fourth parameter group that meets the PCIE format, where the fourth parameter group includes the storage address ;

A virtual interface module, configured to receive the fourth parameter group from the PCIE drive module, and generate a fifth parameter group that satisfies a preset package format according to the fourth parameter group; the fifth parameter group includes the storage address ;

The encapsulation module is configured to receive the fifth parameter group from the virtual interface module, parse the fifth parameter group to obtain the storage address, and obtain the second information according to the storage address. The set decapsulation rule generates data to be processed after decapsulating the second information.
The PCIE receiving device according to claim 7, wherein the virtual interface module comprises a virtual interface and a PCIE adaptation layer;

The PCIE adaptation layer is configured to receive the fourth parameter group from the PCIE driver module, determine an address space corresponding to the storage address according to the fourth parameter group, and determine the corresponding space corresponding to the address space. A virtual interface; determining the preset packaging format of the packaging module corresponding to the virtual interface; generating a fifth parameter group that satisfies the preset packaging format according to the fourth parameter group, and providing the fifth parameter group Giving the virtual interface;

The virtual interface corresponds to the encapsulation module, and is configured to receive the fifth parameter group provided by the PCIE adaptation layer, and send the fifth parameter group to the encapsulation module.
The PCIE receiving device according to claim 8, wherein the virtual interface is a virtual network interface adapter VNIC or a virtual serial communication port VCOM.
The PCIE receiving device according to any one of claims 7 to 9, wherein:

The encapsulation module is specifically configured to perform decapsulation processing on the second information according to a preset decapsulation rule to generate data to be processed corresponding to the type of the encapsulation module;

The PCIE receiving device further includes a service module, configured to process the data to be processed.
The PCIE receiving device according to any one of claims 7 to 10, wherein the packaging module is a transmission control protocol / network interconnection protocol TCP / IP protocol stack packaging module, or an AT command processing program packaging module, or Operate, manage, and maintain OAM inspection program packaging modules.
A high-speed interconnection PCIE transmission method for peripheral devices is characterized in that it includes:

Use the encapsulation module to generate first information to be transmitted and a second parameter group that satisfies a preset encapsulation format according to a preset encapsulation rule; the second parameter group includes a first parameter corresponding to the first information in the PCIE sending device. A storage address in a memory;

Using a virtual interface module to generate a third parameter group that meets the PCIE format according to the second parameter group, where the third parameter group includes the storage address and a destination address in a second memory corresponding to the PCIE receiving device;

Use a PCIE driver module to parse the third parameter group to obtain the storage address and the destination address, and send the first parameter to the first PCIE controller corresponding to the PCIE sending device for driving the first PCIE controller to send all The first instruction of the first information, the first instruction includes the destination address, and the first instruction further includes the first information or a storage address of the first information in the first memory.
The PCIE sending method according to claim 12, wherein the virtual interface module comprises a virtual interface and a PCIE adaptation layer;

The generating a third parameter group that meets the PCIE format according to the second parameter group by using the virtual interface module includes:

Receiving the second parameter group from the encapsulation module by using the virtual interface, and providing the second parameter group to the PCIE adaptation layer;

Use the PCIE adaptation layer to determine an address space corresponding to the virtual interface in the second memory, determine the destination address according to the address space, and generate a satisfying address based on the second parameter group and the destination address The third parameter group in the PCIE format.
The PCIE sending method according to claim 13, wherein the virtual interface is a virtual network interface adapter VNIC, and / or a virtual serial communication port VCOM.
The PCIE sending method according to claim 13 or 14, wherein the PCIE sending device includes multiple encapsulation modules, and the virtual interface module includes multiple virtual interfaces; each virtual interface corresponds to one encapsulation module, And each virtual interface has priority;

Generating the third parameter group that meets the PCIE format according to the second parameter and the destination address includes:

Use the PCIE adaptation layer to obtain a processing order for multiple virtual interfaces according to the priorities of the multiple virtual interfaces, and sequentially generate the third parameter group corresponding to each virtual interface according to the processing order.
A high-speed interconnect PCIE receiving method for peripheral devices, comprising:

Using a PCIE driver module to determine a storage address of the second information to be processed in a second memory corresponding to the PCIE receiving device, and generating a fourth parameter group that meets the PCIE format, where the fourth parameter group includes the storage address;

Receiving the fourth parameter group from the PCIE driver module by using a virtual interface module, and generating a fifth parameter group that satisfies a preset packaging format according to the fourth parameter group; the fifth parameter group includes the storage address;

Receiving the fifth parameter group by using an encapsulation module, parsing the fifth parameter group to obtain the storage address, and obtaining the second information according to the storage address, and performing The information is decapsulated to generate data to be processed.
The PCIE receiving method according to claim 16, wherein the virtual interface module comprises a virtual interface and a PCIE adaptation layer;

Using a virtual interface module to generate a fifth parameter group that satisfies the identification format of the encapsulation module according to the storage address of the second information, including:

Receiving the fourth parameter group from the PCIE driver module by using the PCIE adaptation layer, and determining an address space corresponding to the storage address according to the fourth parameter group; determining the virtual interface corresponding to the address space Determining a preset packaging format of the packaging module corresponding to the virtual interface; generating a fifth parameter group that satisfies the preset packaging format according to the fourth parameter group, and providing the fifth parameter group to the virtual interface;

Using the virtual interface to receive the fifth parameter group provided by the PCIE adaptation layer, and send the fifth parameter group to the encapsulation module.
The PCIE receiving method according to claim 17, wherein the virtual interface is a virtual network interface adapter VNIC or a virtual serial communication port VCOM.
A peripheral device high-speed interconnected PCIE transmission device includes a processor and a first PCIE controller. The processor is used for:

The running encapsulation module generates first information to be sent and a second parameter group that satisfies a preset encapsulation format according to a preset encapsulation rule; the second parameter group includes a first information corresponding to the first information in the PCIE sending device. A storage address in a memory; generating a third parameter group that meets the PCIE format according to the second parameter group by running a virtual interface module, the third parameter group including the storage address and a second corresponding to the PCIE receiving device The destination address in the memory; the third parameter group is parsed by running the PCIE driver module to obtain the storage address and the destination address, and is sent to the first PCIE controller for driving the first PCIE controller to send A first instruction of the first information, the first instruction includes the destination address, and the first instruction further includes a storage address of the first information or the first information in the first memory ;

The first PCIE controller is configured to receive the first instruction, obtain the first information from the first instruction, or, from the first memory, according to the storage address in the first instruction Acquiring the first information, and sending the first information to a second PCIE controller corresponding to the PCIE receiving device.
The PCIE transmission device according to claim 19, wherein the PCIE transmission device is a root complex, and the processor is further configured to: run a PCIE driver module to generate an interrupt message according to the destination address and send the interrupt message to all The first PCIE controller;

The first PCIE controller is further configured to send the interrupt message to the second PCIE controller.
A peripheral device high-speed interconnected PCIE receiving device, comprising a processor and a second PCIE controller;

The second PCIE controller is configured to receive second information sent by the first PCIE controller corresponding to the PCIE sending device, and store the second information into the PCIE reception according to a destination address corresponding to the second information. A second memory corresponding to the device;

The processor is configured to run a PCIE driver module to determine a storage address of the second information in the second memory, and generate a fourth parameter group satisfying the PCIE format, where the fourth parameter group includes the storage address; The running virtual interface module receives the fourth parameter group from the PCIE driver module, and generates a fifth parameter group that satisfies a preset package format according to the fourth parameter group; the fifth parameter group includes the storage address; The encapsulation module receives the fifth parameter group, parses the fifth parameter group to obtain the storage address, and obtains the second information according to the storage address, and performs a second decapsulation rule on the second information. After decapsulation, data to be processed is generated.
The PCIE receiving device according to claim 21, wherein the PCIE receiving device is an endpoint, and the PCIE receiving device further comprises interrupt registers respectively connected to the second PCIE controller and the processor;

The second PCIE controller is further configured to receive an interrupt message sent by the first PCIE controller, and store the interrupt message in the interrupt register;

The interrupt register is used to buffer the interrupt message and send a first trigger signal to the processor;

The processor is further configured to determine, after receiving the first trigger signal, a storage address in the second memory for storing the second information according to the interrupt message in the interrupt register.
A peripheral device high-speed interconnected PCIE system, comprising a PCIE transmitting device according to claim 19 or claim 20, and / or a PCIE receiving device according to claim 21 or claim 22.