CN111211863B - MAC transmitting terminal, MAC receiving terminal and circuit, FPGA chip and data transmission system - Google Patents

Abstract

The invention discloses an MAC transmitting terminal, an MAC receiving terminal circuit, an FPGA chip and a data transmission system, wherein the MAC transmitting terminal executes the following steps: caching a user frame issued by an upper layer, and encapsulating the cached user frame into a logic frame of a first frame, a plurality of intermediate frames and a tail frame according to frame header information of the user frame, wherein the first frame and the tail frame are marked during encapsulation; sequentially writing the logic frames into the transmitting end cache channels respectively; and reading out and transmitting the logical frame in the buffer channel of the transmitting end. The MAC receiving end executes the following steps: receiving a logical frame; writing the received logic frame into a receiving end cache channel, wherein the receiving end cache channel configuration corresponds to the transmitting end cache channel configuration; and identifying the logic frame in the buffer channel of the receiving end to determine a first frame, using a head of the first frame as a head of a user frame, using a load of the first frame, a load of an intermediate frame and a load of a tail frame as a load of the user frame to frame, and restoring the user frame. The whole data transmission system can perform 100M rate transmission and has low error rate.

Description

MAC transmitting terminal, MAC receiving terminal and circuit, FPGA chip and data transmission system

Technical Field

The invention relates to the field of 1553 data information transmission, in particular to a high-speed 1553 mixed service data frame-sealing framing circuit and an information data processing method based on an FPGA (field programmable gate array).

Background

The 1553b bus is an information transmission bus standard specially made for equipment on an airplane by the U.S. military, namely a protocol for transmission among equipment. The traditional 1553 standard is proposed from the last 70 th century to the present day and is widely applied to backbone communication with military purposes such as aviation, aerospace and weaponry.

1553 communication is wired communication using a wireless communication algorithm, and in the case of high-speed communication, the requirement for the frame length of data is high, and the longer the frame payload length is, the lower the data transmission efficiency is and the communication reliability is also reduced. In conventional data communication, the payload of a frame transmitted by an upper layer PC is often between 0 KB and 64KB, while the error rate of a wireless link of a lower layer starts to increase along with the increase of the payload of the data frame because the error rate of the frame increases along with the increase of the frame length, which is contrary to the actual communication principle.

Disclosure of Invention

In order to solve the problems in the prior art and meet the requirements of transmission capabilities of different data frames in a high-speed 1553 data transmission system, the invention provides a framing circuit and a framing method of MAC mixed service based on an FPGA (field programmable gate array), which are used for completing the segmentation and framing of data frames in one FPGA.

In order to solve the technical problems, the technical scheme adopted by the invention is as follows:

a MAC transmitter having a first computer program stored therein, the first computer program being executed by a processor according to the steps of:

step 1, caching a user frame issued by an upper layer, wherein the user frame comprises a user frame header and a user frame load, and framing the cached user frame into a first frame, a plurality of intermediate frames and a tail frame according to the user frame header, wherein the first frame and the tail frame are marked during framing; the first frame comprises a first frame header and a first frame load, the intermediate frame comprises an intermediate frame header and an intermediate frame load, and the tail frame comprises a tail frame header and a tail frame load; the first frame, the intermediate frame and the end frame are all logic frames;

step 2, sequentially writing the logic frames into a transmitting end cache channel respectively;

and 3, reading out and transmitting the logic frame in the buffer channel of the transmitting end.

Preferably, in step 1, the user frame is cached in the RAM, the memory space of the RAM is divided into a plurality of areas, each area occupies 1 kbyte, the user frame is stored in the RAM, the larger the frame is, the more the number of the occupied areas is, and the first byte of the user frame in each frame is located at the start address of the area.

Preferably, in step 2, the number of the transmitting-end buffer channels is configured by the user end, and the number is between 1 and 8.

The invention also provides a circuit based on the MAC transmitting terminal, which sequentially comprises a storage and frame sealing module, a transmitting terminal channel cache module and a data transmitting module which are connected in series;

the storage and frame sealing module is used for caching a user frame issued by an upper layer, the user frame comprises a user frame header and a user frame load, the cached user frame is sealed into a first frame, a plurality of intermediate frames and a tail frame according to the user frame header, and the first frame and the tail frame are marked during frame sealing; the first frame, the intermediate frame and the end frame are all logic frames;

the transmitting end channel cache module is used for caching a plurality of logic frames and crossing clock domains, and converting a logic frame byte data stream into a bit data stream;

and the data transmitting module is used for reading out the logic frame bit data stream and transmitting the logic frame bit data stream.

On this basis, the present invention provides an MAC receiving end, in which a second computer program is stored, and when executed by a processor, the second computer program implements the following steps:

step a, receiving a logic frame;

step b, writing the received logic frame into a receiving end cache channel, wherein the receiving end cache channel configuration corresponds to the transmitting end cache channel configuration;

and c, identifying the logic frame in the cache channel of the receiving end to determine a first frame, taking a head of the first frame as a head of a user frame, taking a load of the first frame, a load of an intermediate frame and a load of a tail frame as a load of the user frame to frame, and restoring the user frame.

Preferably, in step c, the address written in the first byte of the first frame is locked during framing, after the user frame is restored, whether the load quantity of the user frame is correct or not is judged, and if the load quantity is correct, a frame ending mark is added at the end of the user frame; and if the data is incorrect, deleting the wrong user frame, returning to the locked address, and restarting to write the next frame of user frame data.

A circuit based on the MAC receiving end sequentially comprises a data receiving module, a receiving end channel cache module and a storage and framing module which are connected in series;

the data receiving module is used for receiving a logic frame bit data stream;

the receiving end channel cache module is used for converting the received logic frame bit data stream into a multi-bit data stream and crossing a clock domain, and the configuration of the receiving end cache channel corresponds to that of the transmitting end cache channel;

the storage and framing module is used for identifying the logic frames in the buffer channel of the receiving end to determine the first frame, taking the head of the first frame as the head of the user frame, taking the load of the first frame, the load of the intermediate frame and the load of the tail frame as the load of the user frame to frame, and restoring the user frame.

The invention also provides an FPGA chip, wherein the chip is integrated with an MAC transmitting end and an MAC receiving end;

the MAC transmitting terminal is stored with a first computer program, and the first computer program is executed by a processor according to the following steps:

step 1, caching a user frame issued by an upper layer, wherein the user frame comprises a user frame header and a user frame load, and the cached user frame is encapsulated into a first frame, a plurality of intermediate frames and a tail frame according to the user frame header, and the first frame and the tail frame are marked during frame encapsulation; the first frame comprises a first frame header and a first frame load, the intermediate frame comprises an intermediate frame header and an intermediate frame load, and the tail frame comprises a tail frame header and a tail frame load; the first frame, the intermediate frame and the end frame are all logic frames;

step 2, sequentially writing the logic frames into a transmitting end cache channel respectively;

step 3, reading out and transmitting the logic frame in the buffer channel of the transmitting terminal

The MAC transmitting and receiving end stores a second computer program, and when executed by the processor, the second computer program implements the following steps:

step a, receiving a logic frame;

step b, writing the received logic frame into a receiving end cache channel, wherein the receiving end cache channel configuration corresponds to the transmitting end cache channel configuration;

and c, identifying the logic frame in the cache channel of the receiving end to determine a first frame, taking a head of the first frame as a head of a user frame, taking a load of the first frame, a load of an intermediate frame and a load of a tail frame as a load of the user frame to frame, and restoring the user frame.

Finally, the invention also provides a data transmission system, which comprises an MAC layer, a PHY layer, a PCI control layer and a control signal processing layer, wherein the MAC layer comprises an MAC transmitting end and an MAC receiving end;

the MAC transmitting end has a first computer program stored therein, the first computer program being executed by a processor according to the following steps:

step 1, caching a user frame issued by an upper layer, wherein the user frame comprises a user frame header and a user frame load, and the cached user frame is encapsulated into a first frame, a plurality of intermediate frames and a tail frame according to the user frame header, and the first frame and the tail frame are marked during frame encapsulation; the first frame comprises a first frame header and a first frame load, the intermediate frame comprises an intermediate frame header and an intermediate frame load, and the tail frame comprises a tail frame header and a tail frame load; the first frame, the intermediate frame and the end frame are all logic frames;

step 2, sequentially writing the logic frames into the transmitting end cache channels respectively;

step 3, reading out and transmitting the logic frame in the buffer channel of the transmitting terminal

The MAC transmitting/receiving end stores therein a second computer program, and when executed by the processor, the second computer program implements the following steps:

step a, receiving a logic frame;

step b, writing the received logic frame into a receiving end cache channel, wherein the receiving end cache channel configuration corresponds to the transmitting end cache channel configuration;

c, identifying the logic frame in the buffer channel of the receiving end to determine a first frame, using a head of the first frame as a head of a user frame, using a load of the first frame, a load of an intermediate frame and a load of a tail frame as a load of the user frame to frame, and restoring the user frame;

the PHY layer is used for linking the MAC layer and the PCI control layer, OFDM algorithm processing is carried out on data processed by the MAC layer, and data transmission is carried out according to different frequency bandwidths;

the PCI control layer is used for a communication link of command information and data of an upper layer user side;

the control signal processing layer is used for tracking and controlling the MAC layer, the PHY layer and the PCI control layer and configuring a receiving end cache channel and a transmitting end cache channel.

Compared with the prior art, the invention has the following beneficial effects:

according to the MAC transmitting end and the receiving end, the transmitting end slices and divides the giant user frame into the small logical frames for transmission, each segment is sent and confirmed independently, and the receiving end transmits the received segment frames to an upper layer in a form of new assembly of the segment frames into the user frame, so that the frame error rate can be solved, and the communication rate is greatly improved.

In the FPGA, the PCI control circuit is connected with the pins of the FPGA through the external linker, a transmitting end MAC layer and a receiving end MAC layer are integrated, in one-to-one transmission and reception, the segmentation of a user frame and the de-segmentation of a bottom layer frame are finished at the MAC layer, and the MAC layer can determine the size of a payload of a transmission slice frame in the current communication process according to the communication quality of the lower layer, thereby reducing the error rate.

The data transmission system can perform mixed service framing and framing, and comprises an MAC layer, a PHY layer, a PCI control layer and a control signal processing layer, wherein the MAC layer comprises a cache framing module, a channel module, a transmitting module, a receiving module and a cache framing module. All module circuits work in series, data frames with different formats in the 1553 field are transmitted, a user can change the rate according to actual requirements through configuration of the number of channels, and the whole system can transmit information at the communication rate of 100 Mbps.

Drawings

FIG. 1 is a schematic diagram of the system of the present invention.

FIG. 2 is a schematic diagram of the implementation of the method of the present invention.

FIG. 3 is a functional diagram of a memory framing module according to the present invention.

Fig. 4 is a schematic diagram of a user frame buffer RAM at the sending end of the present invention.

Fig. 5 is a schematic diagram of user frame framing at a sending end according to the present invention.

FIG. 6 is a functional diagram of a storage framing module according to the present invention.

Fig. 7 is a diagram illustrating framing of a receiving-end user frame according to the present invention.

Detailed Description

The invention will be further explained by the description of the embodiments with reference to the drawings.

The "frame" of the present invention refers to: data is transmitted over a network in very small units called frames, which are composed of several parts, different parts performing different functions. The frame types include management frames, control frames, and data frames.

The data frame of the invention is a data unit when data is transmitted on the network, and a 'frame' of data consists of two parts: frame header and frame data. The frame header includes the location of the physical address of the receiving host and other network information, and the frame data contains a data body. The data frame is a fixed mode in the transmission process of a physical network, and all data packets are encapsulated into the data frame and are projected to the network.

The framing of the frame means that a sender must encapsulate a packet delivered by a network layer into a frame according to a certain rule in order for a receiver to correctly receive and check the transmitted frame.

In addition, framing according to the present invention means that frame formats transmitted on different layers are different, and each layer decapsulates a previous encapsulated frame into a frame format supported by the layer.

The MAC, PHY, and OI of the present invention are defined as follows:

the chip of the data link layer in the Ethernet card is generally called as MAC controller, the chip of the physical layer is called as PHY, one end of the MAC chip is connected with the PCI bus of the computer, and the other end is connected with the PHY chip. The network transmission process comprises the following steps: after receiving an IP packet (or a packet of another network layer protocol) from the PCI bus, the MAC splits and repacks the IP packet into a maximum 1518Byte, and sends a frame of a minimum 64Byte to the PHY. When the PHY receives the data from the MAC, the PHY converts the parallel data into serial stream data, encodes the data according to the encoding rule of the physical layer (NRZ encoding of 10 base-T or Manchester encoding of 100 base-T), and converts the data into analog signals to send out.

The RAM is a random access memory and has the characteristics that the stored content can be randomly taken out or stored in according to the requirement, and the access speed is irrelevant to the position of the storage unit.

Example 1:

fig. 1 is a whole data transmission system architecture, which includes multiple components of an MAC layer, a PHY layer, a PCI control layer, and a control signal processing layer.

The PHY layer is used for linking the MAC layer and the IO interface, OFDM algorithm processing is carried out on data processed by the MAC layer, data transmission is carried out on different channel data according to different frequency bandwidths, a single-channel baseband signal occupies 5Mhz bandwidth, a protection interval is reserved between every two frequency bandwidths, and therefore every two channels of data are independently separated, and the purpose is achieved without mutual influence. And carrying out data reduction on data input by the IO port, and carrying out down-conversion and down-sampling on the received wireless data stream to obtain all eight self-channel data. The eight subchannel banded data is independently signal detected, demodulated and decoded. And carrying out parallel-serial conversion and other operations on the bits obtained by demodulation and decoding to obtain a logic frame data stream. In the demodulation and decoding process, interference caused by the ordinary 1553 data may exist, and additional interference removal work is needed.

The PCI control circuit comprises a PCI communication bridge, an FPGA internal PCI control sampling IP core and a DMA control circuit. In the system, an external PCI chip is not used, an external linker is directly connected with the FPGA pin, and an IP is used for data sampling transmission and mainly used for a communication link of upper-layer user command information and data.

The control signal processing circuit is mainly used for processing some control information and effectively tracks and controls the working conditions of a PHY layer and an interface of an MAC layer of the whole project.

The framing of the mixed service is realized at the MAC layer. The specific function implementation of the MAC layer is shown in example 2.

Example 2:

in this embodiment, a MAC transmitting end and a MAC receiving end are taken as examples to describe a MAC layer.

The main circuit of the transmitting end or transmitting end circuit of the MAC layer comprises a transmitting end data frame storage and frame sealing module, a channel cache module and a data transmitting module, and the receiving end or receiving end circuit of the MAC layer comprises a receiving end data receiving module, a channel cache module and a data frame framing storage module.

The MAC layer transmitting end or transmitting end circuit mainly realizes user frame slicing and frame sealing: the main realization relies on:

the storage and framing module is used for caching a user frame issued by an upper layer user side, converting 32-bit wide data into 8-bit wide data, crossing clock domains, slicing the user frame according to different frame types, dividing the user frame into a plurality of logic data frames, and sequentially filling the logic data frames into a channel which is allowed to be written by upper layer control. The channel control signal is configured by the upper layer user, the lower layer control signal processing circuit manages uniformly, and the control information can be different in different time periods.

The transmitting channel cache module caches a plurality of logical frame data and spans a clock domain, and converts byte data stream into bit data stream. The clock rate at the write end of the channel is much higher than the read end rate, so that data can be written rapidly, and the working rate of the whole system is improved. The number of the logic frame writing channels depends on parameters configured by an upper layer user, the number of the channels is minimum 1 and maximum 8, when the 8 channels are fully opened and the logic frame transmitted by each channel is transmitted in full load, the system data transmission rate is maximized, and when one channel is opened, the rate is changed along with the data amount of the load section of the logic frame.

Further, the circuit work flow of the transmitting terminal buffer frame sealing module is as follows:

step 1: user frames sent by an upper layer are cached in a Random Access Memory (RAM), the RAM is divided into a plurality of areas, and each frame of data needs to be isolated.

Step 2: and reading the frame head of the data frame, and distinguishing the frame types.

And step 3: and gradually reading the data in the buffer area to form a logic frame, and labeling the first frame and the last frame when the logic frame is formed.

And 4, step 4: the data frames are written into the channels in turn, and one channel writes one frame of data frame.

The MAC layer receiving end or receiving end circuit mainly realizes the restoration of the logical frame to the user frame: the realization mainly depends on:

the receiving channel cache module caches the bit stream data, converts a single bit into a multi-bit data stream, and spans a clock domain. The number of the opening channels is configured by the upper layer user and is consistent with the number of the channels for receiving data currently, so that the data can be completely and correctly received. In order to make the channel control information of the sending end consistent, the channel signals are uniformly distributed under upper layer scheduling, and the channel information of all communication systems at the same time is consistent. The read port, like the write port at the transmitting end, needs to use a high-frequency clock signal for data processing, and reads data as fast as possible.

The receiving end data buffer framing module recombines the logic frames to restore the logic frames to user frames, and correct user frames cannot be restored due to the fact that data transmission errors exist in wireless data transmission, and at the moment, the user frames with errors need to be deleted and are not uploaded. Each time a correct frame is stored, a specific byte is added at the end of each frame to separate the previous frame data from the next frame data, so that the upper layer can simply and correctly process the data frames. When there is enough data in the buffer memory, it needs to report the interrupt to the upper layer to read the lower layer data, or when the data quantity is insufficient but the interrupt is overtime, it reports an interrupt to the upper layer.

Further, the circuit work flow of the receiving end storage and framing module is as follows:

step 1: and the lower layer transmits a logic frame, and when the module identifies the first frame, the frame header information is recorded as the frame header of the whole current user frame.

And 2, step: and writing the frame header and the load information of the first frame into the RAM, writing the load information of the intermediate frame and the tail frame into the RAM, and recording and latching the address written by the first byte of the first frame. Before receiving the end piece frame, if other types of data frames which are not the middle piece frame appear, the data of the frame is wrong, and the frame is abandoned to the initial state to wait for the appearance of the next first frame.

And step 3: after receiving the end frame, judging whether the user frame load quantity is correct, and if the user frame load quantity is correct, adding a frame end mark at the end of the frame. And if the data is incorrect, the write address returns to the lock address again, and the writing of the next frame of data is restarted, which represents that the written error frame is discarded.

And 4, step 4: when the condition is met, the report is interrupted, the write address of the next frame is separated from the data of the current frame, and the software reads the data upwards.

Fig. 2 is a schematic structural diagram of a framing circuit and a method for hybrid services according to an embodiment of the present invention. In this implementation, the main framing and framing circuit includes a buffer framing module, a sending channel module, a data transmitting module, a data receiving module, a receiving channel module, and a receiving buffer framing module. The buffer framing module, the sending channel module and the data transmitting module are sequentially connected in series, so that logical frame framing is carried out after the buffer framing module receives an upper data frame, the logical frame framing is sequentially written into the channel module, and then the data in the channel is read out through the transmitting module, various operations are carried out on the data, and then the data are transmitted into a lower layer. The data receiving module, the receiving channel module and the receiving buffer framing module are sequentially connected in series, data are written into the channel module after the receiving module receives the data and carries out certain processing, the channel module carries out conversion processing of data streams, the buffer framing module reads out data frames and carries out framing processing, the data frames are restored to be in a user frame format to be buffered, and the data are uploaded when specific conditions are met.

Further, the buffer framing module is used for data buffering and user frame framing, and a specific implementation method is shown in fig. 3. The data frames sent down by the upper layer are cached by the RAM, the RAM is a chip area according to the byte space of each 1K in the memory space, the frame data are stored in sequence, the beginning byte of each frame must be at the starting address of the chip area, namely the data volume of the previous frame is not integral multiple of the storage number of the chip area, and the address jumps to the next chip area to write the next frame data after the data is written.

RAM data storage is shown in fig. 4. Therefore, the write-in end and the read-out end of the RAM can judge whether data still exist in the RAM by using the pointer under the condition that the data bit width is different. When the two pointers are not equal, the data reading end can start to read data. Reading the frame header information according to a frame format defined in advance, carrying out frame judgment, then entering a user frame framing device, reading data in the cache according to different frame types, and carrying out framing again according to the user frame format to form a logic frame with a shorter load section. The specific framing manner is shown in fig. 5. And writing each logical frame into one effective channel, stopping writing when all the effective channels are written with the logical frames, and waiting for the next round of writing.

Furthermore, the channel cache module is composed of 8 asynchronous RAMs, and each RAM represents a data channel. It only serves as a buffer for data and a conversion of data bit width.

Furthermore, the data transmitting module reads the data in the channel according to a certain rule, so that the PHY layer can conveniently perform OFDM algorithm processing.

Furthermore, the data receiving module writes all eight self-channel data obtained by performing two-stage filtering, time domain synchronization, signal detection and down-conversion and down-sampling on the PHY layer into the channel control module.

Further, the buffer framing module combines the logical frames transmitted from the lower layer into user frames and puts the user frames into the RAM for buffering. The lower layer logic frames are input frame by frame according to the data stream, and a certain guard time interval is arranged between every two frames, so that the frames are convenient to combine. The lower layer only inputs the frames which are set by OFDM and QPSK and need to be uploaded, and the frames which do not need to be input exist, and the frames are only command frames of each module. When the module receives the data frame, it starts to judge, the head frame information of the logic frame carries the head frame information, the module enters into the user frame sealing device to make user frame group. Normally first the first frame, then the intermediate frame, then the last frame, there may be multiple intermediate frames, or none. Because of the frame error rate and the bit error rate in the wireless communication field, the situation that the whole frame data is discarded can not occur as long as the frame header data is correct in the transmission process of the data frame, the frame type and the length information are correct in the transmission process of the data frame, and the data can be spliced into a complete user frame without frame loss. When other types of data frames are received between the last frame and the first frame, the current frame can be judged incorrectly, and the current frame can be discarded. The two frame processing modes of OFDM and QPSK are basically consistent. A certain byte is added behind each correct frame to play a role of data frame isolation. The specific framing manner is shown in fig. 6 and 7.

And reporting and interrupting the software after receiving a sufficient number of frames, wherein the reporting and interrupting need to be carried out before the next frame is received and the data frame is not required to be received any more when the reporting and interrupting are carried out, and the upper layer can read the complete data frame after each reporting and interrupting. When no data exists for a long time and the data in the RAM has the number of the interrupt which cannot be reported, the judgment of the timeout interrupt is carried out.

Claims (2)

1. An FPGA chip is characterized in that an MAC transmitting terminal and an MAC receiving terminal are integrated in the chip;

the MAC transmitting terminal is stored with a first computer program, and the first computer program is executed by a processor according to the following steps:

step 1, caching a user frame issued by an upper layer, wherein the user frame comprises a user frame header and a user frame load, and framing the cached user frame into a first frame, a plurality of intermediate frames and a tail frame according to the user frame header, wherein the first frame and the tail frame are marked during framing; the first frame comprises a first frame header and a first frame load, the intermediate frame comprises an intermediate frame header and an intermediate frame load, and the tail frame comprises a tail frame header and a tail frame load; the first frame, the intermediate frame and the end frame are all logic frames;

step 2, sequentially writing the logic frames into a transmitting end cache channel respectively, crossing clock domains, and converting the logic frame byte data stream into a bit data stream;

step 3, reading out and transmitting the logic frame in the buffer channel of the transmitting terminal;

in the step 1, the user frame is cached in the RAM, the memory space of the RAM is divided into a plurality of areas, each area occupies 1 kbyte, the user frame is stored in the RAM, the larger the user frame is, the more the number of the occupied areas is, and the first byte of each frame of the user frame is located at the start address of the area;

in the step 2, the number of the transmitting end cache channels is configured by the user end, and the number is between 1 and 8;

the MAC transmitting/receiving end stores therein a second computer program, and when executed by the processor, the second computer program implements the following steps:

step a, receiving a logic frame bit data stream;

b, converting the received logic frame bit data stream into multi-bit data, writing the multi-bit data into a receiving end cache channel and crossing a clock domain, wherein the receiving end cache channel configuration corresponds to the transmitting end cache channel configuration;

c, identifying the logic frame in the buffer channel of the receiving end to determine a first frame, using the head of the first frame as the head of a user frame, using the load of the first frame, the load of an intermediate frame and the load of a tail frame as the load of the user frame to frame, and restoring the user frame;

in the step c, the address written by the first byte of the first frame is locked during framing, after the user frame is restored, whether the load quantity of the user frame is correct or not is judged, and if the load quantity is correct, a frame ending mark is added at the tail of the user frame; and if the data is incorrect, deleting the wrong user frame, returning to the locked address, and restarting to write the next frame of user frame data.

2. A data transmission system comprises an MAC layer, a PHY layer, a PCI control layer and a control signal processing layer, and is characterized in that the MAC layer comprises an MAC transmitting end and an MAC receiving end;

the MAC transmitting end has a first computer program stored therein, the first computer program being executed by a processor according to the following steps:

step 1, caching a user frame issued by an upper layer, wherein the user frame comprises a user frame header and a user frame load, and the cached user frame is encapsulated into a first frame, a plurality of intermediate frames and a tail frame according to the user frame header, and the first frame and the tail frame are marked during frame encapsulation; the first frame comprises a first frame header and a first frame load, the intermediate frame comprises an intermediate frame header and an intermediate frame load, and the tail frame comprises a tail frame header and a tail frame load; the first frame, the intermediate frame and the end frame are all logic frames;

step 2, sequentially writing the logic frames into a transmitting end cache channel respectively, crossing a clock domain, and converting the byte data stream of the logic frames into a bit data stream;

step 3, reading out and transmitting the logic frame in the buffer channel of the transmitting terminal;

in the step 1, the user frame is cached in the RAM, the memory space of the RAM is divided into a plurality of areas, each area occupies 1 kbyte, the user frame is stored in the RAM, the larger the user frame is, the more the number of the occupied areas is, and the first byte of each frame of the user frame is located at the start address of the area;

in the step 2, the number of the transmitting end cache channels is configured by the user end, and the number is between 1 and 8;

the MAC transmitting and receiving end stores a second computer program, and when executed by the processor, the second computer program implements the following steps:

step a, receiving a logic frame bit data stream;

b, converting the received logic frame bit data stream into multi-bit data, writing the multi-bit data into a receiving end cache channel and crossing a clock domain, wherein the receiving end cache channel configuration corresponds to the transmitting end cache channel configuration;

c, identifying the logic frame in the buffer channel of the receiving end to determine a first frame, using a head of the first frame as a head of a user frame, using a load of the first frame, a load of an intermediate frame and a load of a tail frame as a load of the user frame to frame, and restoring the user frame;

in the step c, the address written in the first byte of the first frame is locked during framing, after the user frame is restored, whether the load quantity of the user frame is correct or not is judged, and if the load quantity is correct, a frame ending mark is added at the tail of the user frame; if not, deleting the wrong user frame, returning to the locked address, and restarting to write the next frame of user frame data;

the PHY layer is used for linking the MAC layer and the PCI control layer, OFDM algorithm processing is carried out on data processed by the MAC layer, and data transmission is carried out according to different frequency bandwidths;

the PCI control layer is used for a communication link of command information and data of an upper layer user side;

the control signal processing layer is used for tracking and controlling the MAC layer, the PHY layer and the PCI control layer and configuring a receiving end cache channel and a transmitting end cache channel.

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