KR100242692B1 - Input apparatus for pulse code modulation data - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse code modulation data input device suitable for converting serially input PCM data in parallel and providing the same, and according to the related art, a serial signal is directly received and received by a digital signal processor. There was a flaw that the channel designation signal should be generated and input externally, and when the digital signal processor receives the input signal, the interrupt is automatically generated inside the digital signal processor. Therefore, the digital signal processor stops all operations before the interrupt is generated. Although there is a drawback to be in an interrupt waiting state, the present invention provides a device capable of simultaneously converting and storing serially input PCM data and simultaneously providing PCM data with corresponding channel information, and optionally using a digital signal processor. Poems The present invention provides an apparatus for reading and processing PCM data, and the digital signal processor can easily determine whether data is stored or not by receiving a new data input indication signal (BIO: Brench Control Input). It can improve the shortcomings.

Description

Pulse code modulation data input device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse code modulation (PCM) data input device, and more particularly, to a pulse code modulation data input device for converting serially input PCM data in parallel.

In the prior art, since a serial signal is directly input from an input unit and a signal is processed, a digital signal processing unit has a drawback to generate and input a receiving channel designation signal externally. Because the signal is automatically generated inside the digital signal processing unit, the digital signal processing unit has a drawback that all operations must be stopped and the interrupt standby state before the interrupt is generated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and provides a device for reading and processing PCM data at any time in a digital signal processor after converting and storing serially input PCM data in parallel. There is a purpose.

Another object of the present invention is to provide an apparatus capable of simultaneously providing the corresponding channel information of the PCM data input to the digital signal processing apparatus with the PCM data.

Another object of the present invention is to provide an apparatus for confirming whether new data is stored according to a branch control input signal of a digital signal processor.

In order to achieve the above object, the present invention provides a parallel-to-parallel converter that converts the input serial PCM data (SIN) into parallel PCM data and outputs the same, and generates a divided signal with the input 2M clock and frame synchronization (FS) signals. A divider, first and second latches for latching the outputs of the divider and the serial-to-parallel converter 104, first and second buffers for receiving and storing signals from the latch, and outputs at the time of serial signal input ( D-flip-flop with Q) high and the output Q low when reading the signal from the digital signal processor, and a digital signal processor for receiving PCM data and extracting necessary information. Provided is a pulse code modulation data input device, characterized in that consisting of.

1 is a block diagram showing a pulse code modulation device according to the present invention;

2 is a waveform diagram showing a waveform of a signal for inputting an 8-bit pulse modulated code in the serial-to-parallel converter according to FIG. 1;

3 is a signal waveform diagram for inputting channel information to a digital signal processor in the divider according to FIG. 1;

<Description of the code | symbol about the principal part of drawing>

102 Inverter 104 Serial-to-parallel converter

106, 114: 1st, 2nd latch 108, 116: 1st, 2nd, buffer

110: digital signal processing unit 112: divider

118 D-flip flop

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings by those skilled in the art.

Referring to the configuration of FIG. 1, a serial-to-parallel converter 104 converting serial PCM data into parallel PCM data, a divider 112 for generating a divided signal with an externally input 2M clock and a frame synchronization signal, and a divider. And first and second latches 106 and 114 for latching the output of the serial-to-parallel converter 104, and first and second buffers 108 for receiving and storing signals from the latches 106 and 114 described above. 116 and a D-flip-flop having the output Q high when the serial signal is input, and the output Q low when the signal is read by the digital signal processing unit 110. 118 and a digital signal processing unit 110 for receiving PCM data and extracting necessary information.

Hereinafter, with reference to the accompanying Figures 1 to 3, a preferred embodiment of the present invention will be described in detail.

The serial-to-parallel converter 104 converts the serial pulse code data inputs in parallel in accordance with a clock signal and outputs signals up to signals Q0-Q7.

The divider 112 receives the frame synchronization signal and the 2M clock signal input from the outside via the inverter 102 and generates signals from the signals SQ3 to SQ7.

The first latch 106 receives the outputs Q0 to Q7 of the serial-to-parallel converter 104 and latches them at the instant when the clock pulse signal is converted from low to high.

The second latch 114 receives the signals of the divider outputs SQ3 to SQ7 and latches them at the moment when the clock pulse signal is converted from low to high.

The first buffer 108 buffers the pulse code modulation data stored in the first latch 106. That is, when the input / output selection signal IOSEL output from the digital signal processing unit 110 is low, the signal is output and transmitted to the digital signal processing unit 110, and the input / output selection signal IOSEL is high. If no data is output.

The digital signal processor 110 receives PCM data from the first buffer 108 and extracts necessary information.

The second buffer 116 buffers the pulse code modulation data stored in the second latch 114. That is, when the input / output selection signal IOSEL output from the digital signal processing unit 110 is low, the signal is output and transmitted to the digital signal processing unit 110. When the input / output selection signal IOSEL is high, data is output. I never do that.

The digital signal processor 110 receives channel (CH) information data from the second buffer and extracts necessary information.

The D-flip-flop 118 transmits a new data input display signal (BIO: Brench Control Input) to the digital signal processor 110 according to the control of the signal SQ2 output through the divider 112. The signal processor 110 may check whether new data is input.

The digital signal processing unit 110 checks the new data input display signal BIO, and if the signal is low, waits until it changes to high, and if the signal is high, new data is input. After the determination, the input / output selection signal IOSEL is output low, and the contents of the first and second buffers 108 and 116 are read.

The digital signal processor 110 utilizes the contents of the second buffer 116 as channel information and uses the contents of the first buffer as input PCM data to perform digital signal processing.

After reading the contents of the first and second buffers 108 and 116 in the digital signal processing unit 110, the new data input display signal BIO changes to Low and low until the next new data is input. Maintain state.

2 is a waveform diagram showing a waveform of a signal for inputting an 8-bit pulse modulated code in the serial-to-parallel converter 104, (2a) showing a divider 112 and a serial as a frame synchronization signal (FS). Supplied to the parallel converter 104, 2b is supplied to the divider 112 as a 2M clock signal, and is supplied to the serial-to-parallel converter 104 as PCM serial input data (SIN) of (2f). do.

The divider 112 divides the input signals of (2a) and (2b) to generate and output divided waveforms from (2c) to (2e). The resulting waveform of (2e) is divided by 1/8 with respect to the 2M clock signal and operates in an 8-bit period. The waveform inverting the divided (2e) formed signal is used as a clock pulse for the first latch 106, the second latch 114, and the D-flip-flop 118, respectively. ) Is received at each of the first latch 106 and the second latch 114.

Since the serial-to-parallel converter 104 needs time to make the PCM serial input data SIN of (2f) into parallel data, it outputs with a delay time of one channel. In the first latch 106, one channel delayed data Q0-Q7 of (2g) is received from the serial-to-parallel converter 104, and the received data Q0-Q7 is latched for each channel of (2h). In the first latch 106, the selection signal is grounded, and therefore, the received data Q0-Q7 is always transmitted to the first buffer 108.

In addition, since the second latch 114 receives the information data Q0-Q4 of the corresponding channel delayed by one channel, the information Q0-Q4 of the corresponding channel is stored in the second buffer 116 as in the first latch 106. Is entered.

The waveform / SQ2 of (2e) received by the D-flip-flop 118 generates and transmits a new data input representation signal BIO of (2k) to the digital signal processing unit 110 in an eight-bit period. In the digital signal processing unit 110, each of the first buffer 108 and the second buffer 116 is input by the input / output selection signal (IOSEL: Input Output Selection) of (2j) with the branch control signal BIO shown in FIG. 2L. Enable to receive desired data and channel information.

3 is a waveform diagram illustrating a waveform of a signal for inputting channel information to the digital signal processing unit 110 in the divider 112, and FIG. 3A is a frame synchronization signal FS which is a synchronization signal. The waveform passed through the divider 112 is divided in the form of multiples of two, and in the case of (3f), it is divided into 1/256 of up to 2 MHz.

The waveform divided in (3b) to (3f) shows information of 2 ⁵ , which contains 32 channel information.

As described above, the present invention provides a device capable of simultaneously converting and storing serially input PCM data and receiving PCM data together with corresponding channel information, thereby allowing the PCM data at any time in the digital signal processor. The present invention provides an apparatus for reading and processing a digital signal processor, and the digital signal processor receives a new data input representation signal BIO to easily determine whether data is stored or not.

The principles of the invention have been described above in connection with specific devices, which are described by way of example only, and are not limited to the spirit of the invention as described in the appended claims.

Claims (3)

A serial-to-parallel converter 104 for converting the input serial PCM data SIN into parallel PCM data and outputting the same; A divider 112 for generating a divided signal with an input 2M clock and frame synchronization (FS) signal, First and second latches 106 and 114 for latching an output of the divider 112 and the serial-to-parallel converter 104; First and second buffers 108 and 116 which receive signals from the latches 106 and 114 and store them; A D-flip-flop 118 that sets the output Q high when the serial signal is input, and sets the output Q low when the signal is read by the digital signal processor 110, Pulse signal modulation data input device comprising a digital signal processing unit (110) for receiving PCM data and extracting necessary information. The method of claim 1, The serial-to-parallel converter (104) converts the PCM serial input data (SIN) into parallel data and outputs the delay signal of one channel to the first latch (106). The method of claim 1, The divider (112) makes channel information (SQ3-SQ7) parallel data and outputs the second latch (114) with a delay time of one channel.

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