KR930004860B1 - Interconvert instrument of pcm/adpcm data - Google Patents

Abstract

The apparatus converts mutually PCM and ADPCM having matching ability with a conventional I/O device and improved efficiency of transmission and memorizing. It includes a central controlling section (110) for controlling the apparatus, a time slot control section (120) for generating the frame synchronizing signal of time slots, a PCM decoder (130) for converting analog signal to μ-P PCM signal or reversely, and ADPCM transcoding section (150) for transmitting the μ-P PCM signal to the central controlling section (110) or the ADPCM data to the PCM decoder (130), and a PCM matching section (140) for matching the output of the PCM decoder (130) to a PCM subway.

Description

PCM / ADPCM Data Interconverter

1 is a block diagram of a PCM / ADPCM data interchange apparatus according to the present invention.

2 is a signal waveform diagram of an ADPCM transcoder unit according to the present invention.

3 is a block diagram of a timeslot control unit according to the present invention.

4 is a signal waveform diagram of each part of FIG.

5 is a format diagram of timeslot control data.

6 is a block diagram of a PCM coder according to the present invention.

7 is a signal waveform diagram of each part of FIG.

8 is a configuration diagram of a PCM matching unit according to the present invention.

9 is a block diagram of a clock supply unit according to the present invention.

* Explanation of symbols for main parts of the drawings

110: central control unit 120: timeslot control unit

130: PCM abbreviation code 140: PCM matching part

150: ADPCM transcoder unit 160: clock supply unit

210: control data latch 220,240: shift register

230: D flip-flop 250: AND gate

310: timeslot assigner 320: PCM decoder

VR1: Variable resistor 510: PCM data direction controller

520: PCM signal transceiver

According to the present invention, when an analog signal is converted into digital data and signal processed or stored through a Pulse Code Modulation (PCM) decoder, the differential low-frequency (M-law) PCM data is reduced. Pulse Code Modulation) or PCM / ADPCM data interconversion device for converting ADPCM data into mu-low PCM data.

In general, the PCM method has a transmission rate of 64 Kbps (kilo-bit per seccond), but the ADPCM method is generally adopted at 32 Kbps, which is half of it. Therefore, the PCM scheme is disadvantageous in terms of bandwidth at the time of transmission, and requires a relatively large memory capacity even when storing data.

Accordingly, an object of the present invention is to provide a PCM / ADPCM data transconverter for matching with an existing input / output device and increasing transmission efficiency and storage capacity.

In order to achieve the above object, the present invention converts mu-low PCM data into ADPCM data with reduced bandwidth or converts ADPCM data into mu-low PCM data when the analog signal is converted into digital data and processed or stored. A mutual conversion apparatus, comprising: central control means for controlling the entire PCM / ADPCM data mutual conversion device, connected to the central control means, and digitally assigned to an assignment channel of a signal line time-division multiplexed into 32 time slots with control data of the central control means; PCM decoding means for converting an analog signal into a mu-low PCM signal or a mu-low PCM signal into an analog signal, connected to a time slot control means for carrying data, said central control means and a PCM decoding means. The central control by converting the mu-low PCM signal of the PCM decoding means into ADPCM data ADPCM transcoder means loaded on the data bus of the means or receiving ADPCM data on the data bus and converting it into a mu-low PCM signal and outputting to the PCM decode means, connected to the central control means, PCM decode means and ADPCM transcoder means. And PCM matching means for matching the signals output from the ADPCM transcoder means and the PCM decoding means to the PCM subhighway.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of a PCM / ADPCM data conversion apparatus according to the present invention, 110 is a central control unit, 120 is a time slot control unit, 130 is a PCM decoder, 140 is a PCM matching unit, 150 is an ADPCM transcoder unit , 160 denotes a clock supply unit, respectively.

PCM / ADPCM data conversion apparatus according to the present invention, as shown in Figure 1, the central control unit 110, time slot control unit 120, PCM decoding unit 130, PCM matching unit 140, ADPCM transcoder The unit 150, and the clock supply unit 160.

The central controller 110 is connected to the timeslot controller 120, the PCM matching unit 140, the ADPCM transcoder unit 150, and the clock supply unit 160, and is configured as a general-purpose central processor to form the timeslot controller 120. ) And the PCM matching unit 140 and the ADPCM transcoder unit 150.

The timeslot control unit 120 is connected to the central control unit 110, the clock supply unit 160, and the PCM decoding unit 130 to receive the control data of the central control unit 110 to receive the PCM decoding unit 130. In order to control, a time slot frame synchronization signal for carrying digital data on an assignment channel of a time division multiplexed signal line into 32 time slots is generated and supplied to the PCM decoder 130.

The PCM decoding unit 130 is connected to the timeslot control unit 120, the PCM matching unit 140, the ADPCM transcoder unit 150, and the clock supply unit 160 to convert an analog signal into a mu-low PCM signal. To the ADPCM transcoder 150, or vice versa to convert the mu-low PCM signal received from the ADPCM transcoder 150 into an analog signal.

The PCM matching unit 140 is connected to the central control unit 110, the PCM decoding unit 130, the ADPCM transcoder unit 150, and the clock supply unit 160 to the ADPCM transcoder unit 150 and the PCM decoding unit. A function of matching the signal output from the 130 to the PCM subhighway is performed.

The ADPCM transcoder unit 150 is connected to the central control unit 110, the PCM decoding unit 130, the PCM matching unit 140, and the clock supply unit 160 to receive a mu-low PCM signal and convert the ADPCM data. Put on the data bus of the central controller 110 or vice versa to receive ADPCM data from the data bus and convert it to a mu-low PCM signal and then send the mu-low PCM signal to the PCM decoder 130; do.

FIG. 2 is a signal waveform diagram of the ADPCM transcoder unit 150 according to the present invention. The ADPCM transcoder unit 150 according to the present invention includes a PAL (Programmable Logic Array), so that timing characteristics as shown in FIG. Receives the ADPCM transcoder selection signal, the central control address bus, the central control data bus, the central control read (RD), and the write signal (WR) from the central control unit 110, and the maximum speed of the ADPCM clock is 8.192 MHz. Is used.

The contents of the internal data register or status register are output to the data terminals D7-D0 of the ADPCM transcoder. The contents of the data register may be instructions for controlling the ADPCM transcoder unit 150 to operate as an encoder or a decoder, regardless of ADPCM data. By the way, the contents of the status register are state information in which the ADPCM transcoder unit 150 is operated.

The serial input / output terminal is designed to match the inverted serial clock signal of PCM subhighway clock (CLK), ADPCM transcoder sample signal (SMPL), serial-input enable signal (SIEN), and serial output enable signal (SOEN). SI and SO) input and output 8-bit serial PCM signals.

That is, when the ADPCM transcoder unit 150 is operated as an encoder, two PCM data 1201 and 1203 each consisting of 8 bits are input to a serial input terminal (SI), so that one ADPCM data 1204 composed of 8 bits is provided. ) Is output to the data terminal and loaded on the central control unit data bus, and when operated as a decoder, one ADPCM data 1202 consisting of 8 bits is input to the data bus terminal and two PCM data consisting of each 8 bits (1205) (1206) and output to the serial output terminal (SO).

The state of the ADPCM transcoder control signal is as shown in Table 1 below, and in Table 1 below, X represents an arbitrary condition state.

TABLE 1

The clock supply unit 160 is connected to the central control unit 110, the timeslot control unit 120, the PCM decoding unit 130, the PCM matching unit 140, and the ADPCM transcoder unit 150, and is required for each functional block. Supplying a clock, the operation clock (Φ) of the central control unit 110, the PCM clock (CLK), the reference frame synchronization signal (FS), ADPCM clock, etc., the PCM clock (CLK) and the reference frame The synchronization signal FS is generated by itself or inputted from the PCM matching unit 140.

3 is a configuration diagram of the time slot control unit 120 according to the present invention, FIG. 4 is a signal waveform diagram of each part of FIG. 3, FIG. 5 is a format diagram of time slot control data, 210 is a control data latch, 220, 240 denotes a shift register, 230 denotes a D flip-flop, and 250 denotes an AND gate.

The timeslot control unit 120 according to the present invention connects the control data latch 210 and the D flip-flop 230 to the central control unit 110, as shown in FIG. The AND gate 250 is connected to the timeslot select signal TSAC-SEL and the output terminal of the control data latch 230, and the shift register 220 is connected to the output latch of the data latch 210 and the AND gate 250. The shift register 240 is connected to the output terminal of the AND gate 250.

The operation of the timeslot controller 120 will now be described with reference to FIG. 4.

The timeslot selection signal TSAC-SEL is input to the data input terminal D3 of the D flip-flop 230 and clocked at the rising edge of the operation clock Φ, as shown in FIG. The same output signal Q30 is obtained. In addition, the timeslot selection signal TSAC-SEL and the output signal Q30 of the D flip-flop 230 are logically multiplied through the AND gate 250 to enable parallel enable signals of the shift registers 220 and 240. PE2, PE4).

While the logic state of the parallel input enable signal PE4 of the shift register 240 is "0", all of the input signals D40 to D47 of the shift register 240 are at the rising edge of the operation clock. Loaded at " 0 " and loaded while the parallel input enable signal PE4 is in logic state " 1 ", the input signals D41 to D47 are converted into serial signals at the rising edge of the operation clock. The chip select signal CS, which is maintained at a logic state of "0", is generated during the period to be an output Q47 of the shift register 240 and input to the PCM decoder 130.

At the same time, the shift register 220 includes a time slot in parallel from the data latch 210 in a state in which the parallel input enable signal PE2 of the shift register 220 is a logic “0” like the shift register 240. Control data D0 to D7 become the serial output Q27 of the shift register 220 and are input to the decoder 130.

As shown in FIG. 5, the timeslot control data is allocated from the first to sixth bits D0 to D5 for channel selection, and the seventh and eighth bits D6 and D7 are frame synchronization for input / output PCM. Used to store signals FSR and FSX.

6 is a configuration diagram of the PCM coder 130 according to the present invention, FIG. 7 is a signal waveform of each part of FIG. 6, 310 is a time slot assigner, 320 is a PCM decoder, and VR1 is a variable resistor.

PCM coder 130 according to the present invention is configured by connecting the PCM decoder 320 to the time slot assigner 310 as shown in FIG.

The timeslot allocator 310 receives serial timeslot control data DC, a chip select signal CS, and an operation clock Φ from the timeslot control unit 120, and has a PCM subhighway clock of 2.048 MHz. CLK) and an 8KHz reference frame synchronization signal FS to generate an input PCM frame synchronization signal FSR and an output PCM frame synchronization signal FSX for the corresponding time slot, and transfer the result to the PCM decoder 320. Do it.

The PCM decoder 320 receives the input / output PCM frame synchronization signal (FSR, FSX) and the 2.048 MHz PCM clock (CLK) from the time slot assigner 31 and converts the digital PCM signal DR1 into an analog output signal. In addition, the output PCM frame synchronization signal FSX and the PCM clock CLK are used to generate an analog PCM audible signal DX1 by receiving an analog audible signal from the instrument of the apparatus.

The analog input signal of the PCM decoder 320 is non-inverted and amplified according to the distribution resistor size of the variable resistor VR1.

The operation of the PCM coder 130 will now be described with reference to FIG.

The output or input PCM audible signal starts at the falling edge of the frame synchronization signals FSX, FSR and is one cycle length of the PCM subhighway clock CLK. , Then D0.

8 is a configuration diagram of the PCM matching unit 140 according to the present invention, 510 is a PCM data direction control unit, and 520 is a PCM signal transmission and reception unit, respectively.

The PCM matching unit 140 according to the present invention connects the PCM data direction control unit 510 to the central control unit 110, the PCM decoding unit 130, and the ADPCM transcoder unit 150 as shown in FIG. 8. The PCM signal transceiving unit 520 is connected to the PCM data direction control unit 510.

The PCM data direction controller 510 is configured of a programmable array logic (PAL), a generic array logic (GAL), or a tri-state gate to receive a control signal from the central controller 110 and to receive the PCM from the ADPCM transcoder 150. The PCM data is transmitted to the PCM decoder 130 or the PCM signal transceiver 520, or vice versa. The PCM data from the PCM decoder 130 or the PCM signal transceiver 520 is transferred to the ADPCM transcoder 150. Deliver it.

The PCM signal transceiver 520 may be configured as a PCM differential signal transceiver, which transmits or receives PCM serial data as a differential signal to a PCM subhighway using a differential line driver / receiver. This is how the transmit or receive signal is represented in a "high" or "low" logic state by the potential difference between the two transmission signal lines, respectively.

In addition, the PCM signal transceiver 520 may be configured as a PCM single signal transceiver, and may be realized as a tri-state buffer of general TTL gates. This is how the transmitted or received signals are each represented by a single transmission signal line. When the differential signal transceiver is applied, it is a method used when the transmission environment is poor because the distance between the time switch on the opposite side and the apparatus of the present invention is relatively long as it is connected to the PCM subhighway, and when the single signal transceiver is applied, This method is used when the same distance is relatively short and there is little concern about signal level attenuation and external influence on transmission.

The PCM data direction controller 510 receives the data input / output selection signal, the remote / local selection signal, and the encoder time signal from the central controller 110 and receives the PCM data DR2 from the ADPCM transcoder 150. The output signal DR1 is output to the 130 as an input signal DR1 or the output signal DR to the PCM signal transceiver 520. On the contrary, the PCM data received from the PCM decoding unit 130 or the serial data output signal DX1 or from the PCM signal transceiving unit 520 as the input signal DX is output to the ADPCM transcoder unit 150. DX2). The PCM data direction controller 510 controls each direction as shown in Table 2 below according to an input control signal input from the central controller 110.

TABLE 2

9 is a block diagram of the clock supply unit 160 according to the present invention, 710 is a central clock operation clock generator, 720 is a self-clock generator, 730 is a clock selector, 520 is a PCM signal transceiver.

The clock supply unit 160 according to the present invention includes a central control unit operation clock generator 710, a self clock generator 720, and a clock selector 730.

The central control unit clock generator 710 connected to the central control unit 110 and the timeslot control unit 120 and the self clock generator 720 connected to the ADPCM transcoder unit 150 include a crystal oscillator and a counter. do.

The clock selector 730 is configured as a dual in line package (DIP) switch, and is connected to a self clock generator 720, a PCM signal transmitter 520, and a PCM decoder 130 of the PCM matching unit 140. Supply PCM clock CLK and reference frame synchronization signal FSP from PCM signal transceiver 520 and PCM clock CLKS and reference frame synchronization signal FSS from self-clock generator 720. The clock signal CLK is supplied to the PCM decoding unit 130 by selecting from CLKS and CLKP, and the reference frame sync signal FS is supplied to the PCM decoding unit 130 at the same time by selecting between the FSS and the FSP.

CLKS and CLKP may have different phases, but the waveform and frequency are the same, and 2.048 MHz is usually used, and similarly, FSS and FSP may have phase differences but the waveform and frequency are the same and 8 KHz is used. .

According to the present invention configured and operated as described above, the connection with the existing input / output device uses a PCM decoder, and the connection with the data processing device or the storage device can be matched by an ADPCM transcoder, thereby doubling in bandwidth. It has the advantage of having half the storage capacity, so the transfer efficiency is increased and the small capacity memory device can be used, or there is an application effect that can store data for a relatively long time in the memory device of the same capacity.

Claims (6)

A PCM / ADPCM data transconverter that converts mu-low PCM data into bandwidth-reduced ADPCM data or converts ADPCM data into mu-low PCM data when an analog signal is converted into digital data and processed or stored. Central control means 110 for controlling the entire data interconversion device, connected to the central control means 110, digitally assigned to the assigned channel of the time division multiplexed signal line into 32 time slots as control data of the central control means 110. Time slot control means 120 for generating a time slot frame synchronization signal for carrying data, and connected to the time slot control means 120 to convert an analog signal into a mu-low PCM signal or a mu-low PCM signal. Is connected to the PCM decoding means 130, the central control means 110 and the PCM decoding means 130, which converts the signal into an analog signal. Converts the mu-low PCM signal into ADPCM data and loads it on the data bus of the central control means 110 or receives ADPCM data from the data bus, converts it into a mu-low PCM signal, and outputs it to the PCM decoding means 130. Connected to the ADPCM transcoder means 150, the central control means 110 and the PCM decryption means 130, and the ADPCM transcoder means 150 from the ADPCM transcoder means 150 and the PCM decryption means 130. PCM / ADPCM data interconversion device, characterized in that consisting of the PCM matching means 140 for matching the output signal to the PCM subhighway. According to claim 1, wherein the central control means 110, the timeslot control means 120, PCM decoding means 130, PCM matching means 140 and ADPCM transcoder means 150 is connected in each of the means; PCM / ADPCM data inter-conversion device further comprises a clock supply means for supplying the clock required. The apparatus of claim 1 or 2, wherein the timeslot control means (120) is a data latch means (210) connected to the central control means (110), and a D flip-flop (230) connected to the central control means (110). A first shift connected to the central control unit 110 and the D flip-flop 220; the first latch connected to the data latch unit 210 and the logical multiplication unit 250 and the PCM decoding unit 130; And a second shift register means (240) connected to the register means (220) and the PCM decoding means (130) and the logical product means (250). 3. The time slot according to claim 1 or 2, wherein the PCM decoding means (130) is connected to the time slot control means (120) and outputs a frame synchronization signal (FSR, FSX) for input / output PCM to the corresponding time slot. A PCM / ADPCM data interconnector comprising a assignor 310 and a PCM decoder 320 connected to the timeslot assigner 310 to convert a PCM signal to an analog signal or to convert an analog signal to a PCM signal. Inverter. The PCM data direction control means (510) according to claim 1 or 2, wherein the PCM matching means (140) is connected to the central processing means (110), the ADPCM transcoder means (150), and the PCM decoding means (130). And PCM signal transceiving means (520) connected to the PCM data direction control means (130) to transmit and receive PCM signals. The clock supply means 160, the central control means 110 and the time slot control means 120 is connected to the operation clock generating means 710, ADPCM transcoder means 150 PCM / characterized in that it is composed of a clock generation means 720 connected to the self-clock generation means 720, and the PCM matching means 140 and PCM decoding means 130 and the self-clock generation means 720. ADPCM data interconverter.