KR900002383B1 - Time slot assignment circuit in time division multiplexing method - Google Patents

Abstract

The circuit for assigning the time slot in a Time Division Multiplexing (TDM) system of pulse code modulation (PCM) and continuously variable solpe delta (CVSD) modulation comprises a first inverting buffer (10) inverting the time slot data into the data easily countable by transmitting enable signal, a latch (20) latching and transmitting the time slot assignment signal utilizing the transmitting enable signal and a write signal as a clock signal, a counter (30) loading and counting the output signal of the latch by the frame synchronizing signal, and generating time slot assignment pulse, a second inverting buffer (40) converting and transmitting the output signal of the latch (20) to the CPU, and a timing controller (50).

Description

Time Slot Designator in Time Division Multiplexing

1 is a detailed block diagram of the present invention.

2 is a time slot number data type diagram.

3 is a detailed logic diagram of the 32-bit counter during the second.

4 is an operational waveform diagram for each part of FIG.

* Explanation of symbols for main parts of the drawings

10: first inverting buffer 20: counter

30: counter 40: second inverting buffer

50: timing control unit

The present invention relates to a time slot designation apparatus for time division multiplexing, and more particularly, to an apparatus capable of designating time slots for time division multiplexing in pulse code modulation and delta modulation.

A time slot assignment device (hereinafter referred to as TSAC) is a device that designates a subscriber's time slot located in the subscriber interface of the system using time division multiplexing (hereinafter referred to as TDM). Say.

Therefore, in the Pulse Code Modulation (hereinafter referred to as PCM) and Delta Variable (Continuously Variable Solpe Delta Modulation (hereinafter referred to as CVSD)) methods, channel data on the TDM highway should be assigned to the subscriber for each time slot.

In the PCM-TDM scheme, one frame has 32 timeslots, one timeslot has 8-bit code words, and the sampling frequency is 8KHZ.

f ₁ = f _s × N _CH × bits / CH

f _s : sampling frequency, N _CH : timeslot per frame, bits / CH: bits per time slot

Thus, the clock frequency of the PCM is 8KHZ × 32 × 8 = 2.048MHZ, one highway transmission speed is 2.048Mbps, and one timeslot is 3.096kHz (488.2ns × 8 bits).

In the CVSD-TDM scheme, one frame has 32 timeslots, one timeslot consists of 1 bit, and the sampling frequency can vary up to 10 ⁹ HZ.

If the sampling frequency is 32KHZ, it has a transmission speed of 1.02Mbps on one highway, and one time slot has a length of 976.5ns (976.5ns × 1 bit). If the sampling frequency is 16KHZ, it has a transmission rate of 512Kbps. One timeslot has a length of 1.953 ms.

As the time slot length of PCM-TDM method and CVSD-TDM method is different, it is difficult to designate time slot of CVSD-TDM method because it cannot be used as TASC of CVSD by using existing PCM TSAC for subscriber interface part of system. When TASC is used in PCM-TDM method, the self-time slot is found through the internal comparator, so the delay time is long, so the 8th bit of the control data, which is the time slot designation data, is shortened to prevent collision of other buses. However, data communication can be a cause of fatal error, and there is a problem of supplying CLKC and DC separately for time slot designation.

Accordingly, an object of the present invention is to provide a device capable of designating a time slot designation device in a PCM-TDM method or a CVSD-TDM method without changing the hardware configuration by configuring the time slot designation device in a simple circuit.

It is still another object of the present invention to provide an apparatus capable of assigning accurate data to a subscriber interface portion of a TDM system without loss of data.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 is a detailed block diagram according to the present invention, wherein the first inverting buffer 10 inputs time slot data output from a central processing unit (hereinafter referred to as a CPU) and inverts and outputs the appropriate data. A latch 20 for inputting the output of the first inverting buffer 10 and outputting the latch; a counter 30 for inputting the output of the latch 20 to output a time slot designation pulse at an accurate time; and the latch Input the output of the (20) to the second inverting buffer 40, the NAND gate (G ₁ -G ₂ ), the inverter (G ₃ ) to reverse the output so that the CPU can read the current enable timeslot number The timing controller 50 is configured to control the enable time of the latch 20 and the first inverting buffer 10 and the second inverting buffer 40.

2 is a time slot number form diagram, FIG. 3 is a logic circuit diagram of the 32-degree counter of FIG. 1, and FIG. 4 is a timing diagram showing the operation of each part of FIG.

Hereinafter, the present invention will be described in detail with reference to FIGS. 1, 2, 3, and 4 based on the above-described configuration.

The timeslot number data output from the CPU has the same form as the second diagram. That is, D ₀ -D ₄ bits of data bits (D ₀ -D ₇ ) represent timeslot numbers (0-31), D ₅ -D ₆ bits are not used, and D ₇ is used to assign and cancel timeslots. Indicates.

For example, you can specify timeslots when the D ₇ bit is at the "low" level and cancel the timeslots when at the "high" level.

In addition, the D ₀ -D ₄ bits represent time slot number data from the 0 th time slot to the 31 th time slot, and output predetermined time slot number data in order to designate a predetermined time slot in the CPU.

Transmit enable (TSEN) as shown in (b) of FIG. 4 (A) when arbitrary timeslot number data (D _0- D ₄ ) are output from the CPU as shown in (a) of FIG. 4 (a). The signal is input to the NAND gate G ₁ to invert to a "high" state and then to the "low" state through the inverter G ₃ to enable the first inverting buffer 10.

Therefore, the first inverting buffer 10 inverts the timeslot data D ₀ -D ₄ outputted from the CPU because the time slot in the correct position is generated when the counter 30 generates the timeslot designation pulse. To specify.

At this time, when the write (WE) signal as shown in (c) of FIG. 4 (a) is output from the CPU, the transmit enable signal is negatively multiplied by the NAND gate (G ₂ ), as shown in (d) of FIG. 4 (A). Since it is inputted as the clock signal of the latch 20, the time slot of the data D ₀ -D ₄ of the first inverting buffer 10 is inputted with the day XJ (D ₇ ) of the "low" level, which is designated data. The latch 20 is operated to latch output.

At this time, the output of the latch 20 (Q ₇ ) becomes the enable signal of the counter 30 so that the time slot can be designated or canceled and the latch output Q ₀ − of the time slot number data (D ₀ -D ₄ ). a counter (30, type Q ₄₎₎ operates as follows in a 32 binary counter.

The counter 30, which is enabled by the " low " level signal of the output Q ₇ of the latch 20, has a time slot data D ₀ -D when the frame synchronization signal FSX is input. ₄ ) is loaded in parallel to generate a timeslot pulse when all outputs of latches (F ₁ -F ₅ ) are "high", i.e. the counter value is 32.

In this case, one count means an increase of one timeslot and counts 32-N (N is timeslot designation number data) until a timeslot designation pulse occurs after the parallel day XJ load.

The reason for inverting the timeslot number data D ₀ -D ₄ output from the CPU in the first inverting buffer 10 is to allow the counter 30 to designate the timeslot designation position at the correct position.

In addition, when the CPU wants to know the timeslot number currently specified, the CPU outputs a transmit enable (TSEN) signal and a read (RE) signal, and outputs the latch 20 when the NAND gate G ₂ becomes "low". The input second inverting buffer 40 can be enabled and read.

In order to designate a CVSD-TDM time slot with a sampling frequency of 32 KHZ, it is assumed that the CPU outputs one timeslot number data among timeslot number data (0-31).

Therefore, since the timeslot day XJ (D ₀ -D ₄ ) from the CPU is output as ØØØØ 1 and inverted to 1111 ø in the first inverting buffer 10 and output as 1111 Ø in the latch 20, the counter is shown in FIG. When the frame synchronization signal (FSX) as shown in (B) of Fig. 1 is loaded in parallel and counted twice by 1.024MHZ clock as shown in (B) of Fig. 4 (B), the frame synchronization signal (FSX) as shown in Fig. 4 (B) Generates the timeslot designation pulse as shown in (D).

Also, in the case of the sampling frequency of 16KHZ, if the timeslot number data (D ₀ -D ₄ ) is øøøø1, the frame period is 16KHZ as shown in (b) (f) and (g) of FIG. Is 512KHZ, so time slot 1 can be designated and the PCM-TDM method with sampling frequency of 8KHZ also has a frame period of 8KHZ and clock frequency as shown in (B), (D), (K) and (Wave) in FIG. Since 256KHZ (one code consists of 8 bits), time slot 1 can be designated.

The above description is as follows.

(Table 1) (The parenthesis is the timing diagram of FIG. 4 (B).)

As described above, when specifying the time slots in the CVSD-TDM and PCM-TDM methods, it is possible to simply specify the clock cycle without changing the peripheral circuits, and it is possible to accommodate several TSACs in one IC. There is an advantage in that it can be customized with less allowance and does not need to use a clock called CLKC to write timeslot data in PCAC-TDM type TSAC.

Claims (1)

A time slot designation apparatus of a time division multiplexing system, comprising: a first inverting buffer (10) for inputting time slot number data output from a central processing unit and inverting the data to be suitable for counting due to a transmit enable signal; A latch 20 for inputting the output of the first inverting buffer 10 and the timeslot designation data output from the central processing unit to output the enable signal and the write signal as clock signals, and latching the latch signal; A counter 30 which loads a predetermined output of the signal by the frame synchronization signal, performs a predetermined counting by the clock, and generates a timeslot designation pulse, and an output of the latch 20 is input to transmit the enable signal and the read signal. A second inverting buffer 40 for inverting and outputting to the central processing unit, and a transmit enable signal and a write and read signal from the central processing unit. Apparatus characterized in that the group consists of a first inverting buffer 10 and a latch 20 and the second timing controller 50 for controlling the output timing of the inverting buffer 40.

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