SU1450096A1 - Pulse duration selector - Google Patents

Abstract

The invention relates to a pulse technique and can be used in synchronization devices of digital data transmission systems. The purpose of the invention — extending the functionality — is achieved by providing any integer multiplication coefficients specified by software by changing the input code. For this purpose, a programmable pulse counter 8, an element 6, a short pulse generator 3, a code bus 9 and a unit 2 of comparison and switching are additionally introduced into the device. In addition, the device contains N serially connected delay elements 1-1 ... 1-N, input bus 4, element OR 5, output bus 7. The comparison and switching operation is carried out when there is an (M + 2) - M input block 2 signal resolution. A flow chart of block 2 is provided in the specification. 1 3.p. f-ly, 2 ill. i (L 42 of 01 SO O) (plLZ.I

Description

The invention relates to a pulse technique and can be used in synchronization devices of digital data transmission systems. I The purpose of the invention is to extend the functionality by providing any integer multiplication factors specified by software by changing the input code.

FIG. 1 shows the electrical circuit of the device; I in FIG. 2 is a diagram of the execution of the comparison and switching unit I,

The multiplier of the following pulse frequency j contains N connected after I I elements of 1-1, 1-, 1-3, I ..., 1-N delays, the outputs of which i are connected to the corresponding inputs: unit 2 of comparison and switching, I () -th input of which is connected via I driver 3 short pulses I with input bus 4 and directly I with the first input of the element OR 5, the second I input of which is connected to the output; element 6, the output from the output bus-: 7, with the input of the first element 1-1; delays and from the counting (subtracting) input of a programmable counter 8 pulses, information inputs;. which is connected to the code bus 9, the recording input and the transfer output (exchange; ma) - with the (N + 2) -M input of the comparison unit; 2 and switching and with the first input of the AND 6 element, the second input of which is connected to the output of the unit 2 comparison and switching.

Block 2 of the cara.connection and commutation contains an element NOT 10, N elements ШШ-НЕ 11-1, 11-2, 11-3, ..., 11-N, Nb-triggers 12-1, 12-2, 12- 3,.,., 12-N, first 13 and second 14 elements OR, N elements 15-1, 15-2, 15-3, ..., 15-N, N-input element 16 And shaper 17 short pulse, with the first inputs of each of the elements OR NOT 11-1, 11-2, 11-3,. , -., 11-N and elements 15-1, 15-2, 15-3, ... .15-N are connected to the corresponding inputs of the unit 2 of comparison and switching, the second inputs of elements 1SHI-NOT 11-1, 11-2, 11-3, ./. , 11-N are connected through the element NOT 10 with the (N + 1) -M input of the comparison and switching unit 2, the (Y + 2) th input of which is connected via the short pulse shaper 17 to the installation (start) inputs of each of the ND-trig

five

0

geers 12-1, 12-2, 12-3,, .., 12-N, the information inputs of which are connected to the common bus, clock inputs - with the output of the corresponding element ШШ-НЕ 11-1, 11-2, 11-3 , .., 11-N, inverse outputs - with the corresponding input of the N-input element AND 16, the output of which is connected to the first input of the first element OR 13, the second input of which is connected to the direct output of the first D-flip-flop 12-1, output - with the second input of the first element And 15-1, the output of which and the outputs of the remaining elements And 15-2, 15-3, ...., 15-N are connected to the corresponding inputs of the second element OR 14, the output of which is n with the output of unit 2 comparison and switching, with direct outputs from the second to the Nth

D-flip-flops 12-2, 12-3,

12-n

five

0

five

0

five

0

five

connected to the second inputs of the corresponding elements And 15--2, 15-3, ..., 15-N.

The pulse frequency multiplier works as follows,

The code of the multiplication factor K minus one is preliminarily set on the information inputs of the counter 8, and the level of the logical unit is set at its transfer output. Unit 2 is designed to compare a sequence of time-shifted pulses arriving at each of its N inputs with an input pulse at its () -M input. As a result of the comparison, the output of block 2 is connected to the one of the N inputs at which the indicated pulses coincide.

The comparison and switching operation is performed when there is on the (N + 2) -M input of the block 2 a resolution signal, which is fed through the shaper 17 to the installation inputs of all ND flip-flops and translates the latter into a single state. The change in state of each of the ND flip-flops is further determined by the appearance of a pulse at the clock input of the corresponding D-flip-flop, which is the result of a comparison of the time position of the pulses at the (N + 1) -M input received at the input of the HE element 10, and shifted in the positive pulse mode at the inputs from the first to the Nth and. arriving at the first inputs of the elements OR NOT 11-1. 11-2, 11-3, ..., 1t-N, to the SEC inputs which receives an inverted signal from the (N + 1) -ro input. As a result of the comparison, the pulses of all the elements of OR-NOT appeared, except for the one in which the pulses coincided in time exactly. This means that only one of the ND-flip-flops does not change its state and retains the permission to pass pulses through the corresponding element AND to the output of block 2. In the initial state or if the initial pulse does not coincide with any of the N input pulses in block 2 Allowed the exit signal from its first input.

The device starts operation when the first pulse from the output of the imaging unit 3 through element 5 enters the bus 7 and to the input of the element J-1, from the output of which the impulse held for time U ,, goes to the first input of unit 2 and to the input of element 1- 2, at the output of which a pulse appears, delayed by time l, arriving at the second input of block 2 and at the input of element 1-3, and so on. Thus, pulses displaced relative to each other are formed at each of the N inputs of block 2. Since in the initial state in block 2 its first input is connected to the output, then first to the second input of element 5, through element 6, a pulse arrives, delayed by element

the input of element 1 is the most on N input shifted at each other impulse pulse (N + corresponding to the input of the bus 4 comparison and re 10 input to the output of the second coincided with the input, and the mind s cycle. In this case, the connection will be n 15 pa elements 1-1 through the i-th, the period in det will be determined in the elements of the rear and the delay in the element 20 ke 2. This is connected as long as the signal coincides with the goma of the i input.

The delay times 25 ki are chosen by the words fj and f gj, and the output of the cooTBetcTBeHHo and the output signal

thirty

in MX

Th

where is 35

odd integer chi Then for ale

which and sometime

B -2

40

1-1 at time

together with the delay in block 2 elements 5 and 6, the period of the output igula .- From the output of element 5, the pulse also arrives at the counting input of the counter 8, in which the code of the pulses passed through the code (K-1) contained in the last one on the bus 7.

The process of repeated passage of it- 45 (taking into account the sign): the pulse through element 1-1 continues until the contents of the counter 8 are reset. As a result, during the transfer of the signal, the signal changes from the logical unit to the ul, which prohibits the passage of retained pulses through the element and element 5 to the bus 7. This impulse

bich

- total cops For each delay, the time for the known time of the first element exceeds the tolerance

S.

vck

51

50

and known off

T values

from

at the same time, it moves to (Ы + 2) -th move of block 2, giving permission for equalization. The last of the series of impacted pulses, which zeroed the caterer 8, also goes to the input of the 1-1 element, then from its output to

Sr

55

If by programming the formation

then Di; i

).

fidix {

-

the input of the element 1-2 and so on, thereby forming pulses shifted in time relative to each other at the N inputs of the block 2. When a pulse appears at the (N + 1) -M input of block 2, corresponding to the next pulse at the bus 4 input, the operation of comparing and switching that input input to the output of block 2, the pulse of which coincided with the pulse (N + 1), begins -M is input and the multiply cycle continues. In this case, the group of elements 1-1, 1-2,. ,, from the first to the i-th, will already be connected to the feedback loop from the first to the i-th, the period of the output signal will be determined by the total delay in the delay elements from the first to the i-th and delays in elements 5 and 6 and in block 2. This connection is maintained until the arrival of the input signal coincides with another i-input.

The delay times of the delay elements are selected as follows. If fj and f gj, respectively, the input and output frequencies, then T and Tg, are cooTBetcTBeHHo periods of the input and output signals:

in MX

Th

 BOX

i-ey

where k

multiplication factor, any integer. Then for element 1-1:

Where

B -2

0

5 (with mark):

bich

- total delay in elements 5 and 6 and in block 2. For each subsequent delay element, the delay time is determined from the known temporal instability of the first delay element that exceeds the allowable value of LT ", (

 45 (with mark):

S.

vck

H

51

 four

50

4i

and known deviation

T values

from

Sr

five

V- If the program may require the formation of various T

then Di; i

).

fidix {

- (()

9th;

+

Claims (2)

Invention Formula I -. I 1. The following frequency multiplier 1 pulses, containing N sequences of hbHo connected delay elements, bsd bus and OR element, the output of the co- Iroporo is connected to the output bus. Characterized by the fact that, in order to expand functional capabilities, a programmable pulse counter, element i, a short pulse shaper, one bus and a comparator and com- partment unit, the first N inputs of which 15 are connected to the outputs of the corresponding delay elements, are entered into it. , (Ы + 1) th input is connected to the output of a short-kHx pulse former, the input of which is connected to the input bus, and to the first input 20 elements OR, the output of which is connected to the input of the first delay element and to the counting the input of the programmable counter | pulses, infor | The operational inputs of which are connected to the code bus, the recording input and the transfer output are from the (N + 2) -M input of the Comparison and Switching block and to the first stroke of the AND element, the output of which is connected to the second input of the CLI element, the second input is from output of the comparison and switching unit. : 2. Multiplier according to claim 1, characterized in that the comparison unit and 5;: the ommutation contains the element NOT, N elements OR NOT, ND-trigger25 thirty 2g 50 a ditch, (N + 1) elements AND, the first and second elements OR, a short pulse driver, (N + 2) inputs and one output, while (L + 1) -th input of the comparison and switching unit is connected to the input of the element NO, the output of which is connected to the first inputs of N OR-NOT elements, the output of each of which is connected to the C inputs of the corresponding first through Nth D-flip-flops, the direct outputs of the second through Nth of which are connected to the first inputs of the corresponding elements And, the outputs of the first to the Nth are connected to the N inputs of the second OR element, the output of which is the output of the comparison and switching unit, the inverse outputs of the ND flip-flops are connected to the N inputs of the (N + 1) -ro element I, whose input is connected with the first input of the first element OR, to the second input of which the direct output of the first D-flip-flop is connected, S-inputs 5 of each D-flip-flop is connected to the output of a short pulse shaper, whose input is the (N + 2) -M input of the comparison and switching unit, the D-slots of the ND-flip-flops are connected to 0 logical level zero, the inputs of the unit of comparison and switching from the first. on the Nth are connected to the second inputs of the corresponding elements And, the output of the first element IL is connected to the first input of the first element of the N elements I. Bx {L / 2) F i7 ) iO fi-h ii-5 ii-2 r // - / BX.N o-- 5l: J oh2 Bx.i Ln sixteen i2-2 r r 12-1 i5-n GL J r r I 1f1 Out l- 15-1 Fie.2