SU1396239A1 - Signal shaper with phase shifting - Google Patents

Abstract

The invention relates to radio engineering. Invention chain -. increase the range of phase shifts. The shaper contains a pulse generator 1, a counter 2, a switch 3, a counting trigger 4, a comparison block 5, a block 10 setting the phase shift parameters, a drive 11. To achieve the goal, shaper 6, 8 short pulses are entered into the shaper, element 7, ADC 9, accumulators 12, 14, decoder 3, comparison unit 15, three driver 16, 19, 20 control signals, key 17, switch 18, counters 21, 22, 23. Each code pattern at the output of the ADC 9 corresponds to a certain phase shift, which should receive a digital signal. The maximum phase shift that m. is obtained, is about two clock intervals in both directions. 6 Il.

Description

ff

SA.

v / x

oo with

05

Yu

oo with

Phi2.1

The invention relates to radio engineering and can be used as a signal generator with a phase shift, in particular, in devices for generating test signals.

The purpose of the invention is to increase the range of phase shifts.

FIG. Figure 1 shows the structural electrical circuit of the proposed signal conditioner with a phase shift; in fig. 2 - time diagrams of his work; in fig. 3 is a diagram of a first driver of control signals; in fig. 4 is a diagram of a second driver of control signals; in fig. 5 is a diagram of the third driver control signals; in fig. 6 is a block diagram for setting phase shift parameters.

The signal generator with a phase shift contains (Fig. 1) a pulse generator 1, a first counter 2, a first switch 3, a countable mp) igger 4, a first comparison unit 5, a first shaper 6 short pulses, an And 7 element, a second shaper 8 short pulses, analog-to-digital converter (ADC) 9, block 10 setting phase shift parameters, first 11 and second 12 drives, decoder 13, third drive 14, second comparison block 15, first driver 16 of control signals, key 17, second com.- mutator 18, the second driver 19 control with ignals, the third driver 20 control signals, the second - the fourth counters 21-23 and RS-flip-flop 24.

The first driver 16 of the control signals (FIG. 3) forms the first-fifth elements AND 25-29, the first to fourth RS-flip-flops 30-33, the delay element 34, the OR element 35, the first to fourth drivers 36-39 short pulses.

The second driver 19 of the control signals (Fig. 4) includes a counting trigger 40, the first-strap elements AND 41-46, the first-fourth shapers 47-50 short pulses, the first-third RS-triggers 51-53 and the element OR 54.

The third shaper 20 control signals contains (Fig. 5) RS-flip-flop 55 and the element And 56.

Unit 10 for setting phase shift parameters is made as (Fig. 6) source

57potential voltage generator

58 pulses, the generator 59 of the sinusoidal signal, the generator 60 of the noise and the switch 61.

The signal shaper with the phase shift works as follows.

A digital signal arrives at the input of the signal generator with a phase shift, in which the pulse duration in the general case varies continuously (Fig. 2a).

0

five

0

five

0

five

0

five

0

five

This signal is fed to the input of the second imaging unit 8. In it, the pulses are greatly shortened along the leading edge and acquire a constant duration (Fig. 26). These short pulses are fed to the input of the ADC 9. The control input of the ADC 9 is supplied with a signal from the unit 10 for setting the phase shift parameters. This signal can be fluctuation noise (Fig. 2c), harmonic oscillation, pulse voltage or a constant voltage of a certain magnitude.

The code combination at the output of the A / D converter 9 corresponds to the voltage value at the control input of the A / D converter 9 at the moment when a short pulse appears on its input, which is formed on the leading edge of the digital signal. Thus, with an eight-bit code (the 9th bit is a sign) with the appearance of a zero voltage at the control input of the ADC 9, the combination 100000000 is present at the output of the ADC 9. For example, the control input of the ADC 9 has a voltage of +60 mV, then at the moment of arrival of a short pulse to the first input of the ADC, the combination 100001111 appears at its output. Thus, 256 code combinations can be obtained for positive voltage values at the control input of the ADC 9 and 256 code combinations for negative voltage values every 4 mV. Each code combination at the output of the ADC 9 corresponds to a certain phase shift, which should receive a digital signal. The maximum phase shift that can be obtained is about two clock intervals in both directions. The code combinations 100000000 and 000000000, corresponding to the zero voltage at the control input of the ADC 9, form the phase delay of the digital signal by two clock intervals. The code combination 111111111 at the output of the ADC 9 generates the phase delay of the digital signal by an amount close to zero, and the code combination 011111111 generates a phase delay by an amount close to four clock intervals.

The signal from the output of the A / D converter 9 is fed to the input of the decoder 13. When the code combination arrives at the input of the decoder 13

A 100000000 or 000000000 code combination appears at the output of the decoder.

0100000001 (257), corresponding to zero phase shift during the formation of phase fluctuations or phase delay of 2 clock intervals during the formation of constant phase shifts.

When a code combination 111111111 arrives at the input of the decoder 13, the code combination appears at its output

0000000001 (1), corresponding to the maximum phase shift in the direction of advance when forming phase fluctuations. When the code combination 0111111111 arrives at the input of the decoder 13, the code combination 1000000001 (513) appears at its output, corresponding to a shift to the delay side. In the interval between the zero phase deviation and the maximum, there can be 256 values of phase shifts in the direction of advance and 256 in the direction of delay.

Code combinations from the output of the decoder 13 are applied to the input of the accumulator 14, and with the arrival of the signal from the first output of the driver 19 to the control input of the accumulator 14, these code combinations appear at its output.

The output from accumulator 14 is fed to the first input of comparator 15, the second input of which receives a signal from the output of counter 22 or 23 through switch 18. The signal input of counter 22 or 23 begins to receive a pulse (Fig. 2d) from the generator 1 of pulses through the driver 19 only from the moment of arrival at its first input of the signal from the output of the imaging unit 8 (Fig. 26). With the arrival of pulses from the pulse generator 1, for example, the counter 22, code combinations begin to appear at its output, proportional to the number of arriving pulses. These code combinations through the switch 18 are applied to the second input of the comparator unit 15, and if they coincide with the code combination, a short pulse appears at its first input (Fig. 2e). This pulse has a delay relative to the pulse at the output of the imaging unit 8 by an amount determined by the value of the voltage from the output of the unit 10, and changes with a change in this voltage.

During the formation of long pulse delays, as well as large magnitudes of phase fluctuations, a situation arises when, during the period of the formation of a phase shift of a single pulse, another pulse arrives, which must also be delayed. Such work simultaneously with two input pulses provide the drive 14, the switch 18, the driver 19 and the counters 22 and 23.

With the arrival of the second information pulse at the input of the imaging unit 8 while the phase shift of the first pulse is formed, the operation proceeds as follows. A short pulse from the output of the imaging unit 8 starts the ADC 9, which outputs at its output a code combination corresponding to the voltage of the signal at its second input at the moment of arrival of the second information pulse5

sa The code combination at the output of the A / D converter 9 after its conversion in the decoder 13 is applied to the input of accumulator 14. However, the output of accumulator 14 still contains the code combination corresponding to the first information pulse, since no signal was received at the control input of accumulator 14.

Short pulse corresponding

0, the leading edge of the second information pulse, from the output of the second driver 8 (Fig. 26), is also fed to the first input of the driver 19. Under the action of this pulse in the driver 19, a circuit is triggered through which high-frequency pulses from the generator 1 start to flow to the signal input of the counter 23. Thus, for some period of time, both counters 22 and 23 are working. Switch 18 is turned on at this time.

0 so that the output of the counter 22 is connected to the second input of the comparison unit 15. At the time of the matching of the code combinations, the first and second inputs of the 15/15 comparison appear at its output a short pulse (Fig. 2e) that is applied to the third input of the driver 19. Under the action of this pulse, the driver 19 generates control signals to reset the counter 22, connect the second input of the switch 18 to the output of the counter 23

0 and overwriting information from the input drive 14 to its output. Thus, switching occurs to the formation of the phase shift of the second information pulse, which appears at the output of the comparison unit 15 at the time of coincidence

5 code combinations from the outputs of the drive 14 and the counter 23.

The pulse from the output of the comparator unit 15 is also fed to the S input of the RS flip-flop 24. The trigger 24 is triggered and begins to form an output pulse (Fig. 2n). The decay of this information pulse, the duration of which should correspond to the input pulse, is formed as follows.

5 An information pulse (Fig. 2a) is fed to the input of the element And 7, to another input of which PS are high-frequency pulses from the generator 1 of the pulses (Fig. 2d). The number of these high-frequency IM-pulses that pass through AND 7 (Fig. 2e) to the input of counter 2 is determined by the duration of the input pulse. Under the action of these pulses, code combinations, proportional to the number of 5 pulses received, appear at the output of counter 2. Code combinations are applied to the code inputs of the accumulators 11 and 12. Under the action of the control signal supplied to the accumulator 1 1 or 12, the code combination appears on the first

The BOM or the second input of the switch 3 and then from its output is applied to the second input of the comparison unit 5. At the first input of the comparison unit 5, code combinations from counter 21 through the open key 17 arrive. High-frequency pulses from the pulse generator 1 start to arrive at the signal input of the counter 21 only from the moment of arrival of the short pulse (Fig. 2d) from the output of block 15 comparison to the third input of the former 20.

After a time interval equal to the duration of the input information pulse, the code combinations on the first and second inputs of the comparison unit 5 coincide and a short pulse appears at its output (Fig. 2g). This pulse is applied to the first inputs of the drivers 16 and 20; under its action, the counter 21 is reset and triggers the RS flip-flop 24, forming at its output a phase-shifted information pulse (Fig. 2n).

At large values of phase shifts during the period of formation of the decay of the first input pulse, a second pulse can arrive, the duration of which must also be remembered and restored. Simultaneous operation with two input pulses is provided by the driver 6, the counting trigger 4, the drive 11 and 12, the switch 3, the driver 16, and the key 17.

Information pulses from the input (Fig. 2a) are received, in addition to the second input of the element 7, also to the input of the imager 6, which shortens these pulses in a decay (Fig. 2h). These shortened pulses are then fed to the input of the counting trigger 4 and to the second input of the imaging device 16. The leading edge of these information pulses resets the counter 2 to the zero state (Fig. 26).

With the arrival of the first information pulse, code combinations appear at the inputs of the first 11 and second 12 drives. Under the action of a short pulse from the output of the former 6, the counting trigger 4 overturns and on its one output appears the signal "O, and on the second - the signal" 1 (Fig. 2i, k), which together with the signal at the input of the trigger -4 (Fig 2h) are applied to the second, third and fourth inputs of the driver 16. These signals form control pulses in it, which are fed to the control inputs of the accumulator 11, switch 3 and key 17. Under the action of the control pulse, the code combination at the input of the accumulator 11 is written in him and turns on his way out one women. Govern

five "

5 Q

5 5

0

A NOW impulse arriving at switch 3 causes it to trip and connect the output to the first signal input. Under the action of a control pulse, applied to the key 17, its input and output are connected.

As a result of all these operations, the code combination corresponding to the duration of the first information pulse is applied to the second input of the comparison unit 5. The duration of the input pulse begins with the arrival of a short pulse (Fig. 2e) from the output of the comparator unit 15 to the third input of the imaging unit 20. At the moment the code combinations match, the first and second inputs of the comparator unit 5 appear at its output a short pulse (Fig. 2g), which, being applied to the R-input of the RS-flip-flop 24, forms the drop of the output pulse (Fig. 2n).

If at the moment of forming the first shifted information pulse, the second information pulse arrives, then with its leading edge (Fig. 26), through the imaging unit 8, the counter 2 is reset to the zero state, and applied to the second input of the And 7 element, causes it to trigger and skip the input of the counter 2 (Fig. 2E) high-frequency pulses from the generator 1 pulses. At the output of counter 2, as well as at the inputs of accumulators 11 and 12, a code combination appears, which is proportional to the duration of the second information pulse. With the end of this second information pulse at the output of the imaging unit 6, a short pulse g appears. 2h), arriving at the input of the counting trigger 4 and the second input of the imaging device 16. At its second output, a pulse appears, which enters the control input of the accumulator 12. Under the action of this impulse, the accumulator 12 is activated and, at its output, a code combination, corresponding to the duration of the second information pulse. However, the output of the switch 3 is still connected to the output of the drive 11 through its first input.

At the moment of the end of the formation of the decline of the first shifted information pulse, a short pulse appears at the output of the comparison unit 5 (Fig. 2g) arriving at the first input of the shaper 16. Under the pressure of this pulse, the shaper 16 outputs a signal to the control input of the switch 13, which connects its exit to your first entrance. Thus, the code combination corresponding to the duration of the second information pulse appears at the second input of the comparison unit 5. With the arrival of a short pulse corresponding to the leading edge of the shifted information pulse (Fig. 2d), high-frequency pulses from the pulse generator 1 begin to flow to the third input of the imaging unit 20 from its output to the signal input of the counter 21. The formation of the decay of the second information pulse begins. In this case, the case is considered when the delay time of an information pulse is longer than its duration, i.e. the signal at the third input of the imaging unit 20 appears later than the signals at the second, third and fourth inputs of the imaging device 16. Then the code combinations from the output of the counter 21 go through the key 17 to the input of the comparison unit 5, while at the first input of the imaging equipment 16 already has a code pattern corresponding to the duration of the input information pulse.

It is possible that the delay time of an information pulse is shorter than its duration, i.e. the signal at the third input of the imaging unit 20 appears earlier than the signals at the second, third and fourth inputs of the imaging device 16. In this case, the key 17 is closed and the code combinations from the counter 21, which began to count pulses from the pulse generator 1, do not fall into the first input block 5 comparison. This is necessary so that the code combination at the second input of the comparison unit 5, remaining from the previous information pulse, does not coincide with the code combination generated in the counter 21.

At the end of the input information pulse (Fig. 2a), a short pulse appears at the output of shaper 6 (Fig. 2h), which, applied to the input of the counting trigger 4 and shaper 16, creates control signals for accumulator 11, switch 3 and key 17. Thus, the code combination corresponding to the duration of the input information pulse appears on the second code input of the comparison unit 5, and the code combinations from the counter 21 begin to be supplied to the first input, since the key 17 is now open.

Consequently, the duration of the phase-shifted information pulse in the RS flip-flop 24 is restored for cases when the delay time is greater or less than the pulse duration, as well as for the arrival of the second information pulse during the formation of the first shifted pulse.

The shaper 16 operates as follows (Fig. 3). The appearance at the output of the former 6 (Fig. 1) of a short pulse (decay of the input information pulse) to the second, third, and fourth inputs

- five

five

5 5

0

0

0

Ladies 1-6 apply signals: at the second input - a short unit impulse, at the third - zero, at the fourth - unit.

The short pulse that occurred at the second input of the former 16 passes through the OR element 35 and overturns the RS flip-flop 33. At its output, the signal "1" is applied, which is applied to the fourth output of the former 16 and then to the control input of the key 17 (Fig 1), opening it. The pulse at the fourth input of the imaging unit 16 passes through the imaging unit 37, where it is shortened along the leading edge, and, falling on the S input of the RS flip-flop 30, overturns it (Fig. 3). The same impulse from the output of the imaging unit 37 goes to the first output of the imaging device 16 and then to the control input of the accumulator 11 (Fig. 1), causing it to operate.

At the direct output of the RS flip-flop 30 appears "1, which is applied to the first inputs of the elements AND 27 and 29, and at the inverse output -" O, which is applied to the second input of the element AND 4. At the second input of the element 27, "1 from the inverse output of the RS flip-flop 32. Thus, at the output of the element And 27 also appears a single pulse, which passes through the shaper 36, shortening on the leading edge, and is applied to the S-input of the RS flip-flop 31. It overturns, and at its direct output a single impulse appears, arriving at the first input element and AND 25, as well as to the third output of the imager 16 and further to the control input of the switch 3 (Fig. 1).

At the end of the formation of the decay of the phase-shifted information pulse, a short pulse appears at the output of the comparison unit 5 (Fig. 1), which is fed to the first input of the shaper 16. This pulse in the shaper 16 (Fig. 3) is fed to the R input RS -trigger 23 and overturns him. At the fourth output of the former 16, the "O" key with which the key 17 is closed appears (Fig. 1). The same pulse from the first input of the imaging device 16 is fed to the second input of the element I (FIG. 3) passes through it and is applied to the R input of the RS flip-flop 30, resetting it to its original position.

With the arrival of the next informational pulse, the shaper 30, the third RS-flip-flop 32, the AND 28 element, the shaper 38, the AND 26 element, as well as the RS-flip-flop 31, the OR 35 element and the RS-flip-flop 33 are put into operation.

It is possible that during the formation of the decline of the first information pulse, a second information pulse comes. Suppose under the action

The signal from the fourth input of the driver 16 (from the first pulse) triggered RS-trigger 30 (Fig. 3), as well as the RS flip-flop 31, 4 under the action of a pulse at the second input of the driver 16, the RS-trigger 33 worked. to the second input of the imaging unit 16 comes the signal. (second | th pulse). This signal overturns the RS flip-flop 32. In addition, this signal (1 output of the formator 39 is fed to the second input of the imaging device 16 and then to the control input of the storage device 12 (Fig. 1).

After triggering the RS flip-flop 32, a single pulse from its direct output is applied to the first input of the AND 28 element (Fig. 3). However, this img hive does not pass through it, since at its second inlet /, e at this time there is a zero potential from the inverse output of RS flip-flop 30. In addition, a single pulse from direct output RS -trigger 32 enters the second E of element I 29 and passes through it and the input of delay element 34, since at the first input of element I 29 there was also “1 from the direct output of RS flip-flop 30. Uniform t | H4Hb potential from input the Delay element 34 passes through it and the OR element 35 and is applied to the S-input of the RS-1 rigger 33, which was tilted earlier by a signal from the first Wow Informational Impulse.

; with the end of the formation of the decay of the first information pulse on the first c), the signal that passes through the AND 25 element appears on the first c), and goes to the R input of the RS flip-flop 30, returns to its initial position. A single impulse arises in the reverse output, which, applied to the second E | PROCESS of the E28 element, opens it, passes through the imaging unit 38, shortening the rjo to the leading edge, and hits the R input of the lkS trigger 31. It is triggered , and at its direct output, there appears a zero potential, which is supplied to thirds Output shaper 16 and then to the control input of the switch 3 (Fig. 1).

In addition, the pulse from the first input of the driver 16 (Fig. 3) falls on the R input of the RS flip-flop 33, but does not overturn it, because at this time there is a unit potential at its S input that the element 34 continues to hold for a short time delays.

At the end of the decay formation of the second information pulse, a single signal appears at the first input of the imaging unit 16, which passes through; The AND 26 and, applied to the R input of the RS flip-flop 32, returns it to its original state. The same signal resets the RS-flip-flop 33 as well.

Shaper 19 control signals works as follows (Fig. 4).

ten

The input of the counting trigger 40 (the first input of the former 19) comes a short pulse corresponding to the leading edge of the input information pulse. Trigger 40 is triggered, and at its direct output a single impulse appears, which passes through shaper 48, shortening along the leading edge. This pulse is applied to the S input of the RS flip-flop 51 and causes it to trip. The unit potential from the direct output of the trigger 51 is fed to the first input of the element E 43 and passes through it, since its second v. Code is in this reg. there is a single potential from the inverse output of the RS flip-flop 53. I. pulse, appearing at the output of the element And 43, goes through the driver 47, shortening along the leading edge, and goes to the first element OR 54. Passing through it, it turns out on the first the former 19 and then is fed to the control input of the accumulator 14, causing it to trip (Fig. 1). In addition, the impulse from the output of the formaker 47 enters the S-in. And the RS-flip-flop 52, knocking it over. At its direct output, a single potential appears at the second output of the former 19.

A single from the direct output of the RS flip-flop 51 is also applied to the first input of the element I 4, to the second input of which from the second output of the former 19 enters high-frequency and pulses. These pulses pass through the element AND 41 and arrive at the fifth output of the former 19.

At the end of the formation of the phase-shifted front edge of the information pulse, a short pulse appears at the third input of the former 19. This pulse is applied to the first input of the element 42 and passes to its output, since at its second input at this time there is a single potential from the direct output of the RS flip-flop 52 (Fig. 4). The pulse from the output of the element 42 is fed to the R input of the RS flip-flop 51, resetting it to its original position, and, in addition, this pulse goes to the third output of the driver 19.

When the next information pulse arrives at the first input of the imaging device 19, it works in the same way as it does when the first impulse arrives; the trigger 53, the element And 44, the driver 49, the element And 45 and 46, as well as the counting trigger 40, the element OR 54 and the RS-trigger 52.

In the case when the second information pulse arrives at the first input of the imaging unit 19 while the formation of the phase shift of the first informational pulse continues, the imaging unit 19 operates as follows.

By the time the second pulse arrives at the first input of the imager 19, there is a zero potential at the inverse output of the RS flip-flop 51, and a single potential at the direct output of the RS flip-flop 52. The leading edge of the second information pulse from the first input of the former 19, the counting trigger 40, is transferred to a state in which a unit potential appears at its inverse output. This signal passes through the driver 50, is shortened and is applied to the S input of the RS flip-flop 53. It triggers, and at its direct output appears the signal "1, which arrives at the first

shaper 20) high frequency pulses are supplied from pulse generator 1. These pulses pass through the element AND 56 and arrive at the output of the imaging unit 20 and further to the signal input of the counter 21 (Fig. 1).

At the completion of the formation of the decay of the shifted information pulse, a short pulse from the output of the comparison unit 5 (Fig. 1) comes to the first input of the imaging unit 20. By this impulse, the RS-flip-flop 55 is reset to the initial state, and the AND element 56 stops the passage of the high-frequency pulses.

Block 10 of setting phase parameters

the input element And 44, but does not pass 15 shift can be performed according to the scheme

20

25

through it, since zero potential is applied to its second input at the inverse output of RS flip-flop 51. The unit potential from the direct output of RS flip-flop 51 also goes to the first input of the element 46, to the second input of which high-frequency pulses are fed from the second input of the former 19. These pulses pass through the element E 46 and are fed to the sixth output of the former 19.

With the end of the formation of the leading edge of the first shifted pulse, a short pulse appears at the third input of the former 19, which passes through the element 42 and, falling on the R input of the RS flip-flop 51, moves it to its original, g position. In this case, at its inverse output, a single potential appears, which arrives at the second input of the AND 44 element and opens it. The signal from the output element And 44 passes through the imaging unit 49 and enters the second input of the element OR 54. Next, this signal passes to the first output of the imaging device 19. In addition, the signal from the output of the imaging device 42 acts on the R-input of the RS flip-flop 52, tilting it. At its direct output, a zero potential arises, which is fed to the second output of the driver 19.

Upon completion of the formation of the front of the second shifted information image

40

in FIG. 6

For the implementation of constant phase shifts of different magnitudes, there is a source of 57 constant voltages. A certain value of the DC voltage from its output corresponds to a certain phase shift of the signal at the output of the proposed signal conditioner with a phase shift.

The pulse generator 58 is designed to effect the phase jumps of the digital signal.

The generator 59 of the sinusoidal signal realizes the phase fluctuations of the digital signal according to the harmonic law with different frequencies.

The noise generator 60 realizes the implementation of the phase f.ctuations of a digital signal according to a random law with different values of the width of the energy spectrum.

Claims (1)

Invention Formula A phase shifting signal generator comprising a pulse generator, a first counter, a first switch, a first comparison block, a counting trigger, a phase shift parameter setting block, and a first packer, characterized in that, in order to increase the range of phase shifts, the first copulifier is inserted into it at the third inlet of the former 19 45 blunt pulses, the output of which is connected a short pulse appears, which passes through the element 45 and resets the RS flip-flop 53 to the initial state. In addition, he gets on the fourth driver 19. Shaper 20 control signals works as follows (Fig. 5). When a short pulse arrives at the third input of the shaper 20 corresponding to the leading edge of the shifted information pulse that is generated, an RS flip-flop 55 is triggered. entrance 0 shaper 20) high frequency pulses are supplied from pulse generator 1. These pulses pass through the element AND 56 and arrive at the output of the imaging unit 20 and further to the signal input of the counter 21 (Fig. 1). At the completion of the formation of the decay of the shifted information pulse, a short pulse from the output of the comparison unit 5 (Fig. 1) comes to the first input of the imaging unit 20. By this impulse, the RS-flip-flop 55 is reset to the initial state, and the AND element 56 stops the passage of the high-frequency pulses. Block 10 of setting phase parameters 5 shift can be performed according to the scheme five g five 0 in FIG. 6 For the implementation of constant phase shifts of different magnitudes, there is a source of 57 constant voltages. A certain value of the DC voltage from its output corresponds to a certain phase shift of the signal at the output of the proposed signal conditioner with a phase shift. The pulse generator 58 is designed to effect the phase jumps of the digital signal. The generator 59 of the sinusoidal signal realizes the phase fluctuations of the digital signal according to the harmonic law with different frequencies. The noise generator 60 realizes the implementation of the phase f.ctuations of a digital signal according to a random law with different values of the width of the energy spectrum. Invention Formula A phase shifting signal generator comprising a pulse generator, a first counter, a first switch, a first comparison unit, a counting trigger, a phase shift parameter setting unit, and a first drive driver, characterized in that, in order to increase the range of phase shifts, the first koh generator is introduced into it five the input of the counting trigger, the element And, the output of which is connected to the input of the first counter, the second drive, the input of which is connected to the output of the first counter and the input of the first accumulator, and the output to the first signal input of the first commutator, are in series connected pulses, analog-to-digital converter, the control input of which is connected to the output of the phase shift parameter setting block, the decoder, the third drive and the second comparison block, the second switch, the output of which is connected to orym input of the second comparator unit, the third counter, the output which is connected to the first signal input of the second switch, a fourth counter, the output of which is connected to the second signal input of the second switch, an RS flip-flop, the S input of which is connected to the output of the second comparator unit, serially connected to the second counter and a key whose output is connected to the first input of the first comparison unit, the first driver of the control signals, the first, second, third and fourth inputs of which are connected respectively with the output of the first comparison unit, with the output of the first driver short pulses, with the inverse output of the counting trigger and with the forward output of the counting trigger, and the first, second, third and fourth outputs, respectively, with the control input of the first accumulator, with the control input of the second accumulator, with the control input the key input, the second driver of the control signals, the first, second and third inputs of which are connected respectively to the output of the second driver of short pulses, to the output of the pulse generator and to the output of the second comparator, and the first , Second, third, fourth, fifth and outputs schestoy - sootvet1 I1 F L pp g Thebes. 2 with the control input of the third accumulator, with the control input of the second switch, with the control input of the third counter, with the control input of the fourth counter, with the signal input of the third counter and with the signal input of the fourth counter, the third driver of the control signals, first, second and the third inputs of which are connected respectively to the output of the first comparison unit, to the output of the pulse generator and to the output of the second comparison unit, and the output is connected to the signal input of the second counter, while the second the input and output of the first switch are connected respectively to the output of the first accumulator and to the second input of the first comparison unit, the output of the second short pulse driver is connected to the control input of the first counter, the R input of the RS flip-flop is connected to the output of the second counter , the first input of the element And is connected to the output of the pulse generator, the inputs of the first and second shapers of short pulses and the second input of the element And are interconnected and their connection point is the input form signal turner with phase shift, and the output of the RS flip-flop - its output. P t 1234 Fig.Z 3456 i 2 3 FIG. four / cvemtjuHy 2f I 55 / S 2b FIG. five t 57 Compiled by G. Zakharchenko Editor A. OgarTehred I. VeresKorrektor I. Muska Order 1978/55 Circulation 928 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and ioligraphic enterprise, Uzhgorod, ul. Project, 4 12 60 fie.b