SU1190354A1 - Multistop time interval-to-digital converter - Google Patents

Abstract

MULTI-STOP TRANSFORMER OF TIME INTERVALS IN THE DIGITAL CODE, containing a clock pulse generator, the output of which is connected to the first inputs of the timer and the rewriter, the second inputs of which are connected to the start and stop time dials, and the hys- tem reformer, a part of the sharer, a part of a time frame, and a freeware quotation unit, which is connected to the start time and stop time dials, and the timeframe part of the timeframe shunt unit, the timeframe shunt unit, the timeframe part of the timeframe, and the timeframe part of the timeframe, the part of the timeframe part of the timeframe, and the timeframe part of the timeframe, and the timeframe part of the timeframe, and the timeframe part of the timeframe, and the timeframe part of the timeframe part of the timeframe. the input of the binary counter, the outputs of the bits of which are connected to the corresponding D-inputs of the buffer register, the output of the signal conditioner, the rewriter is connected to the input of the timer , in order to improve the measurement accuracy by reducing its dependence on the number of bits of the binary counter, t-1 rewriting blocks are entered into it, and the C-inputs of the buffer register are combined into m groups, the output of the first bit of the binary counter is connected with the first input of the first rewriting unit, the output of the overwriting signal generator is connected to the C-inputs of the first group of triggers, the buffer register and the second input of the first rewriting unit. The C inputs of the i-th buffer register trigger group are connected to the output of the i-ro rewrite unit and the first input (i + l) -ro of the rewrite unit, the second input of the i-ro rewrite unit is connected to the i-ro output of the binary counter The R inputs of which are connected to the measurement end bus and the third input of the timer series generator, the R inputs of all rewriting blocks are combined and connected to the timer output. 2. The converter according to claim 1, which is different from the fact that the rewriting block contains an I and I and RSo trigger, the output of which is you: o: l block travel, R input - R input of the block, and S input is connected to the output of the elec tant element, the first and second inputs of which are respectively the first and second inputs of the unit.

Description

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The invention relates to measurement technology and can be used as equipment for automating scientific research in the field of nuclear physics, in particular, in a number of physical experiments using time-of-flight measurement techniques.

The aim of the invention is to improve the accuracy of measuring the multi-time digital-to-digital time converter, one TiyTeM reducing its dependence on the number of bits of the binary counter.

FIG. Figure 1 shows a multi-step time-to-digital converter; in fig. 2 - time diagram of his work.

The converter contains 1 clock pulse generator, timer series generator 2, binary counter 3, buffer register 4 with C inputs combined into m, rewriting signal generator 5, timer 6 and (ha 1) serially connected blocks 7.1–7. ( t-1) rewriting, each of which includes an element 8I and RS-flip-flop 9, and the output of the generator 1 clock pulses is connected to the first inputs of the generator 2 of the timer series and the formatter 5 of the rewriting signal, the second inputs of which are connected respectively to the Start buses - and Stop, the output of the generator 2 of the timer series is connected to the counting input of the binary counter 3, the outputs of the bits of which are connected to the corresponding D-inputs of the buffer register 4, the output of the generator 5 of the rewrite loop is connected to the input of the timer 6, with the C-inputs of the first group triggers of buffer register 4 and one of the inputs of rewriting block 7.1, the second inputs of each rewriting block 7 are connected to the D inputs of the last triggers of the corresponding selected trigger groups of buffer register 4, the output of timer 6 is connected to the K input of all blocks 7 restarts ICI. The i-ro RS-flip-flop S-input 9 of rewriting block 7 i is connected to the code of the i-ro element 8I, whose two inputs and the R-input of RS flip-flop 9 are inputs of rewriting blocks 7, the RS Trigger 9 output is output of blocks 7 rewrite.

54 2

The principle of operation of the multi-stop time interval to digital converter is as follows.

In the initial state, the triggers of the binary counter 3 and the RS-triggers 9 of the rewriting blocks 7 are in the state O. The triggers of the buffer register can be in an arbitrary state.

According to the impulse arriving at the Start converter input, the shaper 2 starts producing impulse-7 s, phased at the clock frequency of the generator 1 (Fig. 2a) and arriving at the input of the binary counter 3. Pulses produced at the outputs of the first and K-th bits shown in FIG. 2 b, c, at the outputs of the remaining bits — in FIG. 2g.

Installation in O or 1 of these or other bits of the counter occurs with a delay determined by the frequency properties of the element base of the counter (Fig. 2).

When a pulse arrives at the Stop input using the shaper 5 of the i-ro of the rewrite unit 7, the code from binary counter 3 is overwritten into the buffer register 4. Overwriting is performed taking into account the delay in setting the bits in the binary counter 3.

To do this, at the output of the imaging unit 5 (Fig. 2 e), the impulse Stop produces a signal in the form of level 1, the leading edge of which is phased with the clock frequency of the generator 1.

Moreover, if the triggers of binary counter 3 operate on the falling edge of clock pulses, then the signal should correspond to the leading edge of clock pulses, i.e. have a half frequency generator 1 delay.

On the leading edge of the signal from the imaging unit 5, the first bits of the binary counter 3 are overwritten into the corresponding triggers of the first group of the buffer register 4. It is obvious that the transfer time 1 in the rewritable bits must not exceed a half-period of the clock frequency.

Overwriting the remaining bits of the counter 3 into the corresponding groups of the buffer D triggers) -and (the third hour is sequentially using blocks 7 as the RS-flip-flop 9 is set to state 1 in each of them (Fig. 2t). Installation in the state I of the RS flip-flop 9 occurs at the moment of no transfer 1 in the bits it overwrites. This moment is determined on the element 8 according to the state of the K-th bit of the binary counter 3 preceding the discharge. transition to state 1 Who is counter 3 (like any) does not drive t to transfer 1 in subsequent bits, while its transition to O can lead to transfer 1. Therefore, element 8 sets to 1 RS-trigger 9 or at the moment when the rewrite sequence occurs from the previous block 7, if K th bit is in | or by the transition of the K-th bit to I. Both in the other case, the transfer 1 in the subsequent K-th bit of the rewritable bits of counter 3 ends if the selected number of triggers in any considered group satisfies the condition: tn. T.2, (1) where tj, - transfer time - delay created on one trigger of counter 3; E is the number of triggers in the group; T is the period of the clock frequency; K - preceding rewritable bit. As can be seen from the above expression in the proposed converter, the requirement for the value of the allowable delay created on the meter triggers in each next group is reduced. Consequently, the number of triggers in each subsequent group may increase. For this reason, in this converter, the number of rewriting blocks, which corresponds to the number of groups with a large number of bits of counter 3, is substantially less than in the known. It also follows from the discharge I that the limitation on the measurement accuracy T can be removed by reducing the number of bits f in the group. To do this, for a given number of bits n of counter 3, the number of groups m should be slightly increased. Thus, in the proposed converter, the limitation on the measurement accuracy imposed by the digit capacity of counter 3 can be practically cleared by circuit design and with a smaller number of elements rewrite chain. At the same time, the achieved accuracy is practically determined by the speed of the element base. When expanding the measurement range for a given accuracy, the exact BW delay filling is difficult. In the proposed converter, the oncoming delay in a binary counter can be easily eliminated by selecting the required number of groups with a corresponding introduction by the rewriting unit.

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Claims (2)

MULTI-STAGE TRANSFORMER OF TIME INTERVALS TO DIGITAL CODE, containing a clock pulse generator, the output of which is connected to the first inputs of the timer series shaper and the overwrite signal generator, the second inputs of which are connected respectively to the start- and stop-pulse buses, the output of the timer series counter is connected binary counter, the outputs of the discharges of which are connected to the corresponding D-inputs of the buffer register, the output of the signal shaper. rewriting is connected to the timer input, characterized in that, in order to increase the measurement accuracy by reducing its dependence on the number of bits of the binary counter, t-1 rewriting blocks are introduced into it, and C-inputs of the buffer register are combined into m groups, and the output of the first digit the binary counter is connected to the first input of the first overwrite unit, the output of the overwrite driver is connected to the C-inputs of the first group of triggers, the buffer register and the second input of the first overwrite unit, C are the inputs of the i-th group of trigger flip-flops of the ith register are connected to the output of the i-th rewrite unit and the first input of the (i + 1) -th rewrite unit, the second input of the i-th rewrite unit is connected to the output of the ί-Γο bit of the binary counter ^ R — the inputs of which are connected to the end measurement bus and the third input of the timer series shaper, R — the inputs of all overwrite blocks are combined and connected to the timer output. 2. The converter according to π. 1, characterized in that the rewriting unit contains an AND element and an RS trigger, the output of which is the output of the unit, R — input is the R-input of the unit, and the S-input is connected to the output of the And element, the first and second inputs of which are the first and second, respectively block inputs. 1 1190354 2