SU1522375A2 - Digital multiplier of recurrent pulse repetition rate - Google Patents

Abstract

The invention relates to a pulse technique and can be used in frequency converters. The purpose of the invention — improving noise immunity — is achieved by temporally selecting an input signal. The multiplier contains 1 clock pulse generator, shaper 2 reset pulses, shapers 3 and 12 control pulses, AND 4, 15 elements, dividers 5, 9 and 10 frequencies, counters 6 and 13 pulses, memory register 7, divider 8 with variable division factor , delay element 11, trigger 14, input 16 and output 17 bus. 1 il.

Description

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The invention relates to a pulse technique, can be used in measuring frequency converters and is complementary to the author. St. No. I164858.

The purpose of the invention is to improve the noise immunity due to the time of the input signal.

The drawing shows an electrical JQ block diagram of the device.

The digital pulse frequency monitor of the periodic pulses contains a generator of I clock pulses, shaper 2 reset pulses, J5 first shaper 3 control 1 megapulses, first element "4", first frequency divider 5, first counter 6 of dates, memory register 7, divider 8 with variable factor J (by dividing element 20, second and third dividers 9 and 10 frequencies, delay element 11, second control pulse generator 12, second pulse counter 13, trigger 14, second element 15 25 and input and output buses 16 and 17 . Bus 16 bus connection with the first input of the second element 15, with the input of the second generator 12 control pulses and through the 1 1 JQ delay element with the reset input of the trigger 14, the first start input of which is connected to the transfer output of the second counter 13 pulses, the second start input -, s output of the second form-ipater 2 control pulses, output- with the second input of the second element I 15, the output of which is connected to the input of the first form-3 control pulses, through a driver of 2 reset pulses with setting inputs ne: 5 of the first frequency dividerin; mountain counters 6 and 13 pulses and directly to the recording input of the storage register 7, informational, the inputs of which are connected to the outputs of the first counter 6 pulses, the counting input of which is connected to the output of the first frequency divider 5, the clock input of which is connected to the first input of the first element And 4 and with the output of the second frequency divider 9, the clock input of which is connected to the output of the clock generator 1 and through the third frequency divider 10 to the counting input of the second counter, 13 pulses, the corresponding information The e inputs of which are connected with a shift and one bit in the direction of the low bits with the corresponding outputs of the storage register 7, which are bitwise connected to the information inputs of the divider 8 with a variable division factor, the output of which is connected to the output bus 17, the clock input with the output the first element And 4, the second input of which is connected to the output of the first driver 3 control pulses.

The digital multiplier of the frequency of the periodic pulses operates as follows.

In the initial state, the output of the former 3 is low and the element 4 is closed at the nepBoi fj input. The pulses of the generator 1 to the input of the divider 8 is not received. Bus 16 receives a periodic pulse train with a frequency FU. On the falling edge of the pulse at the output of the imager 2, a signal is produced, which zeroed divider 5 and counter 6, which is filled with pulses arriving at its counting input from the output of divider 5.

The shaper 3 is designed in such a way that with the arrival of the second and subsequent input pulses a high potential appears at its output, as a result of which element 4 opens at the first input and through its second input the generator 1 pulses into the input of the divider 8. By the arrival of the next input pulse on the bus 16 in the counter 6, the number N is written, which is equal to the ratio of the periods of the input and filling counter of 6

1Lm ..

1 / Fr /

K, - ;.

where F is the frequency at the output of the divider 9; n is the division factor of divider 5.

On the leading edge of the input pulse, the number N is rewritten from counter 6 to register 7. In this case, divider 8 divides the frequency F.J. on the number entered into it by the end of each period from register 7. The cycle is repeated and a pulse train is formed on bus 17 at a frequency of

 ± i x

IT

P

FT

Fr / f

VC

P

 F

in

P

; t. e, the follow frequency of the input pulses Fe (increases by n times.

The time selection of the input signal is carried out as follows.

At the moment of switching on the power from the output of the imaging unit 12, the impulse of not less than 3 Tbh, where the maximum value of the period of the input pulses arrives at the input of the installation of the trigger 14 (start input). This impulse translates trigger 14 into a single state. As a result, the element 15 is open dp passing at least the first three pulses.

On the leading edge of (for example, the fourth) input pulse, the counter 13 is set to the zero state. After the time interval L, the trigger 14 is set to the zero state, the input signal is fed through the element 11 to the reset input of the I 4 C trigger (a parameter characterizing this delay element).

On the trailing edge of the pulse from the output of the generator 2, the number N, accumulated in counter 6 for the time interval T and recorded in register 7, is shifted by one (or more bits to the information inputs of counter 13, with the operation of dividing the binary code by L, where L 2, 4, 8 ... (code division is performed by shifting the code

N, and L bits), which is achieved by a corresponding connection of the outputs of the bits of the register 7 and the information inputs of the counter 13. On the leading edge of the signal from the output of the former 2, the pre-recording into the counter 13 of the code

numbers N, / l. On the counting input (countdown) of the counter 13 through the divisor

10 pulses are received with frequency Sx X, where K is the division factor of the divider 10. At the moment when the number of pulses received at the counting input of counter 13 exceeds the number N, / L, the signal that sets the trigger is generated at the output of the transfer (borrowing) of counter 13 14 in one unit. A gate pulse from the output of trigger 14 is fed to the second input of element 15, opening it to pass the input signal. The next input pulse passes through evil 15 and after a time interval sets. Trigger 14 to zero

condition. In other time intervals, the element 15 is closed at the second input, so the interference signal does not arrive at the information input of the entire device.

The duration of the strobe pulse is determined by the frequency S F of the generator B, the ratio S of the division of the divider 9, the coefficient L, the coefficient K of the divider 10, i.e. a strobe pulse is generated at the time when

N L

P-N

one

de

NA LLls- N L

N UTV)

the number of pulses recorded in the counter 13 on the information input;

FT

- is the number of pulses per time interval T between the opening of element 15 and the appearance of a pulse on bus 16.

Then the ratio between the period of the input signal (provided

T "at T) and the time interval & T is equal to

DT t

6X

S. L

0

five

0

five

The relative duration of the strobe pulse is set by selecting certain values of the integers K and S, L (for example, if K 3, 2, then the duration of the strobe pulse is equal to 1/4 of the period T of the input signal).

Claims (1)

The invention of the digital frequency multiplier following periodic pulses auth. St. t A64858, characterized in that, in order to improve noise immunity, the second and third frequency dividers, the second pulse counter, the second driver of control pulses, the trigger, the delay element and the second element AND, which is connected between the input bus and the input the form of the reset pulses, the output of which is connected to the installation input of the second pulse counter, corresponding to , 715223758 information inputs of which are connected to the trigger reset input, are not shifted by one bit, the output of which is connected to the second lower-order input with the corresponding second element I, while the output outputs of the memory register of the pulse clock generator The transfer output is connected to the second, a second frequency divider is connected to the trigger start input, the second clock input to the first divider whose start input is connected through frequencies and to the first input of the first control driver and mi And and through the third clock divider with the input bus and with the input, f.that is with the counting input of the second counting element of the delay element, whose output is the pulse.