SU1107293A1 - Composite function former - Google Patents

Abstract

FORMER OF COMPLEX FUNCTION, containing a delay element, element I, clock generator, random access memory, main counter, additional counter, trigger, digital-analog converter, the output of the delay element connected to the first input of the element And, the output of the digital-analog converter is connected to the output of the former, about characterized by the fact that, in order to expand its functionality by providing a delay control mode, the analog-to-digital input control trigger, digital comparison element, first, second and third additional elements AND, information multiplexer, control multiplexer, register, address multiplexer, the first inputs of the information and control multiplexers are connected to the first and second shaper inputs, respectively, the first output the analog-digital converter is connected to the first input of the random access memory, the output of which is connected to the second input of the information multiplexer, and the output the information multiplexer is connected to the first register input, the output of which is connected to the input of a digital-to-analog converter, the first input of the analog-digital converter is connected to the third input of the driver, the output of the main counter is connected to the first inputs of the address multiplexer and digital comparison element, the output of the additional counter is connected to the second input address multiplexer, the output of which is connected to the second input of the random access memory, the second output of the analog-digital pre the generator is connected to the input of the delay element, with the second input of the element I, the first inputs of the main counter, the first and second additional elements And the third input of the address multiplexer, the output of the clock generator is connected to the second input of the analog-digital converter and , the output of which is connected to the second input of the control multiplexer, and its input is connected to the second input of the register, the second input of the digital comparison element is connected to the fourth swing device, and an output - to a second input of the first additional element and,

Description

the output of which is connected to the first trigger input, the output of the second additional element I is connected to the first input of the additional counter, the control trigger code is connected to the third inputs of the information and control multiplexers, the second inputs of the main counter, the additional counter, the trigger and the clock pulse generator input, the first and the second inputs of the control trigger are connected to the fifth and sixth inputs of the driver, respectively, the output of the element I is connected to the third input of the operational memory. his device, a trigger output connected to second inputs of the second and third of elements and additional

The invention relates to analog-digital computing and can be used in analog-digital computing complexes and automation devices.

A constant delay device is known, comprising two inverters, two integrators, an adder, made on certain amplifiers Cl 1.

The disadvantage of this device is the limited lag time (not more than 25 s) and the difficulty of setting the lag time due to the difficulty of installing the scale factors of the integrators.

The closest to the proposed is a complex function shaper that contains a delay element, an And element, a clock pulse generator (GTI), a random access memory, a main counter, an additional counter, a trigger, a digital-analog converter (D / A converter), an address generation unit, a control unit, a block the formation of information, the unit for setting the starting address, the discriminator, the first and second blocks of the AND elements, the block of the OR elements, the OR element, the NAND element, the output of the delay element being connected to the first input of the elec In the input And, the output of the DAC is connected to the output of the device, the output of the main counter is connected to the first output of the random access memory, the output of which is connected to the input of the DAC, the second and third inputs of the random access memory are connected to the first input of the control unit and the output of the information generating unit, respectively the trigger output is connected to the first input of the element I and the second input of the first block of elements And, the output 5 of the element I is connected to the first input of the main counter, the output of the clock pulse generator в is connected to the first input of the additional counter, the second output of the trigger is connected to the second input of the additional counter, the output of which through the discriminator is connected to the first inputs of the additional first block of the OR elements and the OR element, the second output of the block

5 control is connected to the second input of the OR element, the output of which is connected to the second input of the main counter, the third input of the first block of elements AND the connection to the first input of the device,

0 and the output is with the first input of the block of the OR element, the first output of the W & I block of the AND elements is connected to the second output of the trigger, the second input of the second block of the AND elements is connected to

the output of the address generation unit, and the output with the second input of the OR element block, the second input of the device is connected to the first trigger input and the first input of the NAND element whose output is connected to the second trigger input, the second input of the NAND element is connected to the clock generator output pulses, the third inputs of the additional counter and the main counter are connected respectively to the outputs of the block for setting the starting address and the output of the block for the ILIS2 elements.

A disadvantage of the known device is the inability to implement

controllable delay mode.

The aim of the invention is to enhance the functionality of the device by providing a controlled delay mode.

The goal is achieved by the fact that a complex function driver that contains a delay element, an And element, a clock generator, random access memory, a main counter, an additional counter, a trigger, a D / A converter, and the output of the delay element is connected to the first input of the And element, the digital-analog output the converter is connected to the output of the imager; an analog-digital analyzer, a control trigger, a digital reference element, the first, second and third elements are additionally introduced. Additional elements And, information multiplexer, control multiplexer, register, address multiplexer, with the first inputs of information and control multiplexers connected to the first and second inputs of the driver, respectively, the first output of the analog-digital converter connected to the first RAM memory, the output of which is connected with the second input of the information multiplexer, and the output of the information multiplexer is connected to the first input of the register, the output of which is connected with the input of a digital-to-analog converter, the first input of the analog-digital converter is connected to the third input of the imaging device, the output of the main counter is connected to the first inputs of the address multiplexer and digital reference element, the output of the additional counter is connected to the second input of the address multiplexer, the output of Kotoporo is connected to the second input of the operational memory device, the second output of the analog-digital converter is connected to the input of the delay element, with the second input of the element And, the first inputs of the main counter, first and vtorog additional elements D and the third input of the address multiplexer, a clock pulse generator output is connected to a second input of the analog-chi rovogo transducer and the first input of the third supplementary element, and an output connected to

the second input of the control multiplexer and its output are connected to the second input of the register, the second input of the digital comparison element is connected to the fourth input of the device, and the output is connected to the second input of the first additional element And whose output is connected to the first input of the trigger, the output of the second additional element And connected to the first input of the additional counter; the equal trigger is connected to the third inputs of the information and control multiplexers, the second inputs of the main counter, the additional counter, the trigger and the pulse clock generator input, the first and second inputs of the control trigger are connected to the fifth and sixth formers of the generator, respectively, the output of the And trigger is connected with the third input of the operational storage device, the trigger output is connected to the second inputs of the second and third additional elements I.

Figure 1 shows the functional scheme of the proposed device; Fig. 2 shows voltage plots that clarify the principle of operation of the device; signals that act in the respective conductors and bus are indicated.

The shaper of a complex function contains the element 1 delay, ele. ment I2; clock pulse generator (GTI) 3, random access memory 4, main counter 5, additional counter 6, trigger 7, digital-to-analog converter (DAC) 8, connected by an output to output 9 of the device, analog-to-digital converter (ADC) 10, controlling trigger 11, digital comparison element 2, the first additional element I13, the second additional element I14, the third additional element I15, the information multiplexer 16, the control multiplexer 17, the register 18, the address multiplexer 19, and the output of the delay element 1 connected to the first input element And 2, the first inputs of the information 16 and control 17 multiplexers are connected to the first 20 and second 21 inputs of the device, respectively, the first output of the A / D converter 10 is connected to the first input of the random access memory 4, the output of which is connected to the second input S1 of the information multiplexer 16, the stroke of which is connected to the first input of the register 18, the output of which is connected to the input of the DAC 8, the first input of the ADC 10 is connected to the third input 22 of the device, the output of the main counter 5 is connected to the first inputs of the address mu A multiplexer 19 and a digital comparison element 12, the input of the additional counter 6 is connected to the second input of the address multiplexer 19, the output of which is connected to the input of the random access memory 4, the second output is connected to the first inputs of the address multiplexer 19 and the digital element of equation 12, the output of the additional counter b is connected to the second input of the address multiplexer 19, the output of which is connected to the second input of the random access memory 4, the second output of the ADC 10 is connected to the input of the delay element 1 with the second input element And 2, the first inputs of the main counter 5, the first additional element And 13 and the second, the additional element And 14 and the third input of the address multiplexer 19, the output of the clock generator 3 is connected to the second input of the ADC 10 and the first input of the third An additional element 15, the output of which is connected to the second input of the control multiplexer 17, and its output is connected to the second input of the register 18, the second input of the digital element 12, is connected to the fourth input 23 of the device, and the output to the second input the first additional element And 13, the output of which is connected to the first input of the trigger 7, the output of the second additional element And 14 is connected to the first (INPUT of the additional counter 6, and the output of the control trigger 11 is connected to the third inputs of the information 16 and control 17 multiplexers second inputs the main 5 and additional 6 counters, the trigger 7 and the input of the clock pulse generator 3, the first and second inputs of the control trigger are connected to the fifth 24 and sixth 25 inputs of the device, respectively, the output of the And 2 element It is only one with the third input of the random access memory 4, the output of the trigger 7 is connected to the second inputs of the second 14 and third 15 additional elements I. Figure 2 shows plots (26-37) of signals at the outputs of the blocks of the controlling trigger 11, generator 3 clock pulses , A / D converter 10, delay element 1, element 2, main counter 5, digital comparison element 12, first additional element 13, trigger 7, third additional element 15, second second element 14 and additional counter 6, respectively. The device operates in two modes Prepare and Play. The first inputs of counters 5 and 6 are counting inputs, the second inputs of zeroing, the first and second inputs of multiplexers 16-19 are informational, and the third control inputs. I In Prepare mode, the Stop signal at the sixth input 25 of the device enters the second input of control trigger 11 and zeroes it, the signal from its output zeroes across the second (zeroing inputs) inputs of counters 5 and 6 and the second (zero input) input trigger 7. The same signal blocks the operation of the GTI 3, opens multiplexers 17 and 16 on the first input, generated by this time at the first input 20 of the device code: -the initial conditions are sent to the first (informational) input of the register 18. A signal arrives at the second input 21 of the device Record initial The word that goes through the multiplexer 17 to the second input (synchronization input) of register 18 goes to the DAC 8, which at its output generates the initial conditions voltage. In the Play mode, the Start signal goes to the fifth input 24 of the device and sets the trigger trigger 11 unit state and permits operation of generator 3 (plots 26 to 21 points in time i; /) in FIG. 2), opens multiplexers 16 and 17 on the second information inputs, i.e. the first (informational) input of register 18 is connected to the output of device 4, and the second input (synchronization input) of register 18 is connected to the output of the third additional element 15. The single signal at the output of control trigger 11 also stops blocking the operation of counters 5 and 6 and trigger 7. Clock pulses from the generator 3 are fed to the second input (start input) of the A / D converter 10, while the A / D converter 10 begins converting the analog voltage that goes to the third input 22 of the device into a digital code. When this code is fully formed. At the second output of the A / D converter 10, the signal End of Conversion appears (time t2. On plot 28 of Fig. 2). This signal opens multiplexer 19 at the first information input for the duration of its operation (from time point -t to time point -ti, plot 28, Fig. 2), while the output of counter 5 is connected to the second (address) input of unit 4. Besides of this, the signal of the conversion is fed to the third input (Record-read input) 4 through devices 4. through element I 2 (at its second input), element 1 delay and the first input of element II 2.: This ensures the recording of the ADC formed at the first output 10 codes in the storage device 4 at the address that is defined ate a content meter 5 (to measure -First recording - the zero address, time iT, on the diagram, Figure 2). Signal transmission The end of the conversion to the third input (Record input read) of device 4 through delay element 1 and element 2 is caused by the need to delay the write signal by the time delay of the write address code in multiplexer 19, as well as the need to finish recording before the counter 5 changes state which occurs at the cutoff of the signal End of Conversion (time t, in plots 28 and 30, Fig. 2). Thus, the front of the signal at the output of the And 2 element records the digital code of the input analogue value in the random access memory 4 at the address determined by the current state of the counter 5 (time instant ij, on the jam 30, FIG. The end of the conversion increases the current state of the counter by 1 38 unit (point in time plot 31, Fig. 2). Thus, j digital codes of the input analog value are written to successive cells of the storage device 4. Reading information from Device 4 also originates from consecutive cells, starting with zero, but with a delay of the number of ticks, determined by the digital code supplied to the fourth device input 23. This code will be called the control code Njnp (figure 2 shows the case when). Information from device 4 is fed to the first (informational) input of register 18 through the second input of multiplexer 16, and its reception in register 18 is synchronized by the output pulses of the third additional element 15, which passes through the second input of multiplexer 17 to the second input (synchronization input) of the register 18. The address of the memory cell 4, from which information is read, is determined by the contents of counter 6, the output of which is connected to the second (address) input of device 4 via the second input of multiplexer 19. Pulses from the output of the third additional element AND 15, over which the information is entered into the register 18 is synchronous and in phase with the generator 3 pulses (plots 27 and 35, Fig. 2), but starts with a delay determined by the control code (the moment of time ir / on plot 28 can be compared with Yemeni ig the diagram 35, Figure 2). Such a delay is as follows. The output pulses are constantly fed to the first input of the third additional element 15, but until the reading starts from block 4 (time point on plot 32 (Fig. 2). This element is closed by a zero signal on its second input from the output of trigger 7. The digital storage device 12, when the control code and the address of the current write address are equal (the output of counter 5), generates a single signal at its output (time instant Нg5 on plot 26, Fig. 2), which allows the signal to pass. The element AND 13 (time ig on plot 33, Fig. 2) to the first input (synchronization) of trigger 7. After the first such pulse (plot 33, Fig. 2), trigger 11 is set to one state (time. on plot 24 , figure 2), which opens the third additional element And 15 and the second additional element And 14. After that, the synchronization input register 13 begins to receive clock pulses that allow the code to be written to the register 18 (time point -t on plot 35 , Fig. 2) and through the second additional element I 14 I start to receive signals. On the first (counting) input of the counter 6, they increase its content by one (time tj, on plots 36 and 37, figure 2) after each step of the device operation. Thus, the proposed device allows delaying the input analog signal by the number of clock cycles corresponding to the control code. The proposed device, compared with the base object, has the following advantages: ease of setting the delay time (which is reduced to setting the pre-calculated value of the control code) and extending the range of time adjustment, delay. The latter advantage is confirmed by the following calculations. As can be seen from the principle of operation of the device, the delay time is related to the control code t3-Ab (, pM where -tj is the delay time of the input analog signal; At is the follow-up period of the output pulses from generator 3; Klvjnp is the decimal equivalent of the control code. The value of D.L determines the reproduction accuracy of the input function X F (Vf by the rate of its change (.1: because between these values there is the following relationship 3 d-h "Hoo / F (; t) / wqx where is the relative reproduction error V , (i),% Хп is the maximum value of the input variable jf (, the maximum value of the derivative of the input variable X (t) As can be seen from the principle of action biMnp.may -HtYiQy, where YT is the number of addresses of the operational storage device. If this is taken into account in formulas (1) and (2), we can write) tQ lOo / F (: t) By the formula (3) the maximum delay can be calculated, "various functions. For example, let us define the function x (t) io-sln 2гл-Р% Nwcxy tK The table shows the value t-iwy y calculated for different f by the formula (3). 0.01 {, 10400 104 10.4 1.04 These tables show the possibility of delaying the aiHanoroBoro signal for a time longer than 25 s, provided that the upper limit frequency of the spectrum of this signal does not exceed 4.17 Hz. Compared with the known, the proposed device also has an advantage over blocks of constant delay on magnetic storage devices on a tape, since it lacks the complex kinematic assemblies typical of storage devices on a magnetic tape. The functional diagram of the proposed device can be implemented on blocks that are widely used in electronic engineering, whose basic concepts can be fairly well developed.

Claims (1)

COMPOSITION FUNCTION FORMER containing a delay element, AND element, clock generator, random access memory, main counter, additional counter, trigger, digital-to-analog converter, the output of the delay element being connected to the first input of the And element, the output of the digital-to-analog converter connected to the output of the generator, о characterized in that, in order to expand its functionality by providing a delay control mode, an analog-to-digital conversion is introduced into the shaper a body, a control trigger, a digital comparison element, the first, second and third additional elements And, an information multiplexer, a control multiplexer, a register, an address multiplexer, the first inputs of the information and control multiplexers connected to the first and second inputs of the shaper, respectively, the first output of analog-digital the converter is connected to the first input of random access memory, the output of which is connected to the second input of the information multiplexer, and the output is information of the second multiplexer is connected to the first input of the register, the output of which is connected to the input of the digital-to-analog converter, the first input of the analog-to-digital converter is connected to the third input of the driver, the output of the main counter is connected to the first inputs of the address multiplexer and the digital comparison element, the output of the additional counter is connected to the second the input of the address multiplexer, the output of which is connected to the second input of the random-access memory, the second output of the analog-to-digital converter nen with the input of the delay element, with the second input of the AND element, the first inputs of the main counter, the first and second additional AND elements and the third input of the address multiplexer, the output of the generator of the same pulses is connected to the second input of the analog-to-digital converter and to the first input of the third additional element And, the output of which is connected to the second input of the control multiplexer, and its input is connected to the second input of the register, the second input of the digital comparison element is connected to the fourth input of the device, and output - with the second input of the first additional element And, the output of which is connected to the first input of the trigger, the output of the second additional element And is connected to the first input of the additional counter, the output of the control trigger is connected to the third inputs of the information and control multiplexers, the second inputs of the main counter, additional counter, the trigger and the input of the clock generator, the first and second inputs of the control trigger are connected to the fifth and sixth inputs of the shaper, respectively, the output TA and is connected to the third input of the RAM device, a trigger output connected to second inputs of the second and third elements of the additional AND;