SU1596446A2 - Digital multiplier of recurrence rate of periodic pulses - Google Patents

Abstract

The invention can be used in measuring and frequency converters with a small error of discreteness. The purpose of the invention is to improve accuracy by allowing phasing of input and output pulses with a fractional multiplication factor - achieved by introducing dividers 8 and 9. The device also includes a clock pulse generator 1, element 2, frequency divider 3, pulse counter 4, storage register 5, divider 6 frequency with a variable division factor, control unit 10, driver 11 pulses and input and output buses 7 and 12. 2 Il.

Description

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The invention relates to radio engineering and digital measurement technology and can be used in measuring. bodies and frequency converters with a small error of discreteness.

Depy of the invention - increase of accuracy due to the possibility of phasing of input and output pulses with a different value of the multiplication factor

FIG. 1 shows an electrical block diagram of a digital multiplier for the frequency of following a periodic pulse; on - time diagrams that show his work.

The device contains a generator of 1 clock pulses, the output of which is connected to the first input of the element 2 and the clock input of the first divider 3 frequencies (with a division factor - K), the output of which is connected to the counting input of the counter 4 pulses, the outputs of which through the storage register 5 are connected to information inputs of the divider 6 with the current division factor. Input bus 7 is connected via the second frequency divider 8 (with the division factor M) to the reset input of the third frequency divider 9 (with the division factor M), through the control unit 10 with the second input of the I 2 element, through the driver 11 pulses with the reset inputs of the first a frequency divider 3 and a pulse counter 4 and directly at the input of the storage register 5. The output of the divider 6 with a variable division factor is connected to the clock input of the third frequency divider 9, the output of which is connected to the output bus 12

The periodic frequency pulse frequency multiplier operates as follows.

In the initial state, the output of block 10 is low, prohibiting the passage of pulses from the output of the generator 1 to the clock input of the divider 6, which eliminates the possibility of generating a false code frequency ..

Bus 7 receives a periodic sequence of pulses (Fig. 2a with frequency Fg o). Pulse 7 produces a pulse at the output of shaper 11, tilting divider 3 and counter 4 "Next, the counter 4 is filled with pulses (Fig. 26) of the generator 1, having passed divider 3 and having a frequency K times smaller than the frequency FT at the output of the generator 1. To the arrival of the next input pulse in

counter 4 will be the number N --- -F / K.

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On the pulse front on bus 7, this number is recorded in register 5 and fed to the information inputs of divider 6. With the arrival of the second and subsequent pulses on bus 7, the output of block 10 is set to a high level, permitting the passage of pulses from the generator 1 to the clock input of the divider 6o This. The frequency of the pulses (Figs. 2d) at the output of the divider 6 is equal to F FOX-Co. Bus 12 from the output of the divider 8 receives pulses (Figure 2d) whose frequency is equal to F. The F / Mo phase of these pulses is determined by the phase of the whip divider 9 pulses (Fig. 2c), post Payuschie output from the divider 8 "The frequency of these pulses is Fj.

Thus, the introduction of forced zeroing of the divider by 9 input pulses passed through divider 8 provides for phasing of the output pulses at a fractional device multiplication factor (in FIG. 2, time diagrams correspond to a device multiplication factor equal to K / K / M 4/3) „

Claims (1)

Invention Formula The digital frequency multiplier follows the periodic impulses by. No. 1164858, characterized in that, in order to improve accuracy by allowing phasing of input and output pulses with a fractional multiplication factor, a second frequency divider and a third frequency divider, which is connected between the output of the frequency divider with a variable division factor and the output one, are entered into it. bus and reset input which through the second frequency divider is connected to the input bus " , "but "Have N i: m " N CU ъ