SU790344A1 - Pulse repetition frequency multiplier - Google Patents

Description

The invention relates to measuring technology, automation and can be used in medical electronic equipment. A pulse multiplying frequency multiplier is known, which contains delay elements whose inputs are connected to the multiplier input, and outputs to the inputs of the OR pulse combining circuit whose output is connected to the multiplier output l. The disadvantage of this multiplier is the impossibility of normal operation of the frequency range without rebuilding the values of the magnitude of the delays. The introduction of adjustment elements increases the size of the facility. The closest technical solution to the proposed one is an impulse frequency multiplier, containing a reference frequency generator, an input driver, the output of which is connected via a control unit to the inputs of the first pulse counter of the series-connected and storage register, whose outputs are through the second block the transfer is connected to the installation inputs of the code of the second pulse counter, moreover, the zero input of the first trigger is connected to the output of the input shaper; The first input of the first pulse counter is connected to the first input of the first matching element, and the output of the second pulse counter is connected to the output of the second matching element, the first input of which is connected to the output of the reference generator. frequencies, and the second with a single output of the second trigger, the zero input of which is connected to the output of the second pulse counter, as well as two delay lines, the input of one of which is connected to the output of the second pulse counter, its n The second output is the unit input of the second trigger, the second output is to the setup input of the second counter, the third output is connected to the input of the second transfer unit, and the other delay line is connected between the output of the input driver and the single input of the first trigger .2 J The disadvantage of this device is the fact that, if necessary, measuring the multiplication factor over a wide range, besides the change in the ratio-

laziness t

to t

also necessary

on

9T

It is difficult to fit the delay values of the first and second lines, because of the design of the multiplier, the a-to-device operation is very difficult. The disadvantages of this device are also large dimensions of the structure, weight and energy consumption, and, consequently, its reliability is low.

The aim of the invention is to increase reliability.

The goal is achieved by the fact that a pulse multiplying frequency multiplier, containing a reference frequency generator, the output of which is connected to the input of the first pulse counter via a coincidence element, a control unit whose input is connected to the input bus through the pulse shaper, and the first and second outputs are respectively the inputs of the installation of the first pulse counter and the resolution of the recording of the memory register connected in series, a trigger, the output of which is connected to the second input. the coincidence element, the second pulse counter, the control input of which is connected to the generator output this onnry frequency, a code comparison unit is introduced, the first and second groups of bits of which bits are connected to the outputs of the bits of the storage register and the second pulse counter, the reset input of which is connected to output of the code comparison block.

The drawing shows a structural electrical multiplier circuit diagram of traces of an.

The device contains a reference frequency generator 1, the output of which is connected to the first input of coincidence element 2, the second input of which is connected to the output of trigger 3, the input driver 4, the output of which is connected to the input of control unit 5, the first output of which is connected to the recording input of the storage register 6, second exit -

first

with the installation input in

pulse counter 7, a third output with a counting trigger input 3, a reference frequency generator 8, the output of which is connected to the counting input of the second pulse counter 9, a code comparison unit 10, the first bit inputs of which are connected to the corresponding bit outputs of the storage register b, the second bits the common inputs are connected to the corresponding bit outputs of the second counter 8 pulses

The device works as follows.

The pulses of the signal, the frequency of which is subject to multiplication, through the shaper driver 4 is fed to the input

control unit 5. The control unit 5, for each input pulse, triggers three pulses shifted in time relative to each other. The first of them arrives at the input of the storage register b and allows writing the code into it, which up to this point was on the output bit buses of the first counter.

The second pulse arrives at the current of the first counter 7 and sets all bits to the zero state in it, and the third arrives at the counting, the input of the trigger 3. At the output of the trigger 3 with a period T there appear single pulses of duration Tgj, which are opened at the first input item 2 match. At the same time, the pulses arrive at the counting input of the first counter 7 through the second input of the coincidence element 2 from the frequency generator 1. During the period T of the pulses of the multiplied frequency Fgj, the counter 7 receives the number of pulses equal to TB.

N-Hop (1).

This number is entered as a code in the memory register 6 after it arrives (via the driver 4 and the control block 5) to its input to enable the recording of the next pulse of the signal.

This code from the output of the memory register 6 is fed to the first separate inputs of the code comparison unit 10. A code from the bit outputs of the second counter 9, which counts the pulses coming from the generator 8 of the reference frequency, is fed to its second bit inputs. Moreover, when the code value at the output of the counter 9 becomes equal to N, the output of the code comparison block 10 is a pulse, which sets the bits of the counter 9 to the zero state, etc.

The pulses from the output of block 10 are fed to the output of the multiplier. The output frequency is N times less than the generator frequency.

8 F

and is

at

with

(2)

top N

but according to formula (1), Nili

NI bgv pbh

(3)

Substituting formula (3) into expression (2), we obtain

Where

K-- - ROP

(four)

By varying the ratio of F. to Pp, the frequency multiplication factor can be varied over a wide range. In this case, no adjustment of the parameters included in the device elements is required.

Claims (2)

Invention Formula A pulse frequency multiplier containing a reference frequency generator, the output of which is through the coincidence element is connected to the input of the first pulse counter, a control unit whose input through the input pulse shaper is connected to the input bus and the first and second outputs to the inputs of the first pulse counter, respectively. and enable recording of the storage register, connected in series, trigger, the output of which is connected to the second input of the element coincidence, the second pulse counter, the control input of which is connected to the output of the reference frequency generator, characterized in that, in order to increase the reliability of the device, a code comparison unit is entered into it, the first and second groups of input bits of which are connected respectively to the output bits of the storage bits a register and a second pulse counter, the reset input of which is connected to the output of the code comparison unit. Irtochniki information taken into account during the examination 1. The author's certificate of the USSR 518869, cl. H 03 K 23/00, 1974. 2. USSR author's certificate 533510, cl. H 03 K 23/00, 1974. f 8g ten