SU538334A1 - Series meter time intervals - Google Patents

Description

one

The invention relates to the field of radio electronics and can be used in devices for measuring time.

A series of time interval meters are known that contain a reference frequency pulse generator, a counter, the outputs of each bit of which are connected to the inputs of memory 2 through a readout unit, however. The complexity of the circuit and the low reliability are noted.

Also known is a meter containing a reference frequency pulse generator connected in series through a key to a counter input of the counter, the output of the first time series of which is connected via a delay line to the input of a second key, a extender whose output is connected to the input of a third key, a second delay line and a memory device l. However, such meters have a counter with a large number of bits and low speed.

The proposed meter differs in that in order to reduce the number of bits of the counter and increase speed, sequentially connected trigger, a fourth key and a driver, the output of which is connected to the second input of the second key, are entered to the inputs of all the bits of the counter and the first input of the trigger, the second input of which connected to the output of the third key, the second input of the third key is connected to the output of the second delay line, whose input is connected to the generator output pulse of the reference frequency, also connected to the second entry in the fourth key, and a second output latch coupled to the second input of the first switch, the second switch output is connected to the input of the first discharge storage device, and inputs the remaining bits of the storage device directly connected to respective counter outputs.

In the drawing p; ekazana structural diagram of the meter series of time intervals.

The meter series of time intervals consists of a pulse generator of the reference frequency 1, keys 2-5, pulse counter with simultaneous transfer 6, delay lines 7 and 8, pulse spreader 9, trigger 10, driver 11 and memory 12. The meter works as follows. The first impulse of the series goes to the expander 9 and opens the key 3. Another 6 impulse from the generator 1, passed through the delay line 7 and the key 3, enters the zero input of the trigger 10, As a result, the trigger 10 goes into the zero state and the key 2 closes and key 4 opens. The next lO pulse from generator 1, having passed through key 4, goes to shaper 11. The latter translates trigger 10 and the first digit of counter 6 into one state and resets the remaining bits 5 of counter 6 to zero. From this moment the counter starts filling. 6, which continues until the next impulse 9 is detected at the input of the expander 9. Further operation of the meter is similar to the above. The values of the unit states of the bits of the counter 6 are transferred to the storage device to the first discharge by the pulse of the former through the key 5, which is open if the first discharge of the counter 6 is in the unified state, and to the remaining bits of the storage device 12 - with the help of pulses arising at the dynamic outputs of those bits of counter 6, which under the influence of a reset pulse, the transition is t y

from one to zero state.

The delay line 7 eliminates the cut-off of the pulse part by key 2, and the delay line 8

the appearance of a pulse at the output of the key 5 35 when the first discharge of counter 6 is transferred from the zero state to one.

chica.

Sources of information taken into account in the examination:

1. USSR Author's Certificate No. 369542, G 04 F 10/04, 07/27/1970.

2. USSR author's certificate No. 259702, G O4 F 1O / 04. 26.1 OD 970.

Claims (1)

 The invention The meter series of time intervals. containing a reference frequency pulse generator connected in series through a key to a counter input of the counter, the output of the first bit of which is connected via a delay line to the input of a second key, a extender whose output is connected to the input of a third key, a second delay line and a memory device, and so that, in order to reduce the number of bits of the counter and increase speed, sequentially connected trigger, the fourth key and driver, the output of which is connected to the second input The second key, with inputs of all bits of the counter and with the first trigger input, the second input of which is connected to the output of the third key, the second input of the third key connected to the output of the second delay line, whose input is connected to the output of the reference frequency generator, also connected to the second input of the fourth key, and the second output of the trigger is connected to the second input of the first key, the output of the second key is connected to the input of the first bit of the storage device, and the inputs of the remaining bits of the storage device properly connected to the corresponding outlets