SU451019A1 - Phase shifter - Google Patents

Description

one

The invention relates to a phase-measuring technique.

A phase shifter is known that contains an input voltage driver, a time delay node that includes a frequency multiplier and a scaling circuit, as well as a phase-shifted output voltage driver.

However, the accuracy of such a device is limited by the accuracy of the frequency multiplier, and the multiplier is a fairly complex device .;

The purpose of the invention is to improve the accuracy of maintaining a given phase shift in the frequency range .:

For this purpose, in the proposed device I, the time delay node is made of two; reversible counters, frequency generator, Frequency generator 1, inverzra and four coincidence circuits, the output of the input signal shaper connecting with the first inputs of the third and third matching circuits and the input of the inverter whose output is connected to the first inputs of the second and fourth matching circuits, the output of the frequency generator F through the first matching circuit is connected to the input of the addition of the first, reversible counter and through the fourth; the coincidence circuit is connected with the addition input of the second reversible counter, the output of the frequency generator 2F via the second circuit is sov-. the drop is connected to the subtracting input of the first I: reversible counter and through the third matching circuit to the subtracting input of the second reversible counter, the direct outputs of the higher first and second bits, the counters are connected to the inputs of the output 1fat (l, and their inverse outputs with inputs of the second and third match schemes, respectively.

The drawing shows a block diagram of the proposed device.

The device consists of mi vata l 1, an inverter 2, a generator 3 of frequency 2f, a generator 4 of frequency F, a matching circuit of 5-8, reversible counters 9 and 10, and a driver 11, left) but output voltage.

The device operates as follows: 1

a common voltage where it is formed into rectangular pulses of positive polarity.

A pulse corresponding to the positive half-cycle of the input voltage opens the coincidence circuit S, through which the pulses from the generator 4 with a frequency F are supplied to the input of the reversing counter 9. These pulses fill the reversible counter for the entire duration of the positive half-cycle of the input voltage, open a matching circuit 5 through which pulses from generator 4 with a frequency F are supplied to the input of the reversing counter 9. These pulses fill the reversible counter for the duration of the positive half of the half cycle. At the end of the last, a pulse from the output of the inverter opens a matching circuit 6, through which the pulses with frequency ZF from generator 3 are fed to the input of the subtraction of the reversible counter 9. The subtraction occurs until the number recorded in the counter decreases to O, after whereby the next pulse of the generator 3 sets all the bits of the counter to 1, and at the inverse output of the high bit there appears a potential closing the coincidence circuit 6.

Since the frequency of the filling pulses when subtracting is twice as large; than with addition, the subtraction is concluded in a time equal to a quarter of a period.

With the arrival of the next positive half cycle of the input voltage, the described operation cycle repeats.

Thus, at the output of the reversible counter 9, pulses occur, marking} o-. the moment of transition of the negative input voltage half through maximum

The second part of the circuit works similarly, including the coincidence patterns 7 and 8 and the reversible counter 1O with the difference that all processes in it are shifted by half a period using inversion 1x2. Pa of the output of the counter 10 pulses occur, marking the transition moment of a positive half wave input

voltage through maximum. The outputs of the counters 9 and 1O are connected to the inputs of the form; Rovatel 11, forming follower:. the symmetry of pulses, the fronts of which are shifted in phase by 90 relative to the moments of the transition of the input voltage is zero woov .., |

The failure rate of maintaining the 90th phase shift is mainly determined by the failure rate of the forming device, since the failure rate due to the time delay discreteness can be made negligible by proportional

increase frequencies F and 2g

Subject invention

A phase shifter containing an input voltage driver,

a time delay node and a phase-shifted output voltage driver, characterized in that, in order to increase the accuracy of maintaining a given phase shift in the frequency range, the time delay node is made of two reversible counters, a frequency generator p, a 2F frequency generator, an inverter and four circuits matches, with one BXO-J of the first and third coincidence circuits connected to the output of the input driver connected to the input of the inverter, the output of which is connected to the first inputs of the second and fourth circuits with The output of the frequency generator F through the first matching circuit is connected to the input of the first reversible counter and via the fourth matching circuit to the input of the second reversible counter, the output of the 2G frequency generator is connected to the subtraction input of the first reversible counter through the third the coincidence circuit — with the subtraction input of the second reversible counter; the forward outputs of the higher bits of the first and second counters are connected to the inputs of the output driver, and their inverse outputs — with the inputs of the second and third matching circuits, respectively;

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