SU484645A1 - Pulse frequency division device - Google Patents

Description

one

The invention relates to the field of pulse and computer technology and can be used in various devices of discrete action (frequency synthesizers, frequency manipulators, etc.).

A counting device is known that contains a signal source, a binary counter, the outputs of which through a decoder are connected to the inputs of the OR circuit. However, the known device does not provide a division with an odd division factor and does not preserve the ratio of the pulse duration to the output pause equal to 1: 1.

The aim of the invention is to maintain the ratio of pulse duration and pause at the output, equal to 1: 1 with an odd division factor.

For this, one of the inputs of the decoder is connected to the "lemma of the power source, and the output to one of the control inputs of the binary counter, the other control input of which is connected to the output of the OR circuit.

A block diagram of a pulse frequency division device is shown in the drawing.

The device for dividing the pulse frequency consists of a decoder 1 connected to the outputs of binary counter 2 and to terminal 3 of the signal source, the first output of decoder 1 is connected to one of the control inputs of binary counter 2, and the second and third outputs through the OR 4 s circuit another control input of binary counter 2.

The device works as follows.

A sequence of pulses is applied to the input of the device with the ratio of the pulse duration to the duration: the pause interval is 1: 1. The transition of the counter from one state to another occurs at the moment when the positive edge of the pulse appears on its counting or control inputs.

At the moment in time to, the binary counter 2 goes into the final () state, with the negative edge of the pulse appearing at the first output of the decoder 1. Then, at the moment when the trailing edge of the input pulse appears, at the first Output of the decoder 1 a positive edge of the pulse appears, which goes to the first control input of the binary counter 2 and sets it to the next state (state "O"). Thus, the installation of the binary counter 2 at the first control input to the state "O" is carried out ahead of the length of the pause between the input pulses. By introducing feedback, the operation cycle of the device is reduced by one and the division factor becomes equal, and the pulse duration and

output pauses are reduced equally - by half the period of the input signal.

The ratio of the pulse duration to the pause length at the output of the device, equal to 1: 1, at dividing coefficients is provided by adding one pulse at the first control input in the manner described. In this case, the decoder 1 degenerates into a " And n + 1 inputs logic circuit.

To obtain odd division factors, it is necessary during the operation of the binary counter 2 dry cycle, to add an additional number of pulses. The number of additionally added pulses is obviously even and is determined by the formula: () -K, where K is the division factor;

n is the number of bits of binary counter 2.

In order to keep the ratio of the pulse duration to the pause length at the output of the device equal to 1: 1, the addition of additional pulses is carried out in two steps in equal parts; the first addition is performed during the first half of the cycle of the binary counter 2, and the second addition is performed during the second and half cycles. In this case, both the pulse duration and the pause duration are reduced equally, and, consequently, their ratio is preserved. Adding additional pulses of drying is established by means of a feedback circuit through the second control input of binary counter 2. For example, at the moment binary 2 goes to a certain state in the first half of the cycle, the second output of the decoder 1 appears front of impulse. At the moment when the trailing edge of the input pulse appears at the second output of the decoder 1, a positive edge of the pulse appears, which through the OR 4 circuit goes to the second control input of the binary counter 2 and sets it to a certain state, which is equivalent to adding two additional pulses. At the moment of transition of the binary counter 2 in

another state at the third output of the decoder 1 appears negative edge of the pulse. Further, when the trailing edge of the input pulse appears at the third output of the decoder 1,

the front of the pulse, which through the OR 4 scheme goes to the second control input of binary counter 2, sets it to a different state, which is equivalent to adding the required number of additional pulses. By the input pulse, binary counter 2 is reset. Then the second cycle of the device operation, etc., begins.

Subject invention

A device for dividing the pulse frequency, containing a signal source, a binary counter, whose outputs are connected through the decoder to the inputs of the OR circuit, characterized in that, in order to maintain the ratio of pulse durations and pause at the output, 1: 1 at the division factor, one from the inputs of the decoder is connected to the power supply terminal, and the output to one of the control inputs of the binary counter, the other control input of which is connected to the output of the OR circuit.