SU913369A1 - Squarer - Google Patents

Description

The invention relates to computing and can be used in computing devices for processing information about the progress of technological processes.

Known devices that perform the operation of squaring [1].

The disadvantages of these devices include reduced accuracy and computation and implementation complexity.

The closest to the proposed - the technical essence is

a device containing a pulse generator, a controlled frequency divider, two binary counters, a comparison circuit, an AND element, a trigger £ 2].

However, the presence of a comparison circuit in the device complicates its implementation, since with a capacitance of 2 ^P counters it is necessary to have η comparison elements and one n-input assembly scheme, or η inverters and (n-1) bit adder. The disadvantage of the device is

2

the relative complexity of its implementation, consisting in the presence of a comparison circuit and reducing its operational reliability.

The purpose of the invention is to simplify the scheme.

This goal is achieved by the fact that the quad, containing a pulse generator, the output connected to the input of a controlled frequency divider, the output of which is connected to the first input of the first element And whose output is the output of the device, trigger, the inverse output of which is connected to the second input of the first element And, binary the counter, the bit outputs of which from the first to η (where η is the width of the counter and the controlled frequency divider) are connected respectively to (p-1 ... 1) inputs of the controlled frequency divider, contains a reversible the counter and the second element And, and the input of the addition of the reversible counter is connected to input 3 913369

the house of the binary counter, the input of the subtraction - with the output of the second element I, and the output of the overflow - with the input of the trigger setup, the reset input of which is connected to the quad clock input and the inverse output is connected to the first input of the second element I, the second input is connected to the output of the lth discharge controlled frequency divider.

The drawing shows a quadrant circuit.

The quadrator contains 1 pulse generator, controlled frequency divider 2 (UDCH 2), first element 3, trigger 4, binary counter 5, reversing counter 6, second element 7 and synchronous input 8 of the device.

The principle of operation of the device is as follows.

Bit 2 UDCH binary counter 5 and the down counter 6 are equal to 2 ^n. When writing to the counter 5, the number x is written to the addition input in the reversible counter 6, and at the output of the UDCH 2 a frequency is produced

= (1)

. where ίο is the frequency of the pulse generator 1.

The second input element And 7 receives impulses from the output of the last discharge of UDCH 2, the repetition rate which is P _in / 2 ^P.

When applied to the clock terminal 8 sync trigger 4 of the device is set to "ON", allowing the passage of pulses of frequency F _s via the first AND gate 3 to the output device and the pulse frequency ί ^_0/2-P through a second AND gate 7 to the subtraction input of down counter 6.

After receipt of x pulses of this frequency, the number "O" is written in the reversible counter 6 and a pulse appears at its output overflow, setting trigger 4 to state "1" (on the 5th output) and prohibiting the passage of pulses through IZ elements, 7 ·

A new squares cycle begins.

Thus, at the inverse output of the trigger 4 there is a level "1" from the moment of arrival at the input 8 of the sync pulse until the moment of receipt of x frequency pulses

four

P _0/2 ^l 'to the input of the subtraction of the reversible counter 6.

The duration of this level:

5 During this time "at the output of the device (element I 3) the number of pulses appears in accordance with expressions 1, 2

Y = ίχ T _x = _x 2- (h)

10 In the proposed device, there is no comparison circuit and one of the binary counters, which, while maintaining the advantages of the known, simplifies the circuit implementation.

15 and creates the effect of improving the operational reliability of the device.

20

Claims (1)

Claim Quadrator containing a pulse generator, the output connected to the input of a controlled frequency divider, 25 whose output is connected to the first input of the first element And whose output is the device output, trigger, the inverse output of which is connected to the second input of the first 30 element And, binary counter, bit outputs which from the first to η (where η is the width of the counter and the controlled frequency divider) are connected respectively to (n-1 .., 1) The 35 inputs of a controlled frequency divider are different in that, for the purpose of simplification, it contains a reversible counter and a second element AND, the addition input of the reversible counter being connected to the input of a binary counter, the subtraction input - with the output of the second element I, and the overflow output - with the input the trigger settings, the reset input of which is connected to the ₄₅ with the synchronous input of the quad, and the inverse output is connected to the first input of the second element I, the second input of which is connected to the output of the ηth digit of the controlled frequency divider.