SU746514A1 - Discrete pulse repetition frequency multiplier - Google Patents

Description

OH contains the first generator 1 of the reference frequency pulses, the first counter 2 pulses, the memory block 3, the 4 coincidence block, the second g-generator 5 impulses of the reference frequency, the second counter 6 j pulses, the logical side 7, the output block 8.

The first frequency generator of the frequency signal is connected in series with the counter meter 2, memory block 3, block 4 matches.

The second generator 5 pulses of the reference frequency is connected to the second counter with the second counter 6, the logic block g 7, the output block 8, the block 4 matches, is

The output of the unit 4 dropping is with the installation inputs of the second counter 6. The input of the first counter 2 is connected to the input of the unit 3 of the memory.

The device works as follows.

When the input potential frequency permits, to be multiplied by the installation input of the first counter 2, the last 25 counting pulses of the generator 1 are filled. At the end of the resolving potential, the received code is written into the block: 3 pck rk C: .block 3 memory code in parallel, enters block 4 of matches, which consists of a set of two AND code elements, the first inputs of which are connected by the corresponding bits of memory block 3, and the second codes are connected to the output of an advantageous block 8.35

Thus, block 4 passes the code only if there is a gaps from the output block 8, the second counter 6 continuously receives pulses from the generator 5 s. a frequency different from the frequency of the pulses 40 of the generator 1 n times. The generator code is continuously fed to block 7 (de-state} zero state state). Counting is used on subtraction. In mShent time, when on the second counter 6, the image is 45 vals zero code, block 7 generates

746514

a pulse, which, after passing through the output unit 8, goes to unit 4, the code from memory block 3 passes through unit 4 to the installation inputs of the second counter. 6. Thus, a counter proportional to the frequency multiplied is entered into counter 6. It is then read to the zero state and the process continues further. With the output of the output block 8, the signal is removed with a frequency n times different from the input.

The positive effect of the invention is to reduce the material costs required to implement the device while maintaining the other characteristics of the prototype, reducing power consumption, size, weight; cost, increased device reliability.

Claims (2)

Invention Formula , - ,. The discrete pulse multiplying frequency multiplier, containing the first and second reference frequency pulse generators, the outputs of which are connected to the inputs of the first and second pulse counters, a memory unit, the control input of which is connected to the installation input of the first pulse counter and the input bus, and the input is with the output of the first pulse counter, and the output block, the input of which is connected via a logic block to the output of the second pulse counter, characterized in that, in order to increase the efficiency of the device, A match block was entered, the inputs of which are connected to the output of the memory block and the output of the output block, and the output to the installation input of the second pulse counter. Sources of information taken into account in the examination 1, USSR Author's Certificate 423126, cl. G 06 F 7/52, 1971. 2. US patent number 3798564, cl. 331-1, 1974.