SU824415A1 - Pulse series generator - Google Patents

Description

(54) PULSE GENERATOR PULSES

The invention relates to a pulse technique and can be used in software-temporary devices and control devices.

A device for generating a pulse pulse comprising a pulse counter, a comparison unit, a frequency generator, triggers, and NOT and AND 1 elements is known.

The drawback of the device is the impossibility of obtaining output pulses with a constant frequency of their repetition.

The closest technical solution to the present invention is a device for generating a series of pulses containing a series-connected control trigger, a controlled oscillator, a pulse counter, n triggers, n And elements and nd driver elements connected through comparison elements, the outputs of which are connected to the inputs triggers, with counter outputs.

The disadvantage of this device is its complexity and, as a result, reduced reliability. This is due to the fact that in order to receive signals at the n outputs, it is necessary to set up devices for comparing codes consisting of K reference elements.

The purpose of the invention is to increase the reliability of the generator.

The goal is achieved by the fact that the pulse generator containing

Claims (2)

clock generator, pulse counter, the output of which is connected to the first input of the control trigger, the bit outputs of the pulse counter are connected to the first inputs of the code comparison block, specifying elements, AND elements, additionally introduced the AND element, delay element, OR elements and shift register, the bit outputs of which are connected to the first inputs of the AND elements, the second inputs of which are connected to the corresponding outputs of the driver elements, and the outputs of the elements AND through the corresponding elements OR are connected to the second in Odes of the code comparison unit, the output of which is connected to the first bit input of the shift register, the remaining bit inputs of which are connected to the second input of the control trigger through the delay element, the output of which is connected to the first input of the additional element And, the second bypass is connected to the output of the clock generator pulses, and the output is connected to the input of the pulse counter., The drawing shows the functional diagram of the generator of packets of pulses. The generator contains a generator of 1 clock pulses, an additional element AND 2 counter 3 pulses, block 4 comparison of codes, defining elements 5, control trigger 6, shift register 7 AND elements 8, elements OR 9, delay element 10, output buses 11 and 12, 13 “Start. The operation of the generator is as follows. Before the start of the next cycle of operation, the control trigger 6 is in the zero state and the signals of the generator 1 are not fed to the counter 3 pulses. In all bits of the 7 shift register, zeros are written. A signal arriving at the bus 13, the first bit of the shift register 7 is entered in the unit. At the same signal, after a time determined by the delay element 10, the control trigger 6 tilts and the generator 1 pulses through the element 2 2 to the input of the counter 3 pulses. At the moment of equality of the code, at the outputs of the counter 3 pulses, the code of the driver elements 5, coming through the AND 8 elements and the OR 9 element to the inputs of the code comparison unit 4, opened by the first bit of the shift register 7, a voltage pulse is generated at the output of this block 4. The same pulse records the unit from the first to the second bit of the shift register 7, and the leading edge of the first output pulse is formed on the output bus 11. The inputs of block 4 compare the codes through the elements AND 8 and the elements OR 9 are connected to the outputs of the master elements 5. If the codes on the outputs of the counter of 3 pulses and the master elements 5 are equal, the unit is written to the third digit of the shift register 7 and the back edge of the pulse is formed on the output bus 11. Annealing of the next output pulse occurs in a similar way. Thus, by setting the values of the codes of the driver elements 5, it is possible to form a sequence of rectangular voltage pulses of different duration at any time during an operating cycle. At the end of the cycle, the signal from the output of the pulse counter 3 overturns the control trigger 6, and the pulses from the generator I do not pass through the element 2. The invention The pulse burst generator containing a clock generator, a pulse counter, the output of which is connected to the first control input the trigger outputs, the bit outputs of the pulse counter are connected to the first inputs of the code comparison unit, the driver elements, the AND elements, characterized in that, in order to increase the reliability of the generator, additional elements are introduced into it ent And, a delay element or elements and shift register The discharge outlets are connected to first inputs of AND gates; the second inputs of which are connected to the corresponding outputs of the setting elements, and the outputs of the elements AND through the corresponding elements OR are connected to the second inputs of the code comparison unit, the output of which is connected to the first bit input of the shift register, the remaining bit inputs of which are connected to the second control input trigger, the output of which is connected to the first input of an additional element I, the second input of which is connected to the output of the clock generator, an output connected to the input of the counter and pulses. Sources of information taken into account in the examination 1. USSR author's certificate number 493902, cl. H 03 K 3/64, 1972. 2. USSR author's certificate No. 630735, cl. H 03 K 3/64, 1977.