SU1377761A1 - Method of transforming frequency transient process to voltage function - Google Patents

Abstract

The invention serves to increase the accuracy of converting a frequency transient process to a voltage function. From the highly stable frequencies, the tots form a single reference interval (I) equal to the period of the nominal frequency. The reference and measuring And form of a single reference And periods of the investigated frequency. The formation is carried out by simultaneously increasing them by the value of the unit reference AND and the period of the studied frequency, respectively, until a given difference in the durations of the reference and investigated I. After obtaining the specified difference, the conversion process is repeated. A continuous frequency change is transformed into a sequence of quantized voltage samples following a variable sampling rate. 2 Il. i SL

Description

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This invention relates to a technique for studying frequency transients.

The aim of the invention is to improve the accuracy of converting a frequency transient to a voltage function.

The essence of the method is that a single reference interval, equal to the nominal frequency period, is formed from a highly stable frequency, and the reference and measurement intervals are formed from single reference intervals and periods of the frequency under investigation, respectively, by simultaneously increasing them by the value of the single reference interval and the period the studied frequency, respectively, to obtain a given difference in the duality of the reference and investigated intervals. After receiving the given; the difference between the indicated intervals the conversion process is repeated. A continuous change in frequency is transformed into a sequence of quantized voltage samples following a variable discretization step (the discretization step corresponds to the larger of the studied and reference intervals).

Figure 1 shows the block diagram of the device for implementing the method; figure 2 - timing charts of the device.

The block diagram (figure 1) consists of the first element AND 1, the second 2 and third 3 dividers, the first delay line 4, the first counter 5, the first driver 6 pulses, trigger 7, the element EXCLUSIVE OR 8, the second element AND 9, the second the counter 10, the converter 11, the code is the voltage of the storage unit 12, the second pulse shaper 1.3, the third divider 14, the second delay line 15, the register 16, the comparison block 17.

The device contains the first element AND 1 connected to the output of the first divider 2, the counting input of the first counter 5 and the element AND 9, the output of the divider 2 is connected to the input of the second divider 3, the inverting output of which is connected to the input of the element EXCLUSIVE OR 8, line 4 delay, the output connected to the input of the zeroing of the counter 5, the code of which is connected to the input

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Converter I1 code — voltage and input of pulse generator 6, the output of which is connected to the input of delay line 4, the control input of memory 12, the first input of trigger 7, the output of comparison block 17 and the zero inputs of dividers 2, 3 and 14, trigger output 7 connected to the second input element AND 1, the output of the EXCLUSIVE OR element 8 is connected to the second input of the element AND 9 and the second input of the delay line 15, the output of which is connected to the counting input of the second counter 10, the output of which is connected to the input of the comparison block 17, the output conversion Overt II code - voltage is connected to the input of storage unit 12, the output of the second pulse shaper 13 is connected to the second input of the trigger 7 and the input of the third divider i4, the output of which is connected to the second input of the EXCLUSIVE OR element 8, the output of the second delay line 13 is connected to the zero input the counter 10, a register 16, the outputs of which are connected to the second input of the comparator block 17. The input of the device is the input of the second driver 13, the output is the output of the storage unit 12.

The first pulse from the output of the pulse shaper 13 (Fig. 2,13), formed on the leading edge of the pulses of the frequency under investigation (Fig. 2, the trigger 7 is set to one state, and the pulses of the highly stable frequency (Fig. 2, fg) arrive at the output of the And element 1 (FIG. 2, 1). Divider 2 provides for obtaining single reference intervals (FIG. 2, 2), which are fed to divider 3, at the output of which a sequence of single and zero voltage levels is formed (FIG. 2, 3) the duration of each level is equal to a single reference inte These impulses are fed to the input of element 8, to the second input of which the impulses of the frequency under investigation are formed by the former 13 and divided twice by the divider 14 (Fig. 2, 14). t in antiphase, so at the end of each half-period at the output of element 8 a pulse is generated, which arrives at the input of element 9, and gives permission to the passage of the counter

10 highly stable pulses, the number of which determines the magnitude of the divergence of the pulses arriving at the inputs of element 8. If this value (Fig. 2, 8) does not reach the specified value Af, the counting result is erased after the end of the pulse arriving at the counter zero input. 10 through line 15 delay. Upon reaching the specified in the register

16 magnitude l, the comparison unit 17 generates a pulse arriving at the control input of the storage unit 12. The memory unit 12 memorizes the voltage generated by the code-voltage converter H, and saves it to the next control pulse. Formation of voltage by converter I 1 code - voltage is produced

from a predetermined value equal to that recorded in register 16. Counter 5 starts counting from the beginning of the first reference period. Impulse generated by the block

17 comparison, the dividers 2, 3 and 14 are zeroed out and the trigger 7 is set to zero, i.e. the prohibition of the passage of a highly stable frequency through the element I I, as well as the resetting of the counter 5 through the time determined by line-delay 4. With the passage of the first next pulse, a new definition of the duration of the time over which the given discrepancy sets in begins.

If during the filling of the counter 5 to a certain set limit, the specified races (at the output

converter 1 code - voltage - zero); pulse generator 6 produces a pulse into the same circuit as the comparison device 17, i.e. the device returns to its original state.

Thus, carrying out the transformation by the proposed method allows to reduce the dynamic error, which provides a higher accuracy of recovery of the transient function.

Claims (1)

Invention Formula A method for converting a frequency transient process into a voltage function, consisting in forming reference intervals from a highly stable frequency, and from the frequency studied — the intervals under study and converting the code formed from the duration of the reference interval and the difference between its duration and the duration of the interval being studied, differing from that, in order to improve the accuracy of conversion, from a highly stable frequency, a single reference interval is formed from the high frequency equal to the nominal frequency period, and the reference and test intervals are formed from single reference intervals and periods of the frequency under study by simultaneously increasing them, respectively, by the value of the single reference interval and the period of the frequency under study until the specified difference in the durations of the reference and test intervals is obtained. Fi.G 13 one g 3 eight JlJHJlJTJnnJTri Ig II ill i and-Ig IL P P A P ltz ill i -t t and-Ig P P ltz J