SU957205A1 - Random process generator - Google Patents

Description

one

The invention relates to computing and can be used in modeling systems with accounting and M random external disturbances in the construction of stochastic computing and simulation devices, as well as in the construction of automated test complexes.

A known generator of a random stream of pulses containing a source of a Poisson stream, a group of elements AND, a probable (1, k) syringe, an element OR, and a decimation block 13.

However, this device does not allow receiving a random pulse process with signals of arbitrary programmable shape.

A known generator of random impulse streams, comprising a clock pulse generator, a cyclic shift register, two OR elements, an inverter, a voltage converter, and a controlled probability element 2.

However, the known device does not allow generating pulse signals with random parameters obeying the given distribution laws and an arbitrary programmable form.

The closest technical

1Q of the essence of the invention is a random pulse generator containing serially connected source of reference voltages, first and second transducer, 5 code-voltage solvers in a polarity modulator whose output is connected to the output of the simulator, the first pulse generator connected to the counting the input of a pulse counter, a second pulse generator connected in series, a frequency divider and a reversible counter, the first register, the outputs of which are connected to the control inputs of the first converter d-voltage and polarity modulator, the second register, the output of which is connected to the control input of a frequency divider interconnected memory block, random number sensor and control unit, the output of the random number sensor connected to the setup inputs of the pulse counter and registers , to the control inputs of which, and to the control input of the reversible counter, the corresponding outputs of the interrupt unit are connected. This simulator is designed to generate random triangular polar impulses, but it does not ol to form a random pulse process with signals of any desired shape, which is limited. the possibilities of its application. The purpose of the invention is to expand the national capabilities by expanding the class of reproducible spectral and statistical characteristics of the generated random processes. By forming pulsed random processes with impulses of arbitrary programmable form. To achieve this goal, a random process generator containing the first block, the output of which is connected to the first input of a random number sensor, the first output of which is connected to the information input of a pulse counter, the counting input of which is connected to the output of the first pulse generator, is a unit of reference voltages the output of which is connected to the first input of the converter; the voltage code, the output of which is connected to the first input of the polarity modulator; the output of which is the generator output; the second input of the module the polarity torus is connected to the first output of the first register, the output of the second register is connected to the first input of the frequency divider, the second input of which is connected to the output of the second pulse generator, the first and second decoders, the address counter, the second block pager, mi,. The input of the first decoder is connected to the output of the pulse counter, and the output of the first decoder is connected to the first setup input of the trigger, the second

the input of the random number sensor and the installation input of the address counter, the inputs of the first and second registers

1 pulses. The input of the first decoder 12 is connected, j to the output of the counter 3 1 mpulsov5 the output of the first cipher, respectively, connected to the second and third outputs of the sensor random numbers, inverse and direct trigger outputs are connected respectively to the inputs of the first and second pulse generators, in addition, the direct output of the trigger is connected the control input of the second memory block, the second setup input of the trigger is connected to the output of the second decoder, the input of which is connected to the output of the address counter and the address input of the second memory block, output the second block memory is connected to the first input of the multiplying unit, the second input of which podklnachen to the second output of the first register, output of multiplying unit is connected to the second input of the code converter - voltage output of frequency divider is connected to the counting input of the counter ADRC-ca. FIG. 1 shows the cxtTMa generator block; in fig. 2 - an example of the implementation of the formed random process. The generator contains the first block 1 of memory, a random number sensor., A counter of 3 pulses, the first geng; pulse generator, block 5 is for: -1-: common voltages, a converter 6 is a voltage code, a modulator 7 polarity, the first register 8 , second rcaster 9, frequency divider 10, second pulse generator P, first decoder 12, second decoder 13, trigger 1 4, address counter 15, second memory block 1b, multiplication block 17. The output of memory block 1 is connected to the first input of a sensor 2 of random numbers, the first input of which is connected to the first input of a counter of 3 pulses. The second input of the counter 3 pulses is connected to the output of the first pulse generator. The output of the unit 5 of the reference voltages is connected to the first input of the converter 6, a voltage code whose output is connected to the first input of the modulator 7 polarity, the second output of the last connected to the first output of the first register 8, the output of the modulator 7 polarity is connected to the output of the device. The output of the second register 9 is connected to the first input of the frequency divider 10, the second input of which is connected to the output of the second generator of the torus 12 is connected to the first installation input of the trigger 1A, the second input of the sensor 2 random numbers and the installation input of the address counter 15. The input of the first register 8 is connected to the second output of the sensor 2 random numbers, and the input of the second register 9 is connected to the third output of the sensor 2 random numbers. The inverse and direct outputs of the trigger are connected respectively to the inputs of the first generator and the second generator of 11 pulses, in addition, the direct output of the trigger 1 is connected to the control input of the second block of 16 m. The second setup input is triggered AND connected to the output of the second decoder 13, the input of which is connected to the output of the counter 15 of the address and the address input of the second 16-mA unit. The output of the second memory block 16 is connected to the first input of the multiplication unit 17, the second input of which is connected to the second output of the first register 8, the output of the multiplication unit 17 is connected to the second input of the converter 6 code - voltage. The output of the frequency generator 10 is connected to the counting input of the counter 15 of the address. Unit 1 is intended for storing codes that determine the type and numerical characteristics of the probability distribution functions of the parameters of a pulsed random process. The random number sensor 2 is designed to generate random amplitude, duration, and interval between pulses, subject to distribution functions, the codes of which are stored in block 1, pulse counter 3 serves to store a random code defining the interval between the pulses of the process being formed. and to convert this code to a time interval. The generator k is designed to generate clock pulses. Unit 5 of reference voltages serves to set the boundary values of the amplitudes of the pulse signals generated by the simulator. Transducer 6 voltage code is designed to convert voltage into codes, the sequence of which determines the shape of the pulse at the output of the simulator. The polarity modulator 7 provides pulsed signals of positive or negative polarity. The first register 8 serves to memorize the code determining the amplitude and polarity of the next pulse signal. The second register 9 serves to memorize the code defining the duration of the next pulse. Frequency divider 10 is designed to set the speed of filling the address counter 15 with clocks. The second pulse generator 11 provides a stream of clock pulses for filling the address counter 15. The first decoder 12 is designed to generate a signal indicating the end of the formation of the interval between pulses. The second decoder is designed to generate a signal indicating the end of the formation of a pulse. The trigger is designed to generate signals permitting the operation of the first generator k and the second generator 11 pulses. Counter 15 generates a sequence of addresses for reading the codes of the second memory block 16. The second memory block 16 is designed to store the ordinate codes of the pulse signal of the desired shape. The multiplication unit 17 generates codes defining the values of the pulse signal at discrete points in time. The device works as follows. Each cycle of operation begins with the fact that for the next pulse of the output stream, a set of values of random parameters is generated (durability, amplitude, polarity of the pulse, interval between pulses). The values of the process parameters are formed according to given distribution laws, the codes of which are stored in the first memory block 1. From the output of the sensor 2 random numbers, the generated values of the process parameters are fed to the counter of 3 pulses, registers 8 Let trigger 1 be in the initial (single) state. The enable signal from the output of the trigger 14 is fed to the input of the second generator 11 of pulses and to the control input of the second memory block 16, permitting the reading of information. The inverse output of the trigger 1 is connected to the input of the first generator 4 pulses. With a single state

trigger 1 this signal prohibits the operation of the generator 4.

The value of the random code recorded in the second register 9 determines the coefficient of resetting of the frequency divider 10. This is provided for each pulse duration filling the address counter 15 with the corresponding frequency obtained by dividing the frequency of the pulse flow from the second pulse generator 11. Codes from the output of the counter 15 addresses are fed to the first input of the second memory block 16. Thus, sequential reading of the ordinate codes of the pulse signal of the programmed form with a frequency inversely proportional to the code value of the pulse duration is provided. Codes read from the second memory block 1b are supplied as a first operand to the first input of the multiplication unit 17. The second input of this block receives the amplitude code of the generated pulse, entered into the first register 8. At the output of the multiplication unit 17, the ordinate values of the pulsed signal of the required shape are formed, proportional to the amplitude of the imyuls generated

At the output of the unit 5 of the reference voltages, a voltage level is pre-set equal to the maximum amplitude of the generated pulses. In accordance with the codes from the output of the multiplier block 17, the output signal of the converter 6 is a voltage-voltage signal that forms an analog signal of the required shape with an amplitude corresponding to the code of the amplitude of the pulse being generated.

The modulator 7 of the polarity passes the signal, from the output of the converter 6 the code - the voltage at the output of the device either keeps its polarity or changes it to the opposite one in accordance with the codes recorded in the first register 8.

Upon completion of the formation of a single pulse (after the counter reaches the maximum value), a signal is generated at the output of the second decryptrer 13, setting the trigger 14 to the zero state. At the same time, at the direct output of a trigger-1h signal, a signal is generated, which is canceled by the second pulse generator 11 and the reading of information from the second memory block 16.

At the inverse of the trigger output 1A, a signal is generated enabling the operation of the first pulse generator. Thus, the formation of the interval between pulses begins. Using the generator 4 and the counter 3 pulses organized the conversion of a random code recorded in the counter 3 pulses in the time interval between pulses.

Upon the completion of the interval formation (when the counter reaches 3 pulses of the zero state), the output of the first decoder 12 generates a signal of the end of the formation of the interval between pulses.

This signal is fed to the second control input of the sensor 2 random numbers. After this, the generation and transfer into registers 8, 9 and the counter of 3 pulses of new values of process parameters occurs. The same signal sets the address counter 15 to the first state and the initial (single) state of the trigger 14. Thus, the next cycle of forming the output random process begins.

It should be noted that in order to increase the stability of the characteristics of the formed process as a unit

5 reference voltages required

use a stabilized voltage source. The polarity modulator 7 is based on an operational amplifier with inverting and non-inverting inputs.

Claims (3)

The technical and economic efficiency of the invention is determined by the fact that it provides, in comparison with the known devices, the possibility of forming random external influences, which are pulsed processes with signals of complex shape, which is especially important when modeling and testing complex technical systems, and also improving the accuracy of formation random pulsed signals of complex shape due to the use of digital methods of generating the output process, as well as the possibility of adjusting the type of output th process depending on the characteristics of the subject or object being modeled. The invention contains a random process generator, which holds the first memory block, the output of which is connected to the first input of a random number drive, the first output of which is connected to the information input of a pulse counter, the counting INPUT of which is connected to the output of the first pulse generator, the reference voltage block The output of which | GO is connected to the first input of the converter; the code is the voltage, u | x, which is connected to the first input of the modulator, the output of which is the generator output, the second input of the modulator is connected to the first output the first register, the output of the second register is connected to the first input of the frequency separator, the second input of which is connected to the output of the second pulse generator, characterized in that, in order to expand the functionality by expanding the class of reproducible spectral and statistical characteristics of the random processes generated, the first and the second decoders, the trigger, the address counter, the second memory block, the multiplication block are entered, the input of the first descriptor is connected to the output of the pulse counter, and the output of the first The encoder is connected to the first installation input of the trigger, the second input of the random number sensor and the installation input of the address counter, the inputs of the first and second registers are connected respectively to the second and third outputs of the random number sensor, the inverse and direct outputs of the trigger are connected respectively to the inputs of the first and second pulse generators , the direct output of the trigger is connected to the control input of the second memory block, the second setup input of the trigger is connected to the output of the second decoder, the input of which is connected the output of the address counter and the address input of the second memory block, the output of the second memory block is connected to the first input of the multiplication unit, the second input of which is connected to the second output of the first register, the output of the multiplication unit is connected to the second input of the converter code - voltage, frequency divider is connected to counting input of the address estimator. Sources of information taken into account in the examination 1. USSR author's certificate number, cl. G 06 F) / 02, 1975. 2. USSR author's certificate № $ 11679, cl. H 03 K, 1976. 3. Authors certificate of the USSR W 517018, cl. G About F 1/02, 1976 (prototype).